JPS60117755A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the realization of desired characteristics by reducing the area and dimensions of elements by a method wherein a single crystal semiconductor region filling a recess formed in a substrate is formed and then made as one region for a semiconductor element. CONSTITUTION:An Si oxide film 28 is formed on the surface of the P type Si substrate 27, and this film is selectively etched by the use of a photo resist as a mask. Next, using the anisotropic dry etching method, the recess 29 is formed by selectively etching the substrate to a depth of approx. 3-4mum. Thereafter, an Si oxide film 30 is formed on the surface of the recess by using the vapor phase growing method and the like. Next, this oxide film is etched by the anisotropic dry etching method so that the bottom of the recess becomes exposed, and a high concentration layer 31 is formed by diffusing an N type impurity to the exposed surface. Then, an N type epitaxial layer 32 is selectively formed so as to fill the recess, and an Si oxide film 33 is formed over the entire surface.

Description

[Detailed description of the invention] (Technical field of invention) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.

The present invention relates to a method of manufacturing a semiconductor device in which transistors such as P- and N-channel transistors, insulated gate transistors, and bipolar transistors having different conductivity polarities and different control methods are formed within a single semiconductor substrate.

(Prior Art) For example, in the manufacturing method of complementary insulated gate transistors, as shown in FIG.
A P-chMU in which a well region 3 is formed and a P-type source and drain region 5° 5' is formed in an N-type substrate region.
s) transistor and N-chMUs) transistor having Ng source and drain regions 4.4' in the P-well region 3, respectively. Note that 2 is an insulating film, and 6°6' is a gate pole. Other methods include forming an N-well on a P-type substrate, and forming both a P-well and an N-well.

In any of the above manufacturing methods, when forming the well region, the diffusion depth of the well region is determined by the breakdown voltage.

Approximately 4 to 6 μm is required due to the relationship between U, Chi, P, etc. As a result, transverse waves in the well region are generated, resulting in a drawback that a large distance between elements must be provided.

Furthermore, when an insulated gate transistor and a bipolar transistor are used together, as shown in FIG. After forming the insulating isolation region 15 and the P-well region 14, the bipolar part base region 17. P-ch) Source and drain regions 16°16' of transistor section and emitter and collector contact regions 19 #19' of bipolar section
*N-ch F transistor section source, drain 18
．． It formed 18'. Note that 10 is an electrode for each region. Even in this method, the conditions for forming the p-+yel region 14 are at a high temperature for several hours to more than ten hours.

As a result, the N-type buried layer 13 in the bipolar part is overlaid, which lowers the withstand voltage of the bipolar part. It had the disadvantage that it itself became very large.

In this way, in the conventional method, in order to obtain a desired device with desired characteristics, it was necessary to sacrifice an increase in the device area. It is an object of the present invention to provide a method for manufacturing a dam that achieves the desired characteristics by reducing one dimension.

(Structure of the Invention) The present invention is characterized in that by selectively removing the substrate, a single crystal semiconductor region is formed to fill the gap, and this is used as a region for a semiconductor element.

According to this method, horizontal spread due to diffusion can be prevented,
Desired device characteristics can be obtained by the highly viscous impurity region and the insulating film.

(Example) Hereinafter, the invention will be explained in detail using the drawings.

Fig. 3 shows an embodiment of the non-invention. First, Fig. 3(a)
A P-type silicon substrate 27 with an impurity concentration of 2 to 3XIQ Cm is prepared as shown in FIG.
The oxide film 28 is selectively etched using a photoresist as a mask. Next, the substrate 27 is etched using an anisotropic dry etching method. Four portions 29 are formed by selectively etching to a depth of about 4 μm. Thereafter, a silicon oxide film 30 of 0.5 to 1 μm is formed on the surface of the recess 29 using a vapor phase growth method or the like.
The modified film 30 is formed to a certain thickness using a zero-order anisotropic drying and drying process so that the bottom of the recess 29 is exposed.
etching. N-type impurities are diffused into the exposed surface to form a high concentration layer 31 of about 1 to 5XIQ Cm.

Next, as shown in FIG. 3(b), an N-type epitaxial layer 32 is selectively formed to fill the recess 29.
As a method for selectively forming the epitaxial layer 32, epitaxial growth is performed under reduced pressure using a mixed gas of 5iH2C12-HUl-H2. Then, no silicon layer is formed on the silicon oxide film 28, and single crystal silicon is formed. An epitaxial layer is formed only on the portion. Using the above method.

An N-type epitaxial layer 32 of about 1X10 Cm is formed in the recess 29, and a silicon oxide film 33 is formed on the entire surface.

Thereafter, a normal C-M (JS) transistor formation process is used to form the source and drain regions 34, 34' of the P-ch transistor in FIG. 3 (as shown in C1).

N-ch) transistor source and drain regions 35
．． 35' are formed respectively, and gate oxide films 36 and 36 are formed.
' to form each electrode 37.

This forms a complementary MUS) transistor.

Although the drawing shows a C-MOS transistor with a metal gate, it goes without saying that a Si (silicon) gate type can also be used. An epitaxial layer may also be used.

According to this method, the transverse waves in the well region 32 are
(approximately 5 μm) can be ignored, and in addition, the source,
Since the margin (approximately 1 to 2 .mu.m) between the drain region 34, 34' and the well 11 region 32 can be ignored, the device can be reduced in size to a greater extent than in the past. Further, a high concentration buried layer 31 is provided between the substrate 27 and the epitaxial layer 32.
Due to this, parasitic transistors do not occur,
It also has the advantage of being extremely resistant to latch-up.

FIG. 4 shows another embodiment of the present invention.
), the impurity concentration is 2~3X10"cm-
A silicon oxide film 42 is formed on a P-type silicon substrate 41 of approximately 0.3 μm to a thickness of approximately 0.5 to 1 μm, and the oxide film 42 is selectively etched using a 7-photoresist as a mask.
Next, using an anisotropic dry etching method, the substrate 41 is selectively etched to a depth of about 3 to 4 μm to form recesses 43, 43', 43''.

Thereafter, a silicon oxide film 44 of about 0.5 to 1 μm is formed on the surfaces of the recesses 43 to 43'' using a vapor phase growth method or the like.
Next, using an anisotropic dry etching method, the recesses 43-43"
(by etching the oxide film on the bottom of the oxide film) the silicon surface is exposed. Mist coming out in the recesses 43, 43' 5
N-type impurities are diffused into the i-plane to form heavily doped buried layers 45, 45' with a thickness of about 1 to 5.times.10 cm.sup.-3. Recess 43
No high concentration buried layer is formed on the silicon exposed surface in ".

Next, as shown in FIG. 4(b), N-type epitaxial layers 46, 46' and 46'' having a thickness of about 1×10 15 cm −3 are selectively formed to fill the four portions 43 - 43 ″.

As for the formation method, the method explained in FIG. 3 can be used. Next, a silicon oxide film 47 is formed on the entire surface.

Thereafter, the source and drain regions 48 and 48' of the p-ch transistor in FIG. 4 (as shown in C1) and the base region 49 of the bipolar part are formed at the same time using the usual manufacturing method of MOS transistors and bipolar transistors. Then, the source and drain regions 50 and 50' of the N-ch transistor, the emitter and collector contact regions 51 and 51' of the bipolar part are formed.

Then, gate oxide films 52, 52' are formed to form each metal electrode (23). As a result, a half-quadruple device in which a J, MOS transistor and a bipolar transistor are formed on the same substrate is manufactured.

Although FIG. 1 shows a metal gate M(JS) transistor, it goes without saying that a MOS1-MOS transistor may also be used. Also, the mold of 4 can be replaced. Further, other elements that do not require a buried region are formed in the N-type epitaxial region 46''.

According to this embodiment, the transverse waves in the well region 46 are !
1) (approximately 3 to 5 μm), transverse waves in the insulating area (7 to 5 μm)
10 μm), and the transverse wave in the N1 cedar embedded region 45' is 9 (about 4
~6μm) can be ignored, and the source and drain 48
．． 48' and yel146 and Zimmerschiff (l~2μm
The size of the device is also negligible, making it possible to significantly reduce the size of the device compared to the conventional method. Moreover, the presence of the N+ type buried layers 45, 45' between the substrate 41 and the epitaxial layer 46, 46' prevents the generation of parasitic transistors and has the advantage of being highly resistant to latch-up. have

[Brief explanation of drawings]

1 and 2 are cross-sectional views of elements formed by conventional manufacturing methods, respectively. Figure 3 (al to (C)
4(a) is a process sectional view showing one embodiment of the present invention.
) to fc) are process cross-sectional views showing other embodiments. 1.11, 27.41 are P-type blast rates, 12.4
6-46", 32 is epitaxial layer, 13.45.4
5' is an N-type buried layer, 3 and 14 are P-weJ3 regions, 1
5 is a P+ type insulation region 5.5'. 16.16', 34.34', 48.48', 49 are P
Swelling diffusion layer, 4.4', 35.35', 50.50'. 51.51' is an N+ type diffusion layer, 6, 20, 37° 53 is a metal electrode, 2.28.30, 42.44° 47 is an oxidized layer.
29.43-43" is a concave portion. l Fig. f Fig. 1V Fig. -i

Claims (1)

[Claims] A step of selectively removing a semiconductor substrate to provide a recess, a step of forming an insulator on the side surfaces of the recess, a step of providing a high concentration region on the bottom of the recess, and a step of forming a semiconductor region to fill the recess. 1. A method of manufacturing a semiconductor device, comprising: a step of forming an element region in the semiconductor region; and a step of forming an element region within the semiconductor region.