JPH01155651A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a leakage current due to a parasitic effect between source and drain regions by a method wherein a gate electrode is formed into a form longer than a channel length at the boundary between a gate insulating film and an isolation insulating film. CONSTITUTION:A gate electrode 18 has a region 19 formed on a gate insulating film 8 in an N-type conductivity MOS field-effect transistor region 15 and a region 20 elongated outside on a thick isolation insulating film 7. The pattern of the electrode 18 is determined in such a way that the length l2 of a position of the electrode 18 which crosses the end part of the region 15, that is, the length l2 of the electrode 18 at the boundary part between the films 8 and 7 becomes longer than a channel length l1. Thereby, the interval l2 between source and drain regions 10 at the boundary part becomes longer than the channel length l1 and the path of a leakage current at the boundary part is long.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device suitable for a BiCMO8 integrated circuit device in which bipolar transistors and MOS field effect transistors are mixed.

[Prior Art] Recently, a semiconductor integrated circuit device having a so-called B i CMO8 configuration in which bipolar transistors and CMOS field effect transistors are mixed has been attracting attention.

This B iCMO3 integrated circuit device utilizes the advantages of both the high-speed operation of bipolar transistors and the high density and low power consumption of MOS field effect transistors. It is thought that this will become a new trend in semiconductor integrated circuit devices in the future.

On the other hand, from the perspective of manufacturing a BiCMOS integrated circuit device, the process of forming a bipolar transistor and the process of forming a MO
Since the process for forming the S-type field effect transistor is almost independent, there are problems in that the number of processes is large, and as a result, the period required for manufacturing is long and the product yield tends to be poor. Therefore, in manufacturing BiCMO3 integrated circuit devices, reducing the number of required steps has become an important issue.

FIG. 3 is a plan view showing a semiconductor integrated circuit device made of B iCMO3li, and FIG. 4 is a longitudinal cross-sectional view taken along the line II in FIG. 3. NPN bipolar transistor region 14, N conductive MOS type field effect transistor region 15, and P conductive M
An O3 type field effect transistor region (not shown) is surrounded and partitioned by a thick insulating film 7, and a B iCMO8
It has been completed.

An N-type buried diffusion region 2 is formed in a P-type semiconductor substrate 1 made of single crystal silicon. The top of this N-type buried diffusion region 2 is NP.
N bipolar transistor region 14 or P conductive MO9 type field effect transistor region (not shown). Also,
A P-wall buried diffusion region 3 is also formed in the P-type semiconductor substrate 1, and above this region is an N-conducting MOS type field effect transistor region 15 or a P-type diffusion region 5 for insulating and separating each transistor.

The N-type epitaxial layer 4 is formed closer to the surface of the P-type semiconductor substrate 1 than the N-type buried diffusion region 2 and the P-wall buried diffusion region 3 are. P type well region 6 is formed on P type buried diffusion region 3 of MO8 type field effect transistor regions 1 and 5 in N type epitaxial layer 4 . A thick insulating film 7 for element isolation is formed on the surface of the N-type epitaxial layer 4, and the thick isolation insulating film 7 partitions element forming regions such as the transistor regions 14 and 15.

A gate insulating film 8 is formed on the surface of the P-type well region 6, and a gate electrode 9 is formed on this gate insulating film 8 by patterning polycrystalline silicon or the like. This gate electrode 9 is formed so as to extend from above the gate insulating film 8 to above the thick insulating film 7, and by implanting ions into the substrate using the gate electrode 9 as a mask,
A pair of N-type source/drain regions 10 are formed near the surface of the P-type well region 6 . This source/drain region 10 is formed in a region surrounded by a thick insulating film 7 except for the region immediately below the gate electrode 9.

In addition, an N-type epitaxial layer 4 on the N-type buried diffusion region 2
A P type base region 11 is disposed near the surface of the P type base region 11, and an N type emitter region 1 is disposed within this P type base region 11.
2 is provided. In the epitaxial layer 4 on the N-type buried diffusion region 2, an N-type diffusion region 13 is formed in the vicinity of the P-type base region 11, from which the collector electrode is taken out.

5 and 6 are cross-sectional views showing a semiconductor integrated circuit device with an isoplanar structure that reduces the number of manufacturing steps compared to the conventional semiconductor integrated circuit device shown in FIG. No. 47-31078). This Fig. 5 is a cross-sectional view corresponding to the I-I line in Fig. 3, and Fig. 6 is a sectional view corresponding to the line I-I in Fig. 3.
It is a sectional view corresponding to a line. Conventional BiC shown in Figure 5
In the MO3 integrated circuit device, the P-type diffusion region 5 shown in FIG. 4 is omitted, and the insulation isolation between each transistor is achieved by making the thick insulating film 7 shown in FIG.
This is done by forming a thick isolation insulating film 17 that reaches up to the wall-buried diffusion region 3.

The manufacturing problem when applying this isoplanar film is how to efficiently obtain a thick oxide film (isolation insulating film 17). The semiconductor integrated circuit device shown in FIG. 4 has a thickness of about 1.1 μm by heating to 1000° C. for about 6 hours in an H2-○2 atmosphere at normal pressure and oxidizing it.
An insulating film 7 of silicon dioxide having a thickness of m can be obtained. On the other hand, in the conventional example shown in FIG. 5, the required thickness of the isolation insulating film 17 of silicon dioxide is about 1.5 μm, and if it is attempted to form this isolation insulating film 17 under the above conditions, it will take about 11 hours. Oxidation time is required. Therefore, the oxidation conditions were changed to oxidation under a pressure of approximately 5 atmospheres, and by heating to 950°C under this pressure, the isolation insulating film 1
7 was obtained in about 2 hours of processing time.

[Problems to be Solved by the Invention] Incidentally, in the device shown in FIG.
The P-type diffusion region 5 is formed to surround the periphery of the type well region 6, and this P-type diffusion region 5 prevents parasitic effects in the N-conducting MO3 field effect transistor.

However, in the conventional isobrainer structure semiconductor integrated circuit device shown in FIG. When the surface impurity concentration of No. 6 is low, a weak inversion state occurs between the source and drain regions due to parasitic effects, and leakage current may flow.

In other words, when the isolation insulating film 17 is formed by oxidation under pressure as described above, compared to oxidation at normal pressure,
Boron, which is a P-type impurity for forming the P-type well region 6, is easily incorporated into the oxide film (isolation insulating film 17).

Therefore, the surface impurity concentration of the P-type well region 6 is reduced at the boundary 16 (indicated by O in the figure) between the gate insulating film 8 and the thick isolation insulating film 17 shown in FIG. Therefore, there is a problem in that leakage current tends to flow between the source and drain regions 10 using this boundary portion 16 as a path.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor integrated circuit device that can lengthen a leakage current path and reduce leakage current by optimizing the shape of a gate electrode.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes: a first conductivity type semiconductor region; an isolation insulating film formed on the surface of the semiconductor region to partition an element region; a gate insulating film formed, a gate electrode having a region formed on the gate insulating crotch and an extension region extending over the isolation insulating film; a source/drain region of a second conductivity type whose formation region is defined, and the gate electrode has a length at a boundary between the gate insulating film and the isolation insulating film that is longer than the channel length. shall be.

[Operation] In the present invention, the length of the gate electrode formed on the gate insulating film and the isolation insulating film at the boundary between the gate insulating film and the isolation insulating film is longer than the channel length. Since the impurity concentration on the surface of the first conductivity type semiconductor region at this boundary tends to be low, leakage current tends to flow at this boundary. However, as mentioned above, the length of the gate electrode at this boundary is longer than the channel length, and therefore the interval between the source and drain regions whose formation region is partitioned by the gate electrode is also longer than the channel length at this boundary. Since it is longer, the leakage current path becomes longer than before, and the leakage current is reduced.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view showing a portion of an N-conducting MO8 type field effect transistor in a semiconductor integrated circuit device according to a first embodiment of the present invention. The device shown in Figure 1 is B iCMO
The N-conducting MOS type field effect transistor region 15 and other elements are insulated and separated from each other by a thick isolation insulating film.

In other words, this N-conducting MO9 type field effect transistor region 15 has a gate insulating film 8 and a thick isolation insulating film 7.17.
Its planar shape is defined by the boundary between the two (see FIGS. 4 to 6).

A gate electrode 18 is provided at the center of the N-conducting MOS type field effect transistor region 15, and within the region 15, regions 21 and 22 for forming source and drain electrodes are provided in parallel to this electrode 18. The gate electrode 18 is
It has a region 19 formed on the gate insulating film 8 in the N-conducting MO3 type field effect transistor region 15 and a region 20 extending over the thick isolation insulating films 7 and 17. The source/drain region 10 (see FIGS. 4 and 5) of the MO3 field effect transistor is formed by forming the gate electrode 18 and the thick isolation insulating films 7, 17, and then forming the gate electrode 18 and the insulating films 7, 17. Although formed by ion implantation into the substrate as a mask, the source/drain region 10 is a transistor region 15 surrounded by thick insulating films 7 and 17.
It is formed in a region within the gate electrode 18 that is not covered by the gate electrode 18. Therefore, the channel length 11 is determined by one region of the gate electrode 18. Further, in this embodiment, the length 2 of the position of the gate electrode 18 that crosses the end of the N-conducting MOS field effect transistor region 15, that is, the boundary between the gate insulating film 8 and the isolation insulating films 7 and 17 is Gate ring f! The length ρ2 of 18 is the channel length! The pattern of the gate electrode 18 is determined so that it is longer than the gate electrode 21.

Therefore, by forming the gate electrode 18 in such a pattern, the source/drain region 1 formed by ion implantation using the gate electrode 18 as a mask can be formed.
0 are spaced apart according to the pattern of the gate electrode 18. Therefore, the distance (2) between the source and drain regions 10 at the boundary is longer than the channel length ff1l, and the leakage current path at the boundary is long.

P-type well region 6 at the end of transistor region 15
Since the surface impurity concentration (see FIG. 6) is low, leakage current tends to flow between the source and drain regions 10 at the boundary between the gate insulating film and the isolation insulating film from the viewpoint of impurity concentration. However, in this embodiment, the distance 12 between the source and drain regions 10 at this boundary (the end of the transistor region 15), that is, the leakage path length is
The channel length is longer than 11. Since the magnitude of leakage current is inversely proportional to the path length of the leakage current, it is possible to reduce the leakage current more than in the conventional case where the path length in the region where leakage current easily flows is the same as the channel length 11. Can be done.

FIG. 2 is a plan view showing a part of a semiconductor integrated circuit device according to a second embodiment of the present invention. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted. N conductive M
The OS type field effect transistor region 23 has convex portions 24 projecting outward at both ends of the gate electrode 18 on the extension region 20 side. Since the edge of this convex portion 24 is located within the extension region 20 of the gate electrode length (2), the N-conducting MOS
The length 12 of the gate electrode 19 at a position crossing the end of the type field effect transistor region 20, that is, the leakage path length is longer than the channel length ρl. Therefore, also in this second embodiment, the path length of the leakage current is longer than in the conventional case, and the leakage current can be reduced. Note that this second
In the embodiment, the channel width (spacing between regions 20)
There is an advantage that the leakage current can be reduced by lengthening the leakage current path without reducing the leakage current.

Although the BiCMO3 integrated circuit device has been described above as an example, it goes without saying that the present invention can also be applied to the case where a MOS field effect transistor is formed in a single crystal silicon substrate.

[Effects of the Invention] As explained above, according to the present invention, since the gate electrode has a shape that is longer than the channel length at the boundary between the gate insulating film and the isolation insulating film, the gate electrode has a shape that is longer than the channel length at the boundary between the gate insulating film and the isolation insulating film. Therefore, the path length of the leakage current becomes longer.
Leakage current due to parasitic effects between the source and drain regions of a MOS field effect transistor can be reduced.

[Brief explanation of the drawing]

1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. The figure is B1CM
4 is a plan view showing a semiconductor integrated circuit device with an OS configuration, FIG. 4 is a vertical sectional view taken along line I-I in FIG. 3, and FIG. 5 is a plan view showing a semiconductor integrated circuit device with a conventional isobrain structure.
- A cross-sectional view corresponding to the I line, Figure 6 is the same as in Figure 3 -
It is a cross-sectional view corresponding to the line. 1. P type semiconductor substrate, 2; N type buried region, 3; P type buried diffusion region, 4; N type epitaxial layer, 5; P type diffusion region, 6; P type well region, 7°17; thick isolation insulating film,
8; Gate insulating film, 9° 18; Gate electrode, 10; N type source drain region, 11; P type base region, 12; N
type emitter region, 13; N type diffusion region, 14; NPN bipolar transistor region, 15.23; N conductive MOS
type field effect transistor region, 16; boundary between gate insulating film and isolation insulating film, 19; region, 20; extension region, 2
4; Convex part

Claims (1)

[Claims] a first conductivity type semiconductor region; an isolation insulating film formed on the surface of the semiconductor region to partition an element region; a gate insulating film formed on the element region; a region formed on the gate insulating film; A gate electrode having an extension region extending over an isolation insulating film, and a second conductivity type source/drain region whose formation region is defined within the element region by the isolation insulating film and the gate electrode. The semiconductor integrated circuit device is characterized in that the length of the gate electrode at a boundary between the gate insulating film and the isolation insulating film is longer than the channel length.