KR950006490B1 - Making method of transistor - Google Patents

Making method of transistor Download PDF

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Publication number
KR950006490B1
KR950006490B1 KR1019920013045A KR920013045A KR950006490B1 KR 950006490 B1 KR950006490 B1 KR 950006490B1 KR 1019920013045 A KR1019920013045 A KR 1019920013045A KR 920013045 A KR920013045 A KR 920013045A KR 950006490 B1 KR950006490 B1 KR 950006490B1
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South Korea
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forming
impurity layer
concentration
layer
type impurity
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KR1019920013045A
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Korean (ko)
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KR940003074A (en
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최종문
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금성일렉트론주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

The method includes the steps of sequentially forming a high concentration of N impurity layer (12) and a P epitaxial layer (13) on a semiconductor substrate (11), etching the layers (12,13) except a device formation area, forming a low concentration of N impurity layer (14) on the layer (13), implanting and heat-treating O2 ions thereinto to form an oxide film (17) at a middle depth portion of both sides of the layer (12), forming a gate insulating film (18) thereon to form a first and second gate electrodes (20,19), and forming a high concentration of P impurity layer (21) into the layer (16), thereby forming a horizontal transistor on a vertical transistor to reduce the chip size.

Description

반도체 장치의 트랜지스터 제조방법Method of manufacturing transistor in semiconductor device

제1도는 종래의 평면형 트랜지스터를 설명하기 위한 평면도 및 단면도.1 is a plan view and a cross-sectional view for explaining a conventional planar transistor.

제2도는 종래의 수직형 트랜지스터를 설명하기 위한 평면도 및 단면도.2 is a plan view and a cross-sectional view for explaining a conventional vertical transistor.

제3도는 본 발명의 제조를 설명하기 위한 공정 단면도.3 is a process cross-sectional view for explaining the production of the present invention.

제4도는 제3f도를 나타낸 평면도.4 is a plan view of FIG. 3f.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 기판 12 : 고농도 N형 불순물층11 substrate 12 high concentration N-type impurity layer

13 : P형 에피층 14,16 : 저농도 N형 불순물층13: P type epi layer 14,16: low concentration N type impurity layer

15 : 산화막 17 : 필드 산화막15: oxide film 17: field oxide film

18 : 게이트 산화막 19 : 제1게이트18 gate oxide film 19 first gate

20 : 제2게이트 21 : 소오스/드레인20: second gate 21: source / drain

본 발명은 반도체 장치의 트랜지스터(Transistor)에 관한 것으로, 특히 피모스(PMOS)와 엔모오스(NMOS)를 하나의 소자영역에 형성시켜 고집적을 요하는 메모리 셀(Memory Cell)에 적당하도록 한 반도체 장치의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device. In particular, a semiconductor device in which a PMOS and an NMOS are formed in one device region so as to be suitable for a memory cell requiring high integration. The present invention relates to a transistor manufacturing method.

종래의 평면형 트랜지스터(Lateral Transistor)는 제1도와 같이 제1b도는 제1a도의 "a-a"선을 절단한 것으로, 기판(1)상부 양측에 필드산화막(Field Oxide) (2)을 성장하여 활성영역(Active Region)과 필드 영역을 정의한 후 활성 영역의 기판(1) 표면에 게이트 산화막(3)을 성장한다.In the conventional planar transistor (Lateral Transistor), as shown in FIG. 1, FIG. 1b is a cut line "aa" of FIG. 1a, and a field oxide film 2 is grown on both sides of the substrate 1 to form an active region. After defining the active region and the field region, the gate oxide film 3 is grown on the substrate 1 surface of the active region.

다음, 게이트 산화막(3) 위에 게이트(4)를 패터닝(Patterning)하고, 게이트(4)양측에 이온을 주입하여 소오스/드레인(5)을 형성한다.Next, the gate 4 is patterned on the gate oxide film 3, and ions are injected to both sides of the gate 4 to form the source / drain 5.

종랭의 수직형 트랜지스터(Vertical Transistor)는 제2도와 같이 제2b도는 제1a도의 "b-b"선을 절단한 것으로, 기판(도면중에 도시하지 않음)위에 n,p,n형 영역(68)을 일정폭으로 패터닝하여 차례로 형성한 후 전표면에 산화막(9)을 형성하고, 산화막(9)표면 우측에 게이트 전극(10)을 형성한다.Vertical vertical transistors of the vertical type are cut along the "bb" line of FIG. 1A in FIG. 2B as in FIG. 2, and the n, p, n-type regions 68 are fixed on the substrate (not shown). After patterning by width, the oxide film 9 is formed on the entire surface, and the gate electrode 10 is formed on the right side of the surface of the oxide film 9.

그러나, 이와같은 종래의 기술에 있어서는 하나의 트랜지스터가 큰 면적을 차지하므로써 고집적화 하기가 어려워 메모리 셀을 축소하기가 어렵다.However, in such a conventional technique, since one transistor occupies a large area, it is difficult to be highly integrated and it is difficult to shrink a memory cell.

본 발명은 이와같은 종래의 결점을 감안하여 안출한 것으로, 피모스와 엔모스를 평면과 수직으로 하나의 소자 영역에 형성하여 메모리 셀을 고집적화 할 수 있도록 하는 반도체 장치의 트랜지스터 제조방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and provides a transistor manufacturing method of a semiconductor device in which PMOS and N-MOS are formed in one element region perpendicular to a plane to enable high integration of memory cells. There is a purpose.

이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

제3도는 본 발명의 공정단면도로, 제3a도와 같이 반도체 기판(P형)(11) 전표면에 고농도 N형 이온을 주입하여 고농도 N형 불순물층(12)을 형성하고, (b)와 같이 고농도 N형 불순물층(12) 위에 P형 에피층(13)을 형성한 후, (c)와 같이 소자 형성영역을 정의하고 소자 형성영역을 제외한 영역의 P형 에피층(13)을 제거하고 고농도 N형 불순물층(12)을 중간 깊이까지 식각하여 소자형성영역이 돌출되게 한다.FIG. 3 is a process cross-sectional view of the present invention. As shown in FIG. 3A, a high concentration N-type impurity layer 12 is formed by implanting high concentration N-type ions into the entire surface of a semiconductor substrate (P-type) 11, as shown in (b). After the P-type epitaxial layer 13 is formed on the high concentration N-type impurity layer 12, the device formation region is defined as shown in (c), and the P-type epitaxial layer 13 in the region except the device formation region is removed and the high concentration is formed. The N-type impurity layer 12 is etched to an intermediate depth so that the device formation region protrudes.

(d)와 같이 P형 에피층(13)상부에 저농도 N형 이온을 주입하여 저농도 N형 불순물층(14)을 형성하고, 저농도 N형 불순물층(14)과 식각된 고농도 N형 불순물층(12)에 산소이온주입하고 열처리한다.As shown in (d), a low concentration N-type impurity layer 14 is formed by implanting low concentration N-type ions onto the P-type epitaxial layer 13, and a high concentration N-type impurity layer etched with the low concentration N-type impurity layer 14 ( Inject oxygen ion into 12) and heat treatment.

그러므로 해서 저농도 N형 불순물층(14)의 중간부위에 산화막(15)을 형성하여 저종도 N형 불순물층을 상하 저농도 N형 불순물층(14,16)으로 구분하고, 식각된 고농도 N형 불순물층(12)의 양측 중간부위에는 필드산화막(17)을 형성한다.Therefore, the oxide film 15 is formed in the middle portion of the low concentration N-type impurity layer 14 to divide the low-density N-type impurity layer into upper and lower low-concentration N-type impurity layers 14 and 16, and the etched high concentration N-type impurity layer Field oxide films 17 are formed at the intermediate portions on both sides of the 12. As shown in FIG.

이어서, (f)와 같이 소자형성영역을 포함한 반도체기판(11) 위에 게이트산화막(18)을 형성하고, 소자형성 영역의 일측면과 소자형성 영역의 상측 일부에 NMOS소자의 제1게이트 전극(20), 소자형성영역 상측의 중간영역에 PMOS 소자의 제2게이트 전극(19)을 형성한다.Subsequently, a gate oxide film 18 is formed on the semiconductor substrate 11 including the device formation region as shown in (f), and the first gate electrode 20 of the NMOS device is formed on one side of the device formation region and a part of the upper portion of the device formation region. ), A second gate electrode 19 of the PMOS device is formed in the intermediate region above the device formation region.

그리고, 제1, 제2게이트 전극(20,19)를 마스크로 하여 노출된 저농도 N형 불순물 층(16) 표면에 고농도 P형 이온을 주입하여 소오스/드레인(21)영역을 형성하므로써 평면형 트랜지스터를 제조한다.The planar transistor is formed by forming a source / drain 21 region by implanting high concentration P-type ions into the exposed low concentration N-type impurity layer 16 using the first and second gate electrodes 20 and 19 as masks. Manufacture.

여기서 NMOS소자는 제1게이트 전극(20), 소오스/드레인 영역으로 저농도 N형 불순물층(14)과 고농도 N형 불순물층(12), 채널영역으로 P형 에피층(13)이 된다. PMOS 소자는 제2게이트 전극(19), 소오스/드레인(21)영역, 채널영역으로 저농도 N형 불순물층(16)이 된다.In this case, the NMOS device is the first gate electrode 20, the low concentration N-type impurity layer 14 in the source / drain region, the high concentration N-type impurity layer 12, and the P-type epitaxial layer 13 in the channel region. The PMOS device becomes the low concentration N-type impurity layer 16 as the second gate electrode 19, the source / drain 21 region, and the channel region.

상기 NMOS와 PMOS는 산화막(15)에 의해 격리된다.The NMOS and PMOS are isolated by the oxide film 15.

이와같은 본 발명을 제4도를 참조하여 보면, 게이트(19,20)가 두개 형성되어 평면형 및 수직형 트랜지스터의 게이트로 각각 쓰임을 알 수 있다.Referring to FIG. 4, the present invention can be seen that two gates 19 and 20 are formed to be used as gates of planar and vertical transistors, respectively.

이상에서 설명한 바와 같이 본 발명은 소자 하나의 영역에 수직형 트랜지스터 위에 평면형 트랜지스터를 형성하므로써, 소자의 면적축소를 실현할 수 있으며 특히, 엔모스와 피모스를 함께 사용하는 인버터(Inverter) 등의 회로 제작시 고집적화 할 수 있는 효과가 있다.As described above, the present invention can reduce the area of the device by forming a planar transistor on the vertical transistor in one region of the device, and in particular, manufacture a circuit such as an inverter using NMOS and PMOS together. There is an effect that can be highly integrated.

Claims (1)

반도체 기판 위에 고농도 N형 불순물층과 P형 에피층을 차례로 형성하는 공정과, 소자형성영역 이외의 고농도 N형 불순물층과 P형 에피층을 고농도 N형 불순물층의 소정 깊이까지 식각하는 공정과, 상기 P형 에피층 위에 저농도 N형 불순물층을 형성하는 공정과, 전면에 O2이온주입 및 열처리하여 상기 저농도 N형 불순물층(14) 중간과 상기 고농도 N형 불순물층의 양측 중간에 산화막(17)을 형성하는 공정과, 전면에 게이트 절연막을 형성하고 소자형성영역의 일측면에 제1게이트 전극, 소자형성영역 상측에 제2게이트 전극을 형성하는 공정과, 상기 제1, 제2게이트 전극을 마스크로 하여 상기 저농도 N형 불순물층 표면에 고농도 P형 이온을 주입하여 고농도 P형 불순물층을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 반도체 장치의 트랜지스터 제조방법.Forming a high-concentration N-type impurity layer and a P-type epi layer on a semiconductor substrate in sequence, etching a high-concentration N-type impurity layer and a P-type epi layer other than an element formation region to a predetermined depth of the high-concentration N-type impurity layer, the step of forming the low-concentration N-type impurity layer on the P-type epitaxial layer, and a front O 2 ion implantation and heat treatment by the low-concentration N-type impurity layer 14, the middle and the oxide film on each side node between the high-concentration N-type impurity layer (17 ), Forming a gate insulating film on the entire surface, forming a first gate electrode on one side of the device forming region, and forming a second gate electrode on the top of the device forming region, and forming the first and second gate electrodes. And forming a high concentration P-type impurity layer by implanting high concentration P-type ions into the surface of the low concentration N-type impurity layer as a mask. Way.
KR1019920013045A 1992-07-22 1992-07-22 Making method of transistor KR950006490B1 (en)

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KR950006490B1 true KR950006490B1 (en) 1995-06-15

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