KR100429857B1 - Method for fabricating transistor with punchthrough preventing region - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor with a punchthrough preventing region is provided to form a punchthrough preventing region self-aligned with a common gate electrode of NMOS and PMOS transistors under the common gate electrode by forming the first insulation layer for defining a gate electrode region and by performing a patterning process only once. CONSTITUTION: A P-well region(1) and an N-well region(10) are formed in the surface of a semiconductor substrate. An isolation layer(16) for defining an active region in the P-well and N-well regions is formed on a predetermined region of the resultant structure. The first insulation layer pattern(16) crosses the active regions defined in the P-well and N-well regions, having a groove with a predetermined width. The groove on the N-well region is covered with the second insulation layer pattern. The first punchthrough preventing region having a higher density than that of the P-well region is selectively formed under the surface of the active region exposed by the groove on the P-well region. The groove on the P-well region is filled with the first gate electrode(24). The second insulation layer pattern is removed to expose the groove on the N-well region. The second punchthrough preventing region(26) having a higher density than that of the N-well region is formed under the surface of the active region exposed by the groove on the N-well region. The groove on the N-well region is filled with the second gate electrode(30).

Description

Manufacturing method of transistor having punch-through blocking region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a transistor having a punchthrough blocking region.

In general, semiconductor devices, such as memory devices, are integrated into CMOS circuits composed of NMOS transistors and PMOS transistors to reduce power consumption. As a method of manufacturing a semiconductor device composed of such a CMOS integrated circuit, a method of forming a punch-through blocking region under a channel region has recently been widely used to suppress a short channel effect of a transistor. The punchthrough blocking region is formed to have the same conductivity type as that of the semiconductor substrate, that is, the well region, and has a concentration higher than that of the well region. Accordingly, when a constant voltage is applied between the source region and the drain region of the transistor, the width of the depletion layer formed in the well region can be reduced to suppress a phenomenon in which the punch-through phenomenon occurs.

On the other hand, there are various methods of manufacturing the transistor having the punch-through blocking region. To describe one of these various methods, first, an element isolation film defining an active region is formed on a surface of a predetermined region of a semiconductor substrate, and ion implantation is performed in the entire active region with impurities of the same conductivity type as that of the semiconductor substrate. By performing a deep ion implantation process, a punchthrough blocking region having a concentration higher than that of the semiconductor substrate is formed at a predetermined depth from the surface of the active region, and a gate insulating film and a gate electrode are formed on the active region of the resultant portion where the punchthrough blocking region is formed. And source / drain regions are formed on surfaces of the active regions on both sides of the gate electrode.

According to the conventional technique described above, since the source / drain regions are formed to overlap the punch-through stop region, the parasitic junction capacitance of the source / drain regions is increased to reduce the switching speed of the transistor.

In order to solve the above problem, a method of forming a punchthrough blocking region locally has recently been proposed. According to this method, a device isolation film defining an active region is formed, and then selective to the semiconductor substrate under the region where the gate electrode is to be formed using a mask having a chrome pattern and a reversed chrome pattern of the mask for forming the gate electrode. There is a method of minimizing the parasitic junction capacitance of the source / drain regions by performing a deep ion implantation process. However, according to the above-described transistor manufacturing method, in manufacturing a semiconductor device including a CMOS integrated circuit composed of an NMOS transistor and a PMOS transistor, punch-through blocking regions of different conductivity types are formed in the NMOS transistor and the PMOS transistor, respectively. To do this, two additional photographic processes are required.

Therefore, the technical problem to be achieved in the present invention is to manufacture a semiconductor device consisting of a CMOS circuit in which the NMOS transistor and the PMOS transistor has a common gate electrode, it is possible to simplify the process while minimizing the parasitic junction capacity of the source / drain region The present invention provides a method of manufacturing a transistor having a punch-through blocking region.

1 is a layout diagram of a general transistor used in the prior art and the present invention.

2A through 2E are cross-sectional views illustrating a method of manufacturing a transistor of the present invention along the cutting line 2-2 of FIG. 1.

In order to achieve the above technical problem, the method of manufacturing a transistor according to the present invention first forms an element isolation film defining an active region on a predetermined region of a semiconductor substrate. The device isolation layer may be formed by a trench isolation method or a local oxidation of silicon (hereinafter referred to as "LOCOS"). A first insulating film is formed on the entire surface of the substrate on which the device isolation film is formed, and then patterned to form a first insulating film pattern having an inverted pattern with a common gate electrode of the NMOS transistor and the PMOS transistor. Here, the first insulating layer pattern may be formed using a mask having a chrome pattern inverted from the chrome pattern of the mask for the common gate electrode, and using the same mask as the mask for the common gate electrode, but used to form the gate electrode. It may be formed by using a photoresist different from the resist. The kind of photoresist means a positive photoresist in which the exposed part is removed by the developer or a negative photoresist in which the unexposed part is removed by the developer. A second insulating film having an etch selectivity with respect to the first insulating film pattern is formed on the entire surface of the resultant product on which the first insulating film pattern is formed, and patterned by a photo process and an etching process to cover a portion where the gate electrode of the PMOS transistor is to be formed; 2 An insulating film pattern is formed. Ion implantation of a first conductivity type, i.e., P-type impurity, with a predetermined energy, using the first and second insulating film patterns and the device isolation layer as ion implantation masks to prevent the punchthrough of the first punchthrough region, i.e., the NMOS transistor Form an area. A conductive film is formed on the entire surface of the resultant product and then etched back to form a first gate electrode, that is, a gate electrode of an NMOS transistor. The second insulating layer pattern is removed. Punching the second gate electrode, i.e., the PMOS transistor, by ion implanting a second conductive type, i.e., N-type impurities, with a predetermined energy, using the first insulating layer pattern, the first gate electrode, and the device isolation layer as an ion implantation mask. Form a through blocking area. A conductive film is formed on the entire surface of the resultant material and etched back to form a second gate electrode, that is, a gate electrode of the PMOS transistor. The first gate electrode and the second gate electrode constitute a common gate electrode of the NMOS transistor and the PMOS transistor.

According to the present invention, after forming the inverted first insulating film pattern with the common gate electrode, the punch-through blocking region of the common gate electrode and the self-aligned NMOS and PMOS transistors can be formed using only one photo process. Thus, the parasitic junction capacity of the source / drain regions can be minimized while simplifying the process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout diagram illustrating an NMOS transistor and a PMOS transistor in a general CMOS circuit.

Referring to FIG. 1, reference numeral 1 denotes a P well region, and reference numeral 10 denotes an N well region. Further, reference numerals 3a and 3b denote active regions formed in the N well region 10 and the P well region 1, respectively. The N well region 10 and the P well region 1 may be formed by a self-aligning twin well forming process. Reference numeral 5 denotes a common gate electrode across the active regions 3a and 3b. The active region 3a is a region where a PMOS transistor is to be formed, and the active region 3b is a region where an NMOS transistor is to be formed. Here, the portion of the common gate electrode 5 overlapping the N well region 10 serves as the gate electrode of the PMOS transistor, and the portion of the common gate electrode 5 overlapping the P well region 1 serves as the gate electrode of the NMOS transistor. do.

2A through 2E are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention along the cutting line 2-2 of FIG. 1.

2A is a cross-sectional view for describing a step of forming the P well region 1 and the device isolation layer 12. First, the P well region 1 is formed in a predetermined region of the N-type semiconductor substrate 10. At this time, the semiconductor substrate 10 except for the P well region 1 serves as an N well region. Here, the P well region 1 and the N well region may be formed by a self-aligned twin well forming process even when the semiconductor substrate 10 is N type or P type. Subsequently, an isolation region 12 is formed in a predetermined region of the resultant in which the P well region 1 is formed, thereby defining an active region in the P well region 1 and the N well region 10. The device isolation film 12 may be formed of a thermal oxide film by a LOCOS method or a CVD oxide film by a trench device isolation method. At this time, a thin pad oxide film 14 remains on the surface of the active region.

2B is a cross-sectional view for describing a step of forming the first insulating film pattern 16 and the second insulating film pattern 18. In detail, a first insulating layer, for example, a silicon nitride layer having an etch selectivity with respect to the device isolation layer 12 is formed on the entire surface of the resultant device on which the device isolation layer 12 is formed. Next, the first insulating layer is patterned by using a chromium pattern of a mask for forming the common gate electrode 5 of FIG. 1 and a mask having an inverted chromium pattern, thereby forming an active region of the P well region 1 and A first insulating layer pattern 16 having a groove having a predetermined width is formed while crossing the active region of the N well region 10. When the mask for the common gate electrode 5 is used to form the first insulating layer pattern 16, the first insulating layer may be patterned by using a negative photoresist. The first insulating film is preferably formed to have the same thickness as the gate electrode formed in a subsequent step. Subsequently, a second insulating film, for example, a silicon oxide film having an etching selectivity with the first insulating film pattern 16 is formed on the entire surface of the resultant on which the first insulating film pattern 16 is formed, by a CVD method. Subsequently, the second insulating film is patterned to form a second insulating film pattern 18 covering the groove on the N well region 10. When the second insulating layer pattern 18 is formed in this manner, as shown in FIG. 2B, the groove on the P well region 1 is exposed.

2C is a cross-sectional view for describing a step of forming the first punch-through blocking region 20, the first gate insulating layer 22, and the first gate electrode 24. In more detail, P-type impurities such as boron fluoride (BF ₂ ) ions are formed by using the first insulating film pattern 16, the second insulating film pattern 18, and the device isolation film 12 as ion implantation masks. The first punch-through blocking region 20 at a predetermined depth from the exposed active region surface on the P well region 1 by implanting with energy of KeV to 100 KeV and a dose of 2.0 S10 ¹² to 3.0 S10 ¹² ion atoms / cm 2. To form. Next, the pad oxide film 14 remaining on the upper portion of the first punch-through blocking region 20 is removed to expose the P well region 1 below it. Subsequently, a first gate insulating layer 22, for example, a thermal oxide layer is formed on the exposed P well region 1, and then a conductive layer, eg, a polysilicon layer, is formed on the entire surface of the resultant P well region 1. Subsequently, the first gate electrode 24 filling the groove on the P well region 1 is etched back by etching back the conductive layer until the first insulating layer pattern 16 and the second insulating layer pattern 18 are exposed. Form. Here, the first gate electrode 24 serves as a gate electrode of the NMOS transistor. As such, when the first punch-through blocking region 20 and the first gate electrode 24 are formed, a first gate electrode 24 self-aligned with the first punch-through blocking region 20 can be formed. The area of the region where the source / drain region and the first punch-through blocking region 20 formed in the overlap region may be minimized.

FIG. 2D is a cross-sectional view for describing a step of forming the second punch-through blocking region 26 and the second gate insulating layer 28. In detail, the second insulating layer pattern 18 is removed with a specific chemical solution, for example, a phosphoric acid solution, to expose the pad oxide layer 14 on the N well region 10. Subsequently, the first insulating layer pattern 16, the first gate electrode 24, and the device isolation layer 12 are used as ion implantation masks to form N-type impurities such as phosphorus (P) ions with energy of 120 KeV to 180 KeV. And 1.5 S10 ¹² to 2.5 S10 ¹² ion atoms / cm 2 dose to form a second punch-through blocking region 26 at a predetermined depth from the exposed active region surface on the N well region 10. Next, the pad oxide film 14 remaining on the second punchthrough blocking region 26 is removed to expose the N well region 10 below. Subsequently, a second gate insulating layer 28, for example, a thermal oxide layer, is formed on the exposed N well region 10.

2E is a cross-sectional view for explaining a step of forming the common gate electrode 5. Specifically, a conductive film, such as a polysilicon film, is formed on the entire surface of the resultant product on which the second gate insulating film 28 is formed. Next, the groove is defined by the first insulating film pattern 16 on the N well region 10 by etching back the conductive film until the first insulating film pattern 16 and the first gate electrode 24 are exposed. The second gate electrode 30 filling the gap is formed. The first gate electrode 24 and the second gate electrode 28 formed as described above constitute the common gate electrode 5. As such, when the second gate electrode 30 is formed, the second gate electrode 30 self-aligned with the second punch-through blocking region 26 may be formed. Accordingly, it is possible to minimize the area of the region where the source / drain regions and the second punch-through blocking region 26 formed in a subsequent process overlap.

Subsequently, although not shown, the transistor according to the present invention is completed by removing the first insulating layer pattern 16 and forming source / drain regions in the active regions adjacent to the common gate electrode 5.

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art. For example, after forming the second punch through blocking region, the second gate insulating film, and the second gate electrode, the first punch through blocking region, the first gate insulating film, and the first gate electrode may be formed.

As described above, according to the present invention, in the manufacture of the NMOS transistor and the PMOS transistor constituting the CMOS integrated circuit, after forming the first insulating film pattern defining the gate electrode region, the NMOS transistor and A punchthrough blocking region self-aligned with the common gate electrode may be formed under the common gate electrode of the PMOS transistor. Accordingly, a transistor capable of minimizing the parasitic capacitance of the source / drain regions can be implemented in a simple process.

Claims (7)

Forming a P well region and an N well region on a surface of the semiconductor substrate; Forming an isolation layer defining an active region in the P well region and the N well region on a surface of a predetermined region of the resultant; Forming a first insulating layer pattern having a groove having a predetermined width while crossing an active region defined in the P well region and an active region defined in the N well region; Forming a second insulating film pattern covering a groove on the N well region; Selectively forming a first punchthrough blocking region below the surface of the active region exposed by the groove on the Pwell region, the first punchthrough blocking region having a concentration higher than that of the Pwell region; Forming a first gate electrode filling a groove on the P well region; Exposing a groove on the N well region by removing the second insulating layer pattern; Forming a second punchthrough blocking region below the surface of the active region exposed by the groove on the N well region, the second punchthrough blocking region having a concentration higher than that of the N well region; And Forming a second gate electrode filling the groove on the N well region. The method of claim 1, wherein the first insulating layer pattern is formed of a silicon nitride layer. The method of claim 1, wherein the second insulating layer pattern is formed of a silicon oxide layer. The method of claim 1, wherein the forming of the first gate electrode is performed. Forming a conductive film on an entire surface of the resultant product in which the first punch-through blocking region is formed; And Forming a first gate electrode filling a groove on the P well region by etching back the conductive layer until the first insulating layer pattern is exposed. The method of claim 4, wherein the conductive film is a polysilicon film. The method of claim 1, wherein the forming of the second gate electrode is performed. Forming a conductive film on an entire surface of the resultant product in which the second punch-through blocking region is formed; And And forming a second gate electrode filling the groove on the N well region by etching back the conductive layer until the first insulating layer pattern is exposed. The method of claim 6, wherein the conductive film is a polysilicon film.

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