KR100304501B1 - Method for forming transistor - Google Patents

Abstract

PURPOSE: A transistor formation method is provided to improve an integration degree by using a doped silicon germanium(SiGe) as a gate and to simplify manufacturing processes by controlling a composition rate of the SiGe. CONSTITUTION: After forming a well(32) of a second conductive type on a semiconductor substrate(31) of a first conductive type, a field oxide(33) is formed. Gate insulating layers(35) are formed on the semiconductor substrate(31) and the well(32), respectively. Then, silicon germanium layers(SixGey) are formed on the gate insulating layers(35) by CVD(Chemical Vapor Deposition). Heavily doped dopants of a p-type are implanted into the silicon germanium layers, thereby forming a first and a second gates(36,37).

Description

How to form a transistor

The present invention relates to a method for forming a transistor, and more particularly, to a method for forming a transistor suitable for miniaturization of a PMOS device and control of a threshold voltage.

In order to achieve high speed and high integration of semiconductor devices, device miniaturization is required. In particular, in recent years, scaling has rapidly progressed, but since the power supply voltage is constant, a strong electric field is formed inside the device, causing various problems.

In particular, as the channel becomes shorter, the influence of the depletion layer on the channel side in the source / drain region must be considered. That is, since the short channel transistor takes a portion of the depletion layer charge originally charged by the gate charge at the source / drain charge, the inversion layer is induced at a threshold voltage lower than that of the transistor having a long channel. If the threshold voltage of the device has a large dependence on the length of the channel, the threshold voltage fluctuates significantly even if the slight channel dimension is changed by the process fluctuations, resulting in a small operating margin of the circuit. The defective rate increases. Therefore, there is a need to select a stable device structure in which the threshold voltage does not drop to a very short channel length. Therefore, a method of reducing the influence of the depletion layer spreading from the source / drain region to the channel side in order to prevent the drop in the threshold voltage of the fine semiconductor device has been studied.

1A to 1G are process diagrams showing a method of forming a transistor according to the prior art.

In the related art, as shown in FIG. 1A, a mask (not shown) for exposing a predetermined portion of the semiconductor substrate 11 is formed on an n-type semiconductor substrate 11, and the semiconductor substrate 11 is formed on the semiconductor substrate 11. 11) and p-type impurities such as boron (B) having a different conductivity type, are doped at low concentration to form p well 12. In addition, the field oxide layer 13 is formed on the semiconductor substrate 11 by using a conventional device isolation method such as LOCOS (Local Oxidation of Silicon) to isolate the n-type semiconductor substrate 11 from the p well 12 and The active regions of the n-type semiconductor substrate 11 and p well 12 are defined.

Thereafter, as shown in FIG. 1B, the gate oxide film 14 is formed on the semiconductor substrate 11 whose active region is limited to the field oxide film 13 by thermal oxidation, and the conductive impurity is used to control the threshold voltage. Ion implantation. In general, when a gate is formed using polysilicon doped with n ⁺ type, nMOS is implanted with the same conductivity type as the substrate, and pMOS is implanted with a different conductivity type than the substrate to control the threshold voltage. That is, by implanting p-type impurities such as boron (B), the surface channel layer 15 is formed in the n-type semiconductor substrate 11, and the buried channel layer 15 is formed in the p well 12. do.

As shown in FIG. 1C, polysilicon is deposited on the gate oxide layer 14 by Chemical Vapor Deposition (CVD), and the like (As) or phosphorus (P). N-type impurities are doped to reduce the resistance. Thereafter, the polysilicon and gate oxide film 14 doped with n ⁺ type is patterned by photolithography (Photolithograpy) to form an active region of the n type semiconductor substrate 11 and p well 12. First and second gates 17 and 18 are formed.

Next, as shown in FIG. 1D, a first photoresist 19 is coated on the n-type semiconductor substrate 11 and the p well 12 to cover the first and second gates 17 and 18. Exposure and development are performed to form a first photoresist 19 pattern exposing the active region of the n-type semiconductor substrate 11. Boron (B) having a conductivity different from that of the n-type semiconductor substrate 11 to the n-type semiconductor substrate 11 using the first photoresist 19 pattern and the first gate 17 as a mask. P-type impurities such as p-type impurities are implanted at low concentration to form a low concentration first impurity region 20 to form a lightly doped drain (LDD) structure, and the first photoresist 19 pattern is removed.

As shown in FIG. 1E, the second photoresist 21 is coated on the n-type semiconductor substrate 11 and the p well 12 to cover the first and second gates 17 and 18. Exposure and development are performed to form a second photoresist 21 pattern exposing the active region of the p well 12. The second photoresist 21 pattern and the second gate 18 are used as masks to form acenic (As) having a conductivity different from that of the p well 12 in the p well 12 or phosphorus ( By implanting an n-type impurity such as P) at low concentration to form a low concentration second impurity region 22 forming an LDD structure, the second photoresist 21 pattern is removed.

Thereafter, as shown in FIG. 1F, an insulator layer is formed and etched back on the n-type semiconductor substrate 11 and the p well 12 to cover the first and second gates 17 and 18. Sidewalls 23 are formed on the sides of the first and second gates 17 and 18. A third photoresist 24 is coated on the n-type semiconductor substrate 11 and the p well 12 to cover the first and second gates and the sidewalls 17, 18, and 23. Exposure and development are performed to form a third photoresist 24 pattern exposing the n-type semiconductor substrate 11. Boron (B) having a conductivity different from that of the semiconductor substrate 11 in the n-type semiconductor substrate 11 by using the third photoresist 24 pattern, the first gate 17 and the sidewalls 23 as a mask. P-type impurities such as) are implanted at high concentration to form a high concentration of third impurity region 25 used as a source / drain region and to remove the third photoresist pattern 24.

Next, as shown in FIG. 1G, a fourth photo is formed to cover the first and second gates 17 and 18 and the sidewalls 23 on the n-type semiconductor substrate 11 and the p well 12. The resist 26 is applied, exposed and developed to form a fourth photoresist 26 pattern exposing the p well 12. Asnic (As) different in conductivity from the p well 12 to the p well 12 using the fourth photoresist 26 pattern, the second gate 18 and the sidewalls 23 as a mask, Alternatively, a high concentration of fourth impurity region 27 used as a source / drain region is formed by ion implantation of an n-type impurity such as phosphorus (P) at a high concentration. In the semiconductor substrate 11 and the lower portion of the first and second gates 17 and 18 of the p-well 12, that is, between the high concentration of the third and fourth impurity regions 25 and 27. The n-channel and p-channel regions are made and the devices thus made are nMOS and PMOS in CMOS.

As described above, conventionally, a well having a different conductivity type is formed on a semiconductor substrate, and p-type impurities are ion-implanted into the semiconductor substrate to control a threshold voltage on the semiconductor substrate. The buried channel layer was formed in the nMOS. Then, the first and second gates were formed using polycrystalline silicon doped with n ⁺ type to form nMOS and pMOS including impurity regions of the first and second gates and the conductive type.

However, when the gate is formed of polysilicon doped with n ⁺ type as the device is integrated to form a pMOS that becomes a buried channel type, a pn junction is formed and depleted in the channel region. Since the depletion layer is easy to spread to the channel region, there is a problem in that pMOS integration is limited.

Accordingly, an object of the present invention is to provide a method of forming a transistor capable of controlling the integration of the pMOS and the threshold voltage.

A method of forming a transistor according to the present invention for achieving the above object comprises the steps of forming a second conductivity type well in a first conductivity type semiconductor substrate and forming a field oxide film on a predetermined portion of the semiconductor substrate; And forming a gate oxide film in a predetermined portion on the conductive well and forming first and second gates made of silicon germanium, and forming the first and second conductivity types in the semiconductor substrate and the conductive well, respectively. 2 is a step of forming an impurity region.

1A to 1G are process drawings showing a method of forming a transistor according to the prior art.

2A to 2F are process diagrams illustrating a method of forming a transistor according to an embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

31: n-type semiconductor substrate 32: p well

36: first gate 37: second gate

45: p-type impurity region 47: n-type impurity region

Hereinafter, with reference to the accompanying drawings will be described the present invention.

2A through 2F are flowcharts illustrating a method of forming a transistor according to an embodiment of the present invention.

2A, a mask (not shown) for exposing a predetermined portion of the semiconductor substrate 31 is formed on the n-type semiconductor substrate 31 as shown in Fig. 2A. The p well 32 is formed in a predetermined portion of the n-type semiconductor substrate 31 by doping at a low concentration with other acenic As or n-type impurities such as phosphorus (P). The field oxide film 33 is formed on the semiconductor substrate 31 using a conventional device isolation method such as LOCOS to isolate the n-type semiconductor substrate 31 from the p-well 32 and the n-type semiconductor. The active regions of the semiconductor substrate 31 and the p well 32 are defined.

Next, as shown in FIG. 2B, a gate oxide film 35 is formed on the n-type semiconductor substrate 31 and the p well 32 in which the active region is limited to the field oxide film 33, and the gate oxide film is formed. Silicon germanium (Si _N Ge _M ) is deposited on (35) by a CVD method, and a dopant impurity such as boron (B) is doped to lower the resistance. Then, on the active region of the semiconductor substrate 31 and the p well 32 of the n-type by patterning of the silicon germanium and the gate oxide film 35 it is doped in the above p ⁺ -type by photolithography method of claim 1, and Second gates 36 and 37 are formed.

As shown in FIG. 2C, the first photoresist 38 is coated on the n-type semiconductor substrate 31 and the p well 32 to cover the first and second gates 36 and 37. The first photoresist 38 pattern is formed to expose the active region of the n-type semiconductor substrate 31 by exposure and development. Boron (B) having a conductivity different from that of the n-type semiconductor substrate 31 in the n-type semiconductor substrate 31 by using the first photoresist 38 pattern and the first gate 36 as a mask. P-type impurities such as p-type impurities are implanted at a low concentration to form a low concentration first impurity region 39 forming an LDD structure, and the first photoresist 38 pattern is removed.

Next, as shown in FIG. 2D, a second photoresist 40 is coated on the n-type semiconductor substrate 31 and the p well 32 so as to cover the first and second gates 36 and 37. Exposure and development are performed to form a second photoresist 40 pattern exposing the active region of the p well 32. The second photoresist 40 pattern and the second gate 37 are used as masks to form acenic (As) having a conductivity different from that of the p well 32 to the p well 32 or phosphorus ( By implanting an n-type impurity such as P) at low concentration to form a low concentration second impurity region 41 to form an LDD structure, the second photoresist 40 pattern is removed.

As shown in FIG. 2E, an insulator layer is formed and etched back on the n-type semiconductor substrate 31 and the p well 32 to cover the first and second gates 36 and 37. Sidewalls 43 are formed on side surfaces of the first and second gates 36 and 37. The third photoresist 44 is coated on the n-type semiconductor substrate 31 and the p well 32 to cover the first and second gates 36 and 37 and the sidewalls 43. The third photoresist 44 pattern is formed to expose the n-type semiconductor substrate 31 by exposure and development. The n-type semiconductor substrate 31 is then n-type on the n-type semiconductor substrate 31 using the third photoresist 44 pattern, the first gate 36 and the sidewalls 43 of the first gate 36 as a mask. Ion-doped p-type impurities such as boron (B) having a different conductivity type from the semiconductor substrate 31 of the semiconductor substrate 31 to form a high concentration third impurity region 45 to be used as a source / drain region. The resist 44 pattern is removed.

Thereafter, as shown in FIG. 2F, the fourth photoresist (ie, the first and second gates 36 and 37 and the sidewalls 43 are covered on the n-type semiconductor substrate 31 and the p well 32. 46 is applied, exposed and developed to form a fourth photoresist 46 pattern exposing the p well 32. The p well 32 and the conductive type are formed in the p well 32 using the fourth photoresist pattern 46, the second gate 37, and the sidewalls 43 of the second gate 37 as a mask. An n-type impurity such as phosphorous (P) or other acenic (As) or ion (P) is implanted at a high concentration to form a high concentration fourth impurity region 47 used as a source / drain region. In the semiconductor substrate 31 and the lower portion of the first and second gates 36 and 37 of the p-well 32, that is, between the high concentration of the third and fourth impurity regions 45 and 47. The n-channel and p-channel regions are made and the devices thus made are nMOS and PMOS in CMOS.

As described above, in the present invention, the first and second gates are formed by using silicon germanium doped with p ⁺ type without ion implantation to control the threshold voltage to the first conductive semiconductor substrate and the second conductive well. Formed. In addition, nMOS and pMOS transistors including the first and second gates are formed.

Accordingly, in the transistor according to the present invention, the gate is formed of p ⁺ type doped silicon germanium so that the threshold voltage can be controlled by adjusting the work function according to the component ratio of the silicon germanium. Since there is no need to perform ion implantation to control the voltage, pn junctions do not occur in the channel of the pMOS.

Claims (1)

Forming a well of the second conductivity type in the first conductivity type semiconductor substrate and forming a field oxide film in a predetermined portion of the semiconductor substrate; Forming a gate insulating film on a predetermined portion on the semiconductor substrate and the conductive well, forming a silicon germanium layer (Si _N Ge _M ) on the gate insulating film by chemical vapor deposition; Doping a high concentration of p-type impurities into the silicon germanium layer (Si _N Ge _M ), Pattern-etching the silicon germanium layer doped with the impurity to form first and second gates; And forming first and second impurity regions of a second and a first conductivity type in each of said semiconductor substrate and said well.