JPS5974674A - Insulation gate semiconductor device and manufacture thereof - Google Patents

Insulation gate semiconductor device and manufacture thereof

Info

Publication number
JPS5974674A
JPS5974674A JP18456882A JP18456882A JPS5974674A JP S5974674 A JPS5974674 A JP S5974674A JP 18456882 A JP18456882 A JP 18456882A JP 18456882 A JP18456882 A JP 18456882A JP S5974674 A JPS5974674 A JP S5974674A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
channel
type
part
region
decided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18456882A
Inventor
Hideshi Ito
Mitsuo Ito
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs

Abstract

PURPOSE:To contrive to reduce the output capacitance by a method wherein in a part of a p type region is decided as the first channel part, and the second channel part of a p type region of a low concentration is formed outside it, in an n- channel MOSFET. CONSTITUTION:With and n type Si substrate 1 having an n<+> Si layer 2 on the back surface as a drain, p type regions 3 wherein in a part serves as the channel are formed on the surface of this substrate 1, and an n<+> type regions 5 are formed on the surfaces of the regions, thus being decided as the source. A gate (electrode) 7 is provided, on the surface of the p type region wherein the region 5 is not formed, via an insulation film 6. In the n-channel MOSFET of such a structure, a part of the region 3 is decided as the first channel part, and the p<-> type region 8 is formed outside it, thus being decided as the second channel part. By forming in such a structure, the first channel part operates as an enhancement type, and the second channel part as a depletion type. Thereby , the stretch of a depletion layer between the region 8 and the substrate 1 expands also to the second channel size, and therefore the output capacitance is reduced. Accordingly, the output capacity is reduced.
JP18456882A 1982-10-22 1982-10-22 Insulation gate semiconductor device and manufacture thereof Pending JPS5974674A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18456882A JPS5974674A (en) 1982-10-22 1982-10-22 Insulation gate semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18456882A JPS5974674A (en) 1982-10-22 1982-10-22 Insulation gate semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5974674A true true JPS5974674A (en) 1984-04-27

Family

ID=16155480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18456882A Pending JPS5974674A (en) 1982-10-22 1982-10-22 Insulation gate semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5974674A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4898835A (en) * 1988-10-12 1990-02-06 Sgs-Thomson Microelectronics, Inc. Single mask totally self-aligned power MOSFET cell fabrication process
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor
US5202276A (en) * 1990-08-20 1993-04-13 Texas Instruments Incorporated Method of forming a low on-resistance DMOS vertical transistor structure
US5272098A (en) * 1990-11-21 1993-12-21 Texas Instruments Incorporated Vertical and lateral insulated-gate, field-effect transistors, systems and methods
EP0656661A1 (en) * 1993-11-12 1995-06-07 Nippondenso Co., Ltd. DMOSFET with a resistance for improving the reverse bias conduction
JPH07506941A (en) * 1993-03-31 1995-07-27
US5741736A (en) * 1995-05-04 1998-04-21 Motorola Inc. Process for forming a transistor with a nonuniformly doped channel
US6472678B1 (en) 2000-06-16 2002-10-29 General Semiconductor, Inc. Trench MOSFET with double-diffused body profile
JP2012059744A (en) * 2010-09-06 2012-03-22 Toshiba Corp Semiconductor device
WO2012060248A1 (en) * 2010-11-01 2012-05-10 住友電気工業株式会社 Semiconductor device and manufacturing method therefor
JP5015361B2 (en) * 2010-10-29 2012-08-29 パナソニック株式会社 Semiconductor device and a semiconductor device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4898835A (en) * 1988-10-12 1990-02-06 Sgs-Thomson Microelectronics, Inc. Single mask totally self-aligned power MOSFET cell fabrication process
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor
US5202276A (en) * 1990-08-20 1993-04-13 Texas Instruments Incorporated Method of forming a low on-resistance DMOS vertical transistor structure
US5272098A (en) * 1990-11-21 1993-12-21 Texas Instruments Incorporated Vertical and lateral insulated-gate, field-effect transistors, systems and methods
JPH07506941A (en) * 1993-03-31 1995-07-27
EP0656661A1 (en) * 1993-11-12 1995-06-07 Nippondenso Co., Ltd. DMOSFET with a resistance for improving the reverse bias conduction
US5696396A (en) * 1993-11-12 1997-12-09 Nippondenso Co., Ltd. Semiconductor device including vertical MOSFET structure with suppressed parasitic diode operation
US5741736A (en) * 1995-05-04 1998-04-21 Motorola Inc. Process for forming a transistor with a nonuniformly doped channel
US6472678B1 (en) 2000-06-16 2002-10-29 General Semiconductor, Inc. Trench MOSFET with double-diffused body profile
JP2012059744A (en) * 2010-09-06 2012-03-22 Toshiba Corp Semiconductor device
US9029869B2 (en) 2010-09-06 2015-05-12 Kabushiki Kaisha Toshiba Semiconductor device
JP5015361B2 (en) * 2010-10-29 2012-08-29 パナソニック株式会社 Semiconductor device and a semiconductor device
WO2012060248A1 (en) * 2010-11-01 2012-05-10 住友電気工業株式会社 Semiconductor device and manufacturing method therefor
JP2012099601A (en) * 2010-11-01 2012-05-24 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same
US9006745B2 (en) 2010-11-01 2015-04-14 Sumitomo Electric Industries, Ltd. Semiconductor device and fabrication method thereof
US9443960B2 (en) 2010-11-01 2016-09-13 Sumitomo Electric Industries, Ltd. Semiconductor device and fabrication method thereof

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