JPS6185863A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6185863A JPS6185863A JP59207458A JP20745884A JPS6185863A JP S6185863 A JPS6185863 A JP S6185863A JP 59207458 A JP59207458 A JP 59207458A JP 20745884 A JP20745884 A JP 20745884A JP S6185863 A JPS6185863 A JP S6185863A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- type
- conductivity type
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 230000008961 swelling Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 101100133721 Caenorhabditis elegans npr-1 gene Proteins 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特にＮＰＮ）ランジス
タと同等の特性を有するＰＮＰ ）ランジスタの構造に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to the structure of a PNP transistor having characteristics similar to those of an NPN transistor.
従来ＮＰＮトランジスタと同一基板上に形成されたＰＮ
Ｐ ）ランジスタは、エピタキシャル領域をベース領域
として用いる方法であり、その構造上ラテラルＰＮＰ
トランジスタとバーチカルＰＮＰトランジスタがある。PN formed on the same substrate as conventional NPN transistor
P) Transistor is a method that uses an epitaxial region as a base region, and due to its structure, lateral PNP
There are transistors and vertical PNP transistors.
従来のＮＰＮ トランジスタとＰＮＰ）ランジスタ（ラ
テラルＰＮＰ）の構造を薦１図に示すＰ形Ｓｉ基板ｌに
ｌＸｌ０”ｃｍ−３程度のＮ＋形埋込層２ａ、２ｂｔ−
形成し、その上にｌＸｌ０” 〜ｌＸｌ０”ｃｍ
程度のＮ形エピタキシャル層３ａ、３ｂ全形成する。そ
の後絶縁領域４ａ、４ｂ、４ｃ全形成する、絶縁領域は
Ｐ形の拡散の場合と誘電体を用いる場合等がある。The structure of a conventional NPN transistor and a PNP transistor (lateral PNP) is recommended by adding N+ type buried layers 2a, 2bt- to a P-type Si substrate l shown in Fig.
1Xl0" to 1Xl0"cm
The N-type epitaxial layers 3a and 3b are completely formed. Thereafter, the insulating regions 4a, 4b, and 4c are all formed.The insulating regions may be made of P-type diffusion or may be made of dielectric material.
次に、ＮＰＮ）ランジスタのベース５ａ、ＰＮＰトラン
ジスタのコレクタ５ｂ、エミ、り５ｃｔ−形成、ＮＰｒ
１ランジスタのエミッタ５ａ、 コレクタコンタクト領
域５ｂ、ＰＮＰ）ランジスタのベースコンタクト領域６
Ｃ′ｔ−形成し、電極７形成全行なうことによりトラン
ジスタを構［−ｊる。Next, the base 5a of the NPN transistor, the collector 5b of the PNP transistor, the emitter 5ct- are formed, and the NPr
1 transistor emitter 5a, collector contact region 5b, PNP) transistor base contact region 6
A transistor is constructed by forming C't- and completing all the electrode 7 formations.
また、バーチカルＰＮＰ）ランジスタは ｐ＋形埋込領
域をコレクタとして用い、エミ、り［ＮＰＮトランジス
タとは別工程で形成し、電流増幅率ｔＮＰＮ ）ランジ
スタと同等にしｔものである。Further, a vertical PNP transistor uses a p+ type buried region as a collector, is formed in a separate process from an NPN transistor, and has a current amplification rate tNPN equivalent to that of an emitter transistor.
上述した従来のラテラルＰＮＰトランジスタはエミ、り
・コレクタ１ＮＰＮ）ランジスタのベース形成と同時に
形成されるため、プロセスが非常に簡便であるという長
所を有するが、上記した工うに、ｌＸｌ０”〜１刈ｏ
１６ ｃｒｎ−３程度のＮ形エピタキシャル層をベース
として用いており、耐圧、パターニングの精度の問題か
らベース幅が広くなυ、さらＩｃはエミッタから注入さ
れたキャリアが無効電流になる割合も高く、結局電流増
幅率が小さく、シゃ新局波数もＮＰＮ）ランジスタの１
７１００程度という低いものとなってしまう。The above-mentioned conventional lateral PNP transistor has the advantage that the process is very simple because the emitter, collector, and collector are formed simultaneously with the base formation of the transistor.
An N-type epitaxial layer of about 16 crn-3 is used as the base, and the base width is wide due to problems with breakdown voltage and patterning accuracy.Furthermore, Ic has a high proportion of carriers injected from the emitter becoming a reactive current. After all, the current amplification factor is small, and the new station wave number is also NPN).
It ends up being as low as around 7100.
一方、バーチカルＰＮＰ）ランジスタｈ、ｔａ増幅率は
上昇したものの、し中断周波数はＮＰＮトランジスタの
ｌＸｌ０程度しか得られず、集積回路の高速化を非常に
困難なものとしていた。On the other hand, although the amplification factors of vertical PNP transistors (h, ta) have increased, the interruption frequency can only be obtained on the order of lXl0 of an NPN transistor, making it extremely difficult to increase the speed of integrated circuits.
この発明は以上のような問題点に対処してなされたもの
で、電流増幅率の特性、耐圧、し中断周波数等において
、ＮＰＮ）ランジスタとＰＮＰトランジスタが同等の特
性が発揮できる構造のＰＮＰトランジスタを有する半導
体集積回路装置を提供することを目的とする。This invention was made in response to the above-mentioned problems, and it is a PNP transistor with a structure that allows NPN transistors and PNP transistors to exhibit equivalent characteristics in terms of current amplification characteristics, breakdown voltage, interruption frequency, etc. An object of the present invention is to provide a semiconductor integrated circuit device having the following features.
本発明の半導体集積回路装置は、−４１Ｘ形半導体基板
上に形成された少なくともひとつの一４電形の高ｒａ度
領域と、該一導電形高一度領域と＋２離間して形成され
た少なくともひとつの反対導電形の高ａ度領域とを有し
、前記−４１形高濃度領域上には、均一で低濃度の一導
電形半導体層を有し、前記反対４ｉ形高ａ肛領域上ｉｃ
は均一で低濃度の反対導電形の半導体層を有し、前記−
導１形の半導体層と前記反対導電形の半導体層は誘電体
で分離され、前記低ａ度の一導電形半導体層お工び前記
低ｄ度の反対４電形半導体Ｉａに各々バイポーラトラン
ジスタを形成することにより構成される。The semiconductor integrated circuit device of the present invention includes at least one 14 conductivity type high degree region formed on a -41X type semiconductor substrate, and at least one conductivity type high degree region formed at a distance of +2 from the one conductivity type high degree region. on the -41 type high concentration region, a uniform low concentration semiconductor layer of one conductivity type on the opposite 41 type high concentration region;
has a uniform, low concentration semiconductor layer of opposite conductivity type, and the -
The conductivity type 1 semiconductor layer and the opposite conductivity type semiconductor layer are separated by a dielectric, and a bipolar transistor is formed in the low-a degree one-conductivity type semiconductor layer and the low-d degree opposite 4-conductivity type semiconductor layer Ia, respectively. Constructed by forming.
次に、本発明について、図ｒｊｒＪを参照して説明する
。Next, the present invention will be explained with reference to Figure rjrJ.
Ｊ１図は本発明の一実施例の断面図である。第１図にお
いて、Ｐ形８ｉ基板８に１ｘ１０ ｃｍ程度のＮ 形
埋込層９ａ、９ｂを形成する。その後）’ＮＰ）ランジ
スタのコレクタとなる領域ＶｃＩＸＩ０１９ｃｍ−３程
度のＰ＋形埋込層１０を形成し、ｌＸ１０１５〜ｌＸｌ
０”ｃｍ−３程度のＮ形エピタギシャルＲ１１を２〜３
μｍ程度形成する。次にＰＮＰトランジスタ金形酸形成
領域のエピタキシャル層＝ｉＰ＋形埋込層１０に達する
まで、リアクティブ・イオン・工、チング法等金用いて
工、チングを行ない、Ｎ形エピタキシャル層の側面に絶
縁物１３鳥１３ｂ、１３ｃを形成し、ＰＮＰ）ランジス
タを形成する領域にのみ、ｌＸ１０１５〜ｌＸｌ０
ｃｍ程度のＰ形エピタキシャル層１２を形成する。Figure J1 is a sectional view of one embodiment of the present invention. In FIG. 1, N type buried layers 9a and 9b of about 1x10 cm are formed on a P type 8i substrate 8. After that, a P+ type buried layer 10 of about VcIXI019cm-3 is formed, which will become the collector of the transistor.
2 to 3 N-type epitaxial R11 of about 0"cm-3
It forms about μm. Next, until reaching the epitaxial layer of the PNP transistor die formation region = iP+ type buried layer 10, etching and etching are performed using metal such as reactive ion etching and ching method, and insulation is formed on the sides of the N type epitaxial layer. Only in the region forming object 13 birds 13b and 13c and forming a PNP) transistor, lX1015 to lXl0
A P-type epitaxial layer 12 having a thickness of about 1.0 cm is formed.
以上の工程に工り、絶縁物で分離されたＮ形エビタチシ
ャルの島領域とＰ形エピタキシャルの島領域が形成さＩ
Ｌる。Through the above process, an N-type epitaxial island region and a P-type epitaxial island region separated by an insulator are formed.
L.
その後は通常の拡散、イオン注入等の方法を用いること
にょ力、ＮＰＮ）ランジスタのベース１５゜エミッタ１
７ａ、コレクタ１７ｂお工びＰＮＰ ）ランジスタのベ
ース１４．エミ、り１６ａ、コレクタ１６ｂ’ｉ形成す
る。この時イオン注入条件。After that, the base 15° emitter 1 of the NPN transistor is
7a, Collector 17b PNP) Base of transistor 14. An emitter, a collector 16a, and a collector 16b'i are formed. At this time, the ion implantation conditions.
熱処理条件等を考慮し、ＮＰＮ）ランジスタとＰＮＰト
ランジスタが反対導電形の不純物にエフ構成されている
ことを除いては、エミ、り・ベース・コレクタの不純物
濃度プロファイル全同一になるようにする。Considering the heat treatment conditions, etc., the impurity concentration profiles of the emitter, base, and collector are all made to be the same, except that the NPN transistor and the PNP transistor are configured with impurities of opposite conductivity types.
以上の結果、第１図に示す様にＮＰＮトランジスタとＰ
ＮＰ ）ランジスタを同じ構造にすることができ、電流
増幅率、しゃ新局波数共にＮＰＮ）ランジスタとＰＮＰ
）ランジスタとが同一特性を得ることができる。As a result of the above, as shown in Figure 1, the NPN transistor and P
NP ) transistors can have the same structure, and both the current amplification factor and the new station wave number are NPN) transistors and PNP
) can obtain the same characteristics as a transistor.
また、以上の構造において、Ｎ形とＰ形を変えて構成し
てもさしつかえないことはいうまでもない。Furthermore, in the above structure, it goes without saying that the N-type and P-type may be configured differently.
ま九本実施例ではＮ＋形埋込層９ａは使用目的にエフ省
略し、直接Ｐ＋形埋込層を形成することも出来る。In this embodiment, the N+ type buried layer 9a may be omitted depending on the purpose of use, and a P+ type buried layer may be directly formed.
以上説明したとおり、本発明に工れば、゛ｔｆｔ増幅率
、し中断周波数共にＮＰＮ）ランジスタト同等の値を有
する高性能なＰＮＰ ）ランジスタが得られ、半導体集
積回路の高速化高性能化金遣することができる。As explained above, if the present invention is applied, a high-performance PNP transistor whose TFT amplification factor and interruption frequency are equivalent to that of an NPN transistor can be obtained, and it is possible to improve the speed and performance of semiconductor integrated circuits. can do.
第１図は本発明の一実施例のバイポーラトランジスタの
構造を示す断面図、巣２図は従来のバイポーラトランジ
スタの構造を示す断面図である。
１．８・＝・Ｐ形３ｉ基板、２ａ、２ｂ、９ａ。
９ｂ・・・・・・Ｎ 形埋込層、３ａ、３ｂ、１１・・
・・・Ｎ形エピタキシャル層、４ａ、４ｂ、４ｃ・・・
・・・Ｐ形もシくハ酸化物分離領域、５ａ、５ｂ、５Ｃ
，１５、、−、、、Ｐ膨拡散層、６ａ、６ｂ、６ｃ、１
７ａ、１７ｂ・・・・・・Ｎ＋形形成散層７．１８・・
・・・・金属電極、１゜・・・・・・Ｐ＋形埋込層、１
２・・・・・・Ｐ形エピタキシャル層、１３ａ、１３ｂ
、１３ｃ・・・・・・酸化物もしくは窒化物による絶縁
分離領域、１４・・・・・・Ｎ膨拡散層、１６ａ、１６
ｂ・・・・・・Ｐ 膨拡散層。FIG. 1 is a sectional view showing the structure of a bipolar transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a conventional bipolar transistor. 1.8 = P-type 3i substrate, 2a, 2b, 9a. 9b...N type buried layer, 3a, 3b, 11...
...N type epitaxial layer, 4a, 4b, 4c...
... P-type halide isolation region, 5a, 5b, 5C
,15,,-,,,P swelling diffusion layer,6a,6b,6c,1
7a, 17b...N+ shape forming scattering layer 7.18...
...Metal electrode, 1゜...P+ type buried layer, 1
2...P type epitaxial layer, 13a, 13b
, 13c...Insulating isolation region made of oxide or nitride, 14...N swelling diffusion layer, 16a, 16
b...P Swelling diffusion layer.
Claims (2)
とつの一導電形の高濃度領域と、該一導電形高濃度領域
とは離間して形成された少なくともひとつの反対導電形
の高濃度領域とを有し、前記一導電形高濃度領域上には
、均一で低濃度の一導電形半導体層を有し、前記反対導
電形高濃度領域上には均一で低濃度の反対導電形の半導
体層を有し、前記一導電形の半導体層と前記反対導電形
の半導体層は誘電体で分離され、前記低濃度の一導電形
半導体層および前記低濃度の反対導電形半導体層に各々
バイポーラトランジスタを構成してなることを特徴とす
る半導体集積回路装置。(1) At least one high concentration region of one conductivity type formed on a semiconductor substrate of one conductivity type, and at least one high concentration region of the opposite conductivity type formed apart from the high concentration region of one conductivity type. a uniform, low concentration semiconductor layer of one conductivity type on the high concentration region of one conductivity type, and a uniform, low concentration semiconductor layer of the opposite conductivity type on the high concentration region of the opposite conductivity type. the one conductivity type semiconductor layer and the opposite conductivity type semiconductor layer are separated by a dielectric, and a bipolar transistor is provided in the low concentration one conductivity type semiconductor layer and the low concentration opposite conductivity type semiconductor layer, respectively. A semiconductor integrated circuit device comprising:
間に反対導電形領域を有し、たがいに分離されている特
許請求の範囲第（１）項記載の半導体集積回路装置。(2) The semiconductor integrated circuit device according to claim (1), wherein the semiconductor substrate of one conductivity type and the high concentration region of one conductivity type have an opposite conductivity type region and are separated from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207458A JPS6185863A (en) | 1984-10-03 | 1984-10-03 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207458A JPS6185863A (en) | 1984-10-03 | 1984-10-03 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6185863A true JPS6185863A (en) | 1986-05-01 |
Family
ID=16540100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207458A Pending JPS6185863A (en) | 1984-10-03 | 1984-10-03 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185863A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01164067A (en) * | 1987-07-29 | 1989-06-28 | Fairchild Semiconductor Corp | Manufacture of complementary contactless vertical bipolar transistor |
| US6768183B2 (en) * | 2001-04-20 | 2004-07-27 | Denso Corporation | Semiconductor device having bipolar transistors |
-
1984
- 1984-10-03 JP JP59207458A patent/JPS6185863A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01164067A (en) * | 1987-07-29 | 1989-06-28 | Fairchild Semiconductor Corp | Manufacture of complementary contactless vertical bipolar transistor |
| US6768183B2 (en) * | 2001-04-20 | 2004-07-27 | Denso Corporation | Semiconductor device having bipolar transistors |
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