JPH01251749A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance a device characteristic and to enhance the integration density by a method wherein a MOS transistor and a bipolar transistor are laminated on an identical substrate and these are connected in a direct contact manner. CONSTITUTION:A single-crystal silicon layer 24 is formed on an Si substrate 21 by a selective epitaxial growth method; then, an NPN bipolar transistor composed of a collector 22, a base 25 and an emitter 26 is formed in this region. After that, a prescribed patterning operation is executed in order to form a MOS transistor; a polycrystalline silicon layer 30 is formed; a p-region which is used for a source 31a and a drain 31b of the MOS transistor is formed by implanting ions of arsenic. When the MOS transistor and the bipolar transistor are formed on an identical substrate in such a way that they are overlapped partially, it is possible to reduce an occupied area by about 55%; accordingly, the integration can be achieved extremely effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to an improvement in a semiconductor device having a MOS transistor and a bipolar transistor on the same substrate, and a method for manufacturing the same.

(Prior Art) In recent years, when manufacturing a circuit that accurately controls a relatively large current, a method has been adopted in which a MOS transistor and a bipolar transistor are used and an output signal of the MOS transistor is applied to the base of the bipolar transistor.

The basic concept of this method is to use a low-power MO as a control signal source.
The purpose is to use an S transistor and a bipolar transistor as an element through which a relatively large current to be controlled flows.

By the way, when manufacturing this type of B i /MOS structure element, there are the following drawbacks.

(2) Since MOS transistors and bipolar transistors are fabricated in parallel on the same substrate, a large area is required, making it impossible to achieve high integration.

(2) The process becomes more complicated, and in particular the thermal history becomes longer, so the redistribution of impurities in the portion created at the beginning of the process spreads over a wide range, leading to deterioration of device characteristics.

FIG. 7 is a cross-sectional view showing the manufacturing process of a conventional Bi/MO8 structure element. First, as shown in FIG. 7(a), an n+ type buried layer 2 and a p-type epitaxial layer 3 are formed on a p-type silicon substrate 1, and then an n-well 4.0 is formed as shown in FIG. 7(b). A field oxide film 5 and a gate oxide film 6 are formed. Next, as shown in FIG. 7(C), a gate electrode 7 of a MOS transistor is formed, and a base 8 of a bipolar transistor is further formed by ion implantation. Then the seventh
As shown in figure (d), the source
A drain is formed, an emitter is formed by n+ ion implantation, etc., and a MOS transistor is formed on the left side of the figure, and a bipolar transistor is formed on the right side of the figure. In the figure, 9a and 9b are source/drain regions, 10 is an emitter, 11 is an insulating film, and 12 is an AI wiring layer.
Processes that require high temperatures and long periods of time, such as the epitaxial growth process and element isolation process shown in
During the formation of the type epitaxial layer 3, unnecessary impurities are incorporated into not only the bipolar region but also the MOS element region from the n+ type buried layer 2 due to autodoping, out-diffusion, etc., resulting in deterioration of characteristics. Furthermore, re-diffusion of impurities occurs even in the element isolation process.

Furthermore, a structure in which a MOS transistor and a bipolar transistor are stacked has been devised as a B i /MOS structure element. This involves forming a polycrystalline silicon film over a MOS transistor via an insulating film, recrystallizing this silicon film using techniques such as beam annealing, and forming a bipolar transistor on the recrystallized silicon film. .

However, with this structure, it is not possible to obtain a sufficiently homogeneous recrystallized layer by beam annealing, which causes deterioration of device characteristics.

(Problem to be Solved by the Invention) As described above, conventionally, in a semiconductor device in which an N1oS transistor and a bipolar transistor are formed on the same substrate,
There is a problem that the device occupation area increases and the degree of integration decreases.
Furthermore, there was a problem that device characteristics deteriorated due to the manufacturing process.

The present invention has been made in consideration of the above circumstances, and its purpose is to realize a tM structure in which a MOS transistor and a bipolar transistor are stacked on the same substrate, and to improve device characteristics and increase integration. An object of the present invention is to provide a semiconductor device with a new structure that can improve performance.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that easily realizes the above semiconductor device.

[Structure of the Invention (Means for Solving the Problem) The gist of the present invention is to stack a MOS transistor and a bipolar transistor, and connect the source or drain of the MOS transistor and the base of the bipolar transistor by direct contact. There is a particular thing. Furthermore, for direct contact, a selective epitaxial growth method that allows single crystal growth at low temperatures is used instead of a process that requires high temperatures such as beam annealing.

That is, the present invention provides a semiconductor device in which a MOS transistor and a bipolar transistor are stacked on a semiconductor substrate, in which the source or drain of the MOS transistor and the base of the bipolar transistor are of the same conductivity type, and are connected by direct contact. It is something.

The present invention also provides the method for manufacturing a semiconductor device, in which an insulating film is formed on a semiconductor substrate, a hole is opened in a part of the insulating film reaching the substrate, and then a first layer is formed in the hole by selective epitaxial growth or the like. A bipolar transistor is formed on the first semiconductor thin film and the substrate, a second single crystal semiconductor thin film is formed on the insulating film and the first semiconductor thin film, and then a second single crystal semiconductor thin film is formed on the insulating film and the first semiconductor thin film.
In this method, a MOS transistor is formed in a semiconductor thin film in which the source or drain is in direct contact with the base of a bipolar transistor.

Furthermore, the present invention provides the method for manufacturing the semiconductor device, comprising:
After forming a MOS transistor on a semiconductor substrate, a single crystal semiconductor thin film is formed on the substrate and the MOS transistor via an insulating film, and a part of the single crystal semiconductor thin film is brought into direct contact with the source or drain of the MOS transistor (at least In this method, a bipolar transistor is formed in which the base is in direct contact with the source or drain of the MOS transistor in the semiconductor thin film.

The present invention also provides a complementary MOS transistor provided on a semiconductor, a single crystal semiconductor thin film formed on the transistor and the substrate via an insulating film, and two bipolar transistors formed in this semiconductor thin film. Equipped with
By connecting the two MOS transistors and the two bipolar transistors, B i / CM OS
The inverter is configured to form 1 IS.

(Function) According to the present invention, since the MOS transistor and the bipolar transistor are stacked, the area occupied by the element is reduced compared to a structure in which these transistors are provided in a planar manner, and the degree of integration is improved. is possible. Also, since the source or drain of the MOS transistor is in direct contact with the base of the bipolar transistor,
The number of connections between the MOS transistor and the bipolar transistor can be reduced, contributing to simplification of the manufacturing process and higher integration. Furthermore, the above-mentioned direct contact is effective in increasing the speed of the device. Furthermore, since the direct contact portion is formed by selective epitaxial growth, there is no thermal damage to the underlying element, and deterioration of the characteristics of the underlying element can be suppressed. Furthermore, since the selective epitaxial growth method is used, the semiconductor thin film formed on the insulating film can be made into a high-quality single crystal, which improves the device characteristics of the MOS transistor or bipolar transistor formed on this semiconductor thin film. Is possible.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG. 1(a), arsenic is ion-implanted into an element formation region on a single-crystal Si substrate 21 by an ion implantation method to form an n++ diffusion region 22. The ion implantation conditions at this time are a dose of 4
X 10"cll-2, accelerating voltage 40kV. Here, the Si substrate 21 contains 1.5x arsenic as an impurity.
A pJ421& board containing 10'' cIIl-2 was used. Also, the n+ type region 22 is a portion that will form the collector of an NPN type bipolar transistor in a process described later.

Next, as shown in FIG. 1(b), 6,000 SiO□ films 23 are deposited on the Si substrate 21 using atmospheric pressure chemical vapor deposition (CVD). Further, as shown in FIG. 1C, after a hole is made in the SiO□ film 23 by dry etching, a single crystal silicon layer 24 is first formed in this region by selective epitaxial growth. Next, in order to form a bipolar transistor in this region, arsenic was applied at an accelerating voltage of 60 kV and a dose m I
m-2 ions are implanted to form a p-type head region 25, and arsenic is implanted at a dose of Q30x1016 cm-2 into a part of the region to form a Cn + type region 26. As a result, the collector 22, base 25 and An NPN bipolar transistor consisting of an emitter 26 is obtained.

Next, as shown in FIG. 1(d), an fHC-based SiO2 film 27 is deposited on the entire surface by atmospheric pressure CVD, and then a part of it is peeled off as shown. After that, Figure 1 (
As shown in Q), a polycrystalline silicon film 28 is formed on the peeled part.
After depositing a, the deposited layer 28a is recrystallized to become a single crystal. At this time, as the recrystallization method, a method was used in which silicon ion implantation was performed and then single crystallization was performed by low temperature heat treatment. That is, polycrystalline silicon is made amorphous by silicon ion implantation, and then a single crystal silicon thin film 2 is formed over a part of the Sio2 film 23 and the p-type head region 25 by solid phase growth using low temperature annealing.
8b was formed. The silicon ion implantation conditions are: acceleration voltage 50kV, dose amount 2.52X 10'well-
2, and accelerated ftzokV, dose Q 5.4
XlO''ell-2.The low-temperature annealing conditions were 620°C for 24 hours.

When annealing is performed under such conditions, it can be seen that the amorphous polycrystalline silicon film 28a is recrystallized using the buried single crystal silicon layer 24 as a seed. In this example, it was found that silicon ion implantation was performed under the above conditions, and that below these conditions the recrystallization rate slowed down.

Further, under the above conditions, the polycrystalline silicon film 28a was sufficiently recrystallized, and Kikuchi lines were clearly seen when observed by electron beam diffraction test. In addition, when cross-sectionally observed with a transmitted electron beam, only a few twin crystals were observed. That is, it was found that the polycrystalline silicon film 28a was almost completely recrystallized to a single crystal.

Thereafter, in order to form a p-channel MO3 transistor in the monocrystalline silicon film 28b on the 5in2 film 23 thus formed, it was first placed in a dry atmosphere at 900°C, as shown in FIG. 1(f). , by thermal oxidation method 400
A gate oxide film 29 is formed. Next, Figure 1 (g
), a 4,000-layer polycrystalline silicon layer that will become the gate electrode of a MOS transistor is formed by low pressure CVD, and then predetermined patterning is performed to form a polycrystalline silicon layer 30.

Thereafter, as shown in FIG. 1(h), p regions that will become the source 31a and drain 31b of the MOS transistor are formed by ion-implanting arsenic. The ion implantation conditions at this time are a dose of 4 x 10" cm-2 and an acceleration voltage of 40 kV. As a result, a MOS transistor is created in a part of the region 25 above the SiO2 film 23, and this MOS transistor The drain 31b of the bipolar transistor is in direct contact with the base 25 of the bipolar transistor.In the above ion implantation process, arsenic is also implanted into the polycrystalline silicon layer 30.

Next, as shown in Figure 1N), 5 inches of plasma was applied to the entire surface.
A source contact hole 33a is formed in this 5in2 film 32 by depositing 600 layers of the 5in2 film 32.

Gate contact hole 33b1 emitter contact hole 33c1 collector contact hole 33d are opened. From now on, by forming an Afi wiring layer (not shown), a B i/MOS tj4 formed by stacking MOS transistors and bipolar transistors will be formed.
The first semiconductor device is completed.

The circuitry of the semiconductor device thus manufactured is as shown in FIG. That is, the drain 31 of the MOS transistor
The structure is such that b and the base 25 of the bipolar transistor are directly connected by a single crystal silicon film. Also, VD
Between the collector 22 serving as the D terminal and the drain 31b, there was a resistance R1 of 7.1Ω, and between the drain 31b and the base 25 there was a resistance of IOkΩ. Furthermore, M
The ON resistance of the OS transistor was 42.9Ω.

On the other hand, when the DC characteristics of the bipolar transistor were quantified, the results shown in FIG. 3 were obtained. Here, the horizontal axis is the pace emitter voltage VBE, the vertical axis is the collector current density Jc, and V cE! It was fixed at 5V. It can be seen from this figure that good transistor characteristics are exhibited. Furthermore, when the lifetime of electrons in the base was determined based on this transistor characteristic, it was found to be 10-6 sec, which is approximately the same as that of a transistor formed on a normal bulk substrate.

Next, the operating characteristics of the device in this example will be explained. Now, with Vno=-5V, apply -1.OV, which is larger than the threshold voltage, to the gate of the MOS transistor, and
The S transistor was turned on.

At this time, the potential at point P shown in FIG. 2 was determined by the distribution of the resistor Rl and the ON resistance of the MOS transistor, and its value was -4.29V. Furthermore, there was a resistor R2 between P and Q, and the potential at point Q was -4.3V. In this case, the V BE of the bipolar transistor is −0,7
V, the base current was approximately 1O-6A/ctn2, and the collector current Jc was 10-'A/co+2.

Furthermore, when the MOS transistor is in the OFF state, the potential at point P is -4.9V, the potential at point Q is approximately the same, the base current is 10-■A/cm2 or less, and the collector current Jc is 10- +1A/am2. That is, MOS
As the transistor turns ON and OFF, the collector current Jc of the bipolar transistor increases from 10-' to 10-''A/
It was found that it varies between cm2. In other words, it was found that good switching characteristics could be obtained.

In this way, according to this embodiment, some MOS transistors and some bipolar transistors are on the same substrate! It is possible to realize a semiconductor device provided with a TL repeater, and the device characteristics thereof can also be made sufficiently good. Also,
Compared to conventional devices, the occupied area is reduced by about 55% since the device is not simply arranged in parallel, and is therefore extremely effective for integration. Furthermore, the manufacturing process is relatively simple, and the factors that cause deterioration at high temperatures can be extremely reduced.

FIG. 4 is a sectional view showing the manufacturing process of a semiconductor device according to a second embodiment of the present invention. First, as shown in FIG. 4(a), a field oxide film 42 is formed on a p-type wheel crystal Si substrate 41 for cable isolation. Next, a gate oxide film 43 is formed by, for example, a dry oxidation method, and a poly7crystalline silicon film 44 is further deposited and patterned to form a gate portion. Using the gate portion as a mask, arsenic ions are implanted to form source/drain regions 45a and 45b of the MOS transistors by a so-called self-line method.

Next, as shown in Figure 4(b), CVD-3i was applied to the entire surface.
After depositing the n2 film 46, the Si layer located on the drain part is
The O2 film 46 is removed by etching.

Subsequently, selective epitaxial growth is performed at 700° C. while doping with arsenic so as to form a semiconductor of the same type as the drain. As a result, an n-type single crystal silicon layer 47 is grown directly on the drain portion. Note that this region (silicon layer 47) becomes the base of the bipolar transistor.

Next, as shown in FIG. 4(C), a polycrystalline silicon film 4 is formed.
By epitaxially growing 8 at 600°C and further ion-implanting arsenic using an ion-implantation mask,
Bipolar transistor emitter 49 and collector 50
form. Thereafter, annealing is performed in a nitrogen atmosphere at 600° C. in order to improve the crystallinity of the bipolar transistor portion and to activate the implanted impurity ions.

Finally, as shown in Figure 4(d), C
A VD-3in2 film 52 is formed, a gate contact hole and a source contact hole of a MOS transistor, an emitter contact hole and a collector contact hole of a bipolar transistor are opened, and an AiI wiring 52 is formed.
administer.

Through such a manufacturing process, it is possible to form a bipolar transistor in which the base is in direct contact with the drain portion of the MOS transistor, and it is possible to realize a highly integrated and highly reliable semiconductor device. In particular, the great advantage of this embodiment is that the so-called recrystallization step can be uniformly performed at low temperatures and with high reliability. Therefore,
When a single-crystal silicon layer is formed on a MOS transistor, the device characteristics of the MOS transistor are not deteriorated, and since the single-crystal silicon layer can be formed homogeneously, the characteristics of a bipolar transistor can be improved. Further, since the drain of the MOS transistor and the base of the bipolar transistor are in direct contact, fewer A, 17 wirings, etc., are required to connect each transistor, which has the advantage of simplifying the manufacturing process.

FIG. 5 is a sectional view showing a schematic configuration of a semiconductor device according to a third embodiment of the present invention. This is a high-speed Bi/CMO
This is an example of an S inverter, and this inverter is formed as follows.

First, p-channel and n-channel MOSs each having a source, drain, and gate on the surface of a p-type silicon substrate 61
Transistors 4 and 65 are formed. Here, the source and drain regions of the MOS transistors 64 and 65 are respectively p+ type impurity regions, and are p-channel M
The O3 transistor 5 is formed in an n-well 63 formed on the surface of the substrate. Furthermore, a metal film or a polycrystalline silicon film 6 that becomes a resistor is formed on a part of the element isolation insulating film 62.
6 is formed, and the drains of MOS transistors 64 and 65 are connected to each other.

Next, an insulating film 6 such as a silicon oxide film is formed on the entire surface of the substrate 61.
7 is formed, an opening is provided in a part of the insulating film 67 to expose the surface of the substrate. Furthermore, after forming a polycrystalline silicon film on the entire surface, the polycrystalline silicon film is made into a single crystal silicon film 67 using a solid-phase vapor deposition technique. At this time,
A single crystal silicon layer is buried in the opening by selective epitaxial growth in the same manner as described in the previous embodiment.

Next, ions of arsenic or boron are applied to desired regions of the silicon film 67 at an accelerating voltage of 30 kV, for example.
Dose amount I x 10”co+-2 and accelerating voltage eok
v.

Ion implantation is performed at a dose of HI x 10"Cm-2 to form two bipolar transistors 68 and 69. Here, the ion implantation is performed by connecting the source/drain of the MOS transistor and the collector and base of the bipolar transistor. In this embodiment, the drain of the n-channel MOS transistor RO 4 and the collector of the bipolar transistor 68 (both n+ type regions are in direct contact with each other, and the drain of the p-channel MOS transistor RO 5 and the collector of the bipolar transistor 68 are in direct contact with each other).
9 (both p+ type regions are directly contacted). Thereafter, the MOS transistor and the bipolar transistor are connected using A, Q wiring, etc. to obtain a Bi/CMOS inverter.

An equivalent circuit diagram of the inverter thus formed is shown in FIG. In this circuit, MOS transistor 64.
When the input signal to the gate electrode 65 is "H", the transistor 64 is turned off, and the h transistor 5 is turned on.
The output signals to the emitters or collectors of the bipolar transistors 68 and 69 become "L". Conversely, when the input signal is "L", the output signal is "H". For example, if we give the drain voltage Voo = 5V and the input signal 5V, the output signal will be CO, 4V, and the input signal will be O.
When V was applied, an output signal of 4.5V was obtained.

As a result, it was found that the Bi/CMOS inverter in this example sufficiently satisfies the electrical characteristics as an inverter circuit element.

As described above, according to this embodiment, it is possible to realize a non-conductor device having a CMOS transistor and a bipolar transistor on the same substrate.

Furthermore, compared to conventional devices, it is possible to reduce the occupied area by about half, which is extremely effective for integration.

Furthermore, the manufacturing process is relatively simple, and there are few processes that require high temperatures and long periods of time, so that factors that degrade device characteristics can be extremely reduced.

Note that the present invention is not limited to each of the embodiments described above. For example, as a method of selectively forming single crystal regions, it is also possible to use a technique such as etching. Furthermore, the conditions for silicon ion implantation and low-temperature annealing for recrystallization can be changed as appropriate as long as the recrystallization of polycrystalline silicon is performed satisfactorily, as shown in the embodiments. Further, the ~10S transistor is not necessarily limited to a P channel E type, but may also be applied to an N channel or D type. Furthermore, it goes without saying that the source instead of the drain can be similarly formed on the base of the bipolar transistor. Furthermore, the substrate material and thin film material are not necessarily limited to silicon;
Various semiconductors can be used. In addition, as a modification of the first embodiment, a bipolar transistor is formed in the substrate, an insulating film having a partial opening is deposited thereon, and a single crystal silicon layer is formed in the opening by selective epitaxial growth. It is also possible to form a silicon layer for forming a MOS transistor in contact with the silicon layer. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a semiconductor device in which a MOS transistor and a bipolar transistor are partially overlapped on the same substrate, and the device characteristics thereof are also sufficiently good. can be taken as a thing. Furthermore, compared to conventional devices, the occupied area is reduced by about 55% since the device is not simply configured in parallel, and is therefore extremely effective for integration. Furthermore, the manufacturing process is relatively simple, and the factors that cause deterioration at high temperatures can be extremely reduced.

Fig. 1 is a cross-sectional view showing the manufacturing process, Fig. 2 is an equivalent circuit diagram, Fig. 3 is a characteristic diagram showing changes in collector current density Jc with respect to VBH, and Fig. 4 is a diagram showing the change in collector current density Jc with respect to VBH. 5 and 6 are cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention, and are for explaining the semiconductor device according to the third embodiment of the present invention. 6 is a sectional view showing a schematic configuration, FIG. 6 is an equivalent circuit diagram, and FIG. 7 is a sectional view showing a manufacturing process of a conventional device.

21... Single crystal silicon substrate, 22... n+ region collector), 23.27... SiO2 film, 24...
Embedded single crystal layer, 25...P type layer (base), 26.
... n-type layer emitter), 28b... single crystal silicon film, two... gate oxide film, 30... polycrystalline silicon film (gate), 31a, 31b... p+ type layer (source・Drain region), 32...SiO2 film (insulating film), 32a, ~, 32d... Contact hole.

Applicant's agent: Patent attorney Takehiko Suzue ;;; 1 d Figure 3 Figure 5 Vo.

Claims (6)

[Claims] (1) It has a structure in which a MOS transistor and a bipolar transistor are stacked on a semiconductor substrate, and the source or drain of the MOS transistor and the base of the bipolar transistor are of the same conductivity type and are directly connected. Semiconductor equipment. (2) A first single-crystal semiconductor thin film selectively formed on a semiconductor substrate, a bipolar transistor formed in this semiconductor thin film and the substrate, and a bipolar transistor formed on the substrate with an insulating film interposed therebetween. a second single-crystal semiconductor thin film formed in the same manner and having a part directly connected to the base of the bipolar transistor; and a part formed in the second semiconductor thin film and connected to the base of the bipolar transistor serving as a source or a drain. 1. A semiconductor device comprising: a MOS transistor. (3) forming an insulating film on a semiconductor substrate; making a hole in a part of the insulating film reaching the substrate; filling the hole with a first single-crystal semiconductor thin film; 1
forming a bipolar transistor in the semiconductor thin film and the substrate; forming a second single crystal semiconductor thin film on the insulating film and the first semiconductor thin film; and forming a source or a bipolar transistor on the second semiconductor thin film. forming a MOS transistor whose drain is in direct contact with the base of the bipolar transistor. (4) a MOS transistor formed on a semiconductor substrate;
A single crystal semiconductor thin film formed on the MOS transistor and the substrate via an insulating film and a part of which is directly connected to the source or drain of the MOS transistor; A semiconductor device comprising a bipolar transistor whose connected portion is a base. (5) Forming a MOS transistor on a semiconductor substrate, forming a single crystal semiconductor thin film on the substrate and the MOS transistor via an insulating film, and partially forming the MOS transistor on the substrate and the MOS transistor.
A method for manufacturing a semiconductor device, comprising the steps of: bringing the bipolar transistor into direct contact with the source or drain of the transistor; and forming a bipolar transistor in the semiconductor thin film, the base of which comes into direct contact with the source or drain of the MOS transistor. (6) A complementary MOS transistor provided on a semiconductor substrate, a single crystal semiconductor thin film formed on the transistor and the substrate via an insulating film, and two bipolar transistors formed in this semiconductor thin film. A semiconductor device comprising: an inverter configured by connecting the two MOS transistors and the two bipolar transistors.