JP3276168B2 - Manufacturing method of thin film SOI substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates <br/> the manufacturing method of the thin film SOI substrate. More specifically, semiconductor can be prevented it is possible to reduce the thickness of the semiconductor crystal layer of the element forming region, the occurrence of stress in the semiconductor crystal layer
About the manufacturing method of a thin film SOI substrate capable of forming a body unit.

[0002] In this specification, SOI is used in the meaning of a semiconductor crystal layer on an insulating film, and is not limited to a silicon semiconductor but is used in a broad sense including a semiconductor.

[0003]

2. Description of the Related Art A conventional SOI substrate manufacturing method is shown in FIG.
First, a silicon oxide film as an insulating film is formed on a silicon substrate 21.
22 is formed by, for example, a CVD method (see step a in FIG. 4). Next, another silicon substrate 31 is bonded onto the silicon oxide film 22 (see step b in FIG. 4), and both are brought into close contact by performing a heat treatment (see step c in FIG. 4). Next, the upper silicon substrate 31 is ground to a desired thickness using a grinder or the like, and finally the surface is mirror-polished to obtain an SOI substrate (see step d in FIG. 4).

[0004]

However, in the conventional manufacturing method described above, since the upper silicon substrate is mechanically polished to obtain a desired film thickness, it is difficult to control the film thickness by polishing, and it For example, it was difficult to obtain a thin silicon layer of about 1 μm or less. Further, since the upper silicon substrate is directly bonded to the insulating film, there is a problem that stress is generated in the upper silicon substrate and crystal defects are generated in the semiconductor crystal.

SUMMARY OF THE INVENTION In view of the circumstances described above, an object of the present invention is to provide a method of manufacturing a thin film SOI substrate that can be made thin and does not generate stress in the film.

[0006] Still another object of the present invention, element isolation is performed completely, no substrate-capacity, high-speed device and the high-voltage element,
Furthermore, semiconductor devices capable of realizing latch-up-free elements , bipolar semiconductor devices of high speed, high withstand voltage and low power consumption.
It is an object of the present invention to provide a method for manufacturing a thin film SOI substrate on which a device can be formed .

[0007]

[0008]

Preparation of a thin film SOI substrate SUMMARY OF THE INVENTION The present invention includes the steps of providing a recess in the surface of the semiconductor substrate, the
Forming an insulating film on the semiconductor substrate including the inside of the concave portion, and substantially forming a surface on the insulating film including the inside of the concave portion.
Depositing a semiconductor polycrystalline layer so as to be flat, bonding another semiconductor substrate on the semiconductor polycrystalline layer, and thinning the another semiconductor substrate by mechanical polishing.
Characterized by heating the semiconductor substrate side of the Luo said another, comprising the steps of a single crystal of the previous SL semiconductor polycrystalline layer as a seed the another semiconductor substrate, that comprises the step of removing at least the another semiconductor substrate And

[0009]

[0010]

[0011]

According to the present invention, since a concave portion is provided on the surface of a semiconductor substrate and the thickness of the single crystal layer can be controlled by using the concave portion, a semiconductor crystal layer thinner than the conventional one can be obtained. In addition, since the single crystal layer is not formed directly on the insulating film, but is formed as a polycrystalline layer to be single crystallized, no stress is generated in the single crystal layer.

Furthermore, if a semiconductor circuit is formed in an element forming region formed of a thin semiconductor crystal layer in the recess, each element or each element group is completely insulated by an insulating film, and the withstand voltage between elements is reduced. Get higher. Further, since no parasitic capacitance occurs on the substrate, high-speed operation can be realized. Furthermore, latch-up can be free, and the bipolar semiconductor device has no parasitic capacitance and operates with low power consumption.

[0013]

Next, referring to the drawings, the thin film S of the present invention will be described.
The method of manufacturing the OI substrate will be described in detail. FIG. 1 is a process chart showing a method for manufacturing a thin film SOI substrate according to one embodiment of the present invention.

First, as shown in step a of FIG. 1, a recess 8 is provided on a semiconductor substrate 1. As a specific example, a resist film is applied to the surface of the silicon semiconductor substrate 1, and a resist pattern is formed using a mask having a concave portion to be formed. Then, using the patterned photoresist 3 as a mask, a part of the substrate is removed by etching to form a recess having a depth of about 1.5 μm.

Next, the photoresist 3 is removed, and an insulating film 2 and a semiconductor polycrystalline layer 4 are formed on the semiconductor substrate 1 in this order. As a specific example, the photoresist 3 is removed by oxygen plasma, a gas of monosilane (SiH ₄ ) and nitrogen suboxide (N ₂ O) is introduced, and the temperature is 800 ° C.
A silicon oxide film is deposited by the LP-CVD method under the conditions described above. Next, a polycrystalline silicon layer 4 is deposited on the silicon oxide film by LP-CVD using a monosilane gas at a temperature of 700 ° C. In this case, the deposition is continued until the surface of the polycrystalline silicon layer 4 becomes substantially flat (see step b in FIG. 1).

Next, as shown in step c of FIG. 1, another semiconductor substrate is placed on the semiconductor polycrystalline layer 4 deposited in step b.
11 are bonded to each other by heat treatment. As a specific example, another silicon substrate is placed on the polycrystalline silicon layer 4.
The polycrystalline silicon layer 4 is bonded to the silicon substrate 11 by performing a heat treatment (temperature: about 1200 ° C., time: about 2 hours) in a mixed atmosphere of argon (Ar) and oxygen (O ₂ ). . Next, the bonded upper silicon substrate 11 is thinned by mechanical polishing. In this case, in order to improve heat transfer in the subsequent annealing step, it is preferable to make the upper silicon substrate 11 as thin as possible, specifically, about 5 μm.

Next, as shown in steps d to e of FIG.
Heat treatment is performed on the thinned semiconductor substrate 11 by a strip heater or the like, and the semiconductor substrate 11 is used as a seed to monocrystallize the semiconductor polycrystalline layer. Specifically, the heater temperature
The heater is scanned at a speed of 2 mm / sec at a temperature of 1000 to 1300 ° C., and the polycrystalline silicon layer is turned into a single crystal silicon layer 5 using the silicon substrate as a seed.

Next, as shown in step f of FIG. 1, the surface of the single crystal semiconductor layer is mechanically polished from the side of the another silicon substrate 11 bonded to remove the single crystal semiconductor layer. At this time, the insulating film 2 above the concave portion 6, that is, the insulating film 2 other than the concave portion 6 functions as a stopper, and the film thickness of the element forming region 7 can be accurately controlled. That is, the film thickness can be accurately controlled by controlling the depth of the concave portion.
The following thinning is possible.

In the above-described specific example, the semiconductor substrate 1 and the deposited semiconductor polycrystalline layer have been described using silicon as an example.
The same applies to other semiconductor materials such as SiC and SiGe other than silicon. Further, although the description has been given of the example of the silicon oxide film as the insulating film, the same can be applied to other silicon nitride films and the like.

Further, in the example described above, a polycrystalline semiconductor layer is heat-treated by a ZMR method using a strip heater in order to monocrystallize a polycrystalline semiconductor layer. It is only necessary to be able to heat and heat the substrate, such as electron beam annealing using an electron beam, light lamp annealing such as a halogen lamp, and discharge lamp annealing.
Other heating methods may be used.

The SOI substrate obtained by the above-described manufacturing method is
An island-shaped semiconductor single crystal layer is accurately formed in a thin layer on the insulating film, and a semiconductor circuit can be formed in the semiconductor crystal layer, and the element formation region 7 can be formed. This element formation region 7
One or a plurality of the island-shaped element formation regions can be formed on the substrate according to the purpose of the semiconductor circuit formed in the semiconductor device.

In each of the island-shaped element forming regions, one element or one group including a plurality of elements is formed by a conventional semiconductor device manufacturing process, so that insulation between elements is completely achieved, and A semiconductor device with excellent withstand voltage and radiation resistance can be obtained, and since a parasitic capacitance and a pn junction are not formed, a latch-up-free semiconductor device that operates at high speed can be realized.

Further, a semiconductor layer is formed again via a protective insulating film on the surface of the semiconductor device in which the semiconductor circuit is formed in the element forming region, and the island-shaped element is formed again by the same process as the above-described SOI substrate manufacturing method. A formation region is formed, and a semiconductor circuit can be formed. By repeating this method, a three-dimensional semiconductor circuit can be formed.
As a result, a semiconductor device with a high degree of integration and high characteristics can be obtained with a small chip having a small area.

Next, an example in which a bipolar transistor and a MOS transistor are formed in the element formation region will be described with reference to the drawings.

First, FIG. 2 shows an example in which a bipolar transistor is formed in the element forming region 7 of the SOI substrate.

The bipolar transistor shown in FIG. 2 is based on the steps described earlier with reference to FIG.
A first conductivity type high-concentration region (n ⁺ type region) 22 is formed at the bottom of the first conductivity type (n-type) element formation region 7 by ion implantation or the like, and further diffused or ionized into the element formation region. The second conductivity type (p-type) region 2 is formed by a conventional method such as an implantation method.
3. A first conductivity type high concentration region 24 is formed, and a bipolar transistor is configured as a collector region 21, a base region 22, and an emitter region 23, respectively. High-concentration regions 25 and 26 for ohmic contact are formed in the collector region 21 and the base region 22, respectively, contact holes are formed in a protective film 27 formed on the surface, and a collector electrode 28, a base electrode 29, and an emitter electrode are formed. 20 are formed to form a bipolar transistor. Reference numeral 19 denotes an element isolation region (silicon oxide film) for preventing lateral leakage.

For comparison, FIG. 5 is an explanatory sectional view of a conventional bipolar transistor.

[0028] In FIG. 5, the n ⁺ buried layer 51 for low resistance is formed on a semiconductor substrate (p-type) 1, n and the collector region 52 ^- -type epitaxial layer is formed, further the base A p-type region to be a region 53 and a source region 54
An n ⁺ -type region is formed to a collector electrode 55, a source electrode 56, base electrode 57 is formed. LOCOS oxide film to isolate this transistor part from other areas
Under the LOCOS oxide film 58 and the p-type region 59 formed through the semiconductor substrate under the LOCOS oxide film 58, it is separated. Therefore, the horizontal separation is performed by the LOCOS oxide film and the pn junction, while only the high concentration buried layer is provided in the vertical direction. For this reason, the separation is insufficient in both the horizontal and vertical directions, and there is a problem in the withstand voltage between the elements, and the speed of the elements is hindered due to the substrate capacitance.

On the other hand, in the bipolar transistor shown in FIG. 2 of the present invention, both the vertical and horizontal directions are completely separated by the oxide film, and since there is no substrate capacitance, a high-speed element can be realized. Further, a semiconductor device having a high withstand voltage in which the withstand voltage between elements is improved and low power consumption can be obtained, and a latch-up-free element can be realized.

Next, when a MOS semiconductor device is formed using the SOI substrate according to the present invention, each element is completely separated by an insulating film as in the case of a bipolar device.
There is no escape through the LOCOS, the withstand voltage in the lateral direction is greatly improved, and there is no need to form a channel stop implant below the LOCOS oxide film, so that no parasitic transistor is formed and latch-up occurs. Not even. MOS on SOI substrate according to the present invention
FIG. 3 shows an example in which a transistor is formed.

The MOS transistor shown in FIG. 3 is constructed by following the steps described earlier with reference to FIG.
A gate electrode film 34 is formed on the surface of the element region 7 with a gate insulating film 33 interposed therebetween. Impurities are introduced from both sides of the gate electrode film 34, and the source region (n) is formed in the element formation region (p-type) 7.
⁺ Type) 31 and the drain region 22 are formed, a contact hole is formed in the protective film 35 formed on the surface, and the source electrode 36,
The gate electrode 37 and the drain electrode 38 are formed to form a MOS transistor. In this configuration, the thickness of the element forming region 7 is formed as a thin layer of about 1 μm or less, and the depletion layer formed by the channel region p ⁻ reaches the insulating film 2 directly, so that the switching characteristics are excellent.

FIG. 6 is an explanatory sectional view of a conventional MOS transistor for comparison. In the example shown in FIG.
Part of the surface is used as an element region, and the source region 6
3. A drain region 64 is formed, and lateral separation is performed using a LOCOS oxide film 62. Further, vertical separation is not particularly performed. On the surface of the substrate 61, a gate electrode film 66 is formed via an insulating film 65, a protective film 67 is formed, and electrodes 68, 69, and 70 are formed.

In the example shown in FIG. 6, a substrate capacity other than the element region is generated, which hinders an increase in speed.
In some cases, a channel stop implant 71 is required under the LOCOS oxide film. Further, there is a problem that latch-up occurs.

On the other hand, FIG.
In the MOS transistor shown in (1), the substrate and the element region are completely separated by a silicon oxide film, and the source region 21 and the drain region 22 extend to the insulating film 2 and no common region is formed. Therefore, unlike the prior art, both the vertical and horizontal directions are completely separated by the silicon oxide film. Therefore, it is possible to realize a latch-up-free high-speed element without substrate capacitance. Further, the withstand voltage in the lateral direction is improved, and leakage between elements can be prevented.

As described above, the bipolar transistor and the MO
Although the case where the SOI substrate obtained by the present invention is applied when manufacturing an S transistor has been described, the present invention can be suitably applied to an IC, a BI-CMOS or the like in which these are combined.

[0036]

As described above, according to the manufacturing method of the present invention, since the thickness of the single crystal layer is controlled by using the concave portion provided on the surface of the semiconductor substrate, an extremely controlled ultra-thin film is obtained. Is obtained. In addition, since a single crystal layer is not formed directly on the insulating film but is formed into a single crystal by forming a polycrystalline layer, no stress is generated in the single crystal layer and the semiconductor crystal has a small number of defects. Layers are obtained.

A bipolar or MO using this substrate
An S semiconductor device is a semiconductor device in which elements or element groups are completely separated by an insulating film. Bipolar can be operated with particularly low power consumption, and high speed, high withstand voltage, radiation resistance are common to both. A semiconductor device which is strong against aging is obtained.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a thin film SOI substrate according to one embodiment of the present invention.

FIG. 2 is an explanatory cross-sectional view of a bipolar transistor formed on a substrate obtained by a manufacturing method of the present invention.

FIG. 3 is an explanatory sectional view of a MOS transistor formed on a substrate obtained by the manufacturing method of the present invention.

FIG. 4 is a process chart showing a conventional SOI substrate manufacturing method.

FIG. 5 is an explanatory cross-sectional view of a bipolar transistor formed using a conventional technique.

FIG. 6 is an explanatory cross-sectional view of a MOS transistor formed using a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 4 Semiconductor polycrystal layer 6 Semiconductor single crystal layer 7 Element formation region 8 Depression 11 Another semiconductor substrate 22 High concentration impurity region

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-284416 (JP, A) JP-A-60-244036 (JP, A) JP-A-60-207363 (JP, A) JP-A 64-64 18248 (JP, A) JP-A-4-53123 (JP, A) JP-A-4-180674 (JP, A) JP-A-62-130510 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/12 H01L 21/02 H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (2)

(57) [Claims] A step of forming a concave portion on the surface of the semiconductor substrate, a step of forming an insulating film on the semiconductor substrate including the inside of the concave portion, and a step of forming a real surface on the insulating film including the inside of the concave portion.
Depositing a semiconductor polycrystalline layer so as to be qualitatively flat, bonding another semiconductor substrate on the semiconductor polycrystalline layer, and thinning the another semiconductor substrate by mechanical polishing.
And then heating from the other semiconductor substrate side,
The different the steps of the single-crystallized pre Symbol semiconductor polycrystalline layer as a seed to a semiconductor substrate, a thin film SOI substrate, comprising the step of removing at least the another semiconductor substrate manufacturing method. 2. The thickness of the semiconductor crystal layer is controlled by the depth of the recess by forming the single crystallized semiconductor crystal layer by shaving the semiconductor crystal layer to be flush with the upper surface of the recess. The method according to claim 1, wherein: