JPH02170540A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a bipolar transistor, whose gain is large and whose switching speed is fast, in a simple process by a method wherein the vertical bipolar transistor is formed on an insulating substrate or an insulating layer and base lead-out parts are formed up to the upper part of the interface between a window and the insulating substrate or the insulating layer. CONSTITUTION:An n-type single crystal silicon layer 102, which is used as a collector, is epitaxially grown on an insulating substrate 102 and a p-type silicon thin base layer 103 is epitaxially grown thereon. Moreover, after an insulating layer 104 is formed on the upper part of the layer 103, windows 105 are opened to perform a thermal diffusion of boron and base lead-out parts 106 are formed in such a way as to reach sufficiently up to the substrate (in such a way that an n-type collector layer is left between the base lead-out parts and the substrate and a large additional capacity is not formed). Moreover, after an insulating layer 107 is laminated, a window for emitter formation part use is formed and an n-type polycrystalline silicon emitter is formed by an LPCVD method. Thereby, a high-speed and large-gain bipolar transistor can be realized in a simple process.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates, in part, to the connection of semiconductors of different conductivity types [Prior Art] Conventionally, a bipolar transistor is formed on a single crystal semiconductor substrate, and -Ba is A structure (Brehner type) as shown in FIG. 3(a) has been used. 301 is aluminum wiring.

However, in such a structure, the external resistance of the base is high because the conductivity of the base extension is low, and the switching speed of the transistor is reduced because the junction capacitance directly under the base extension is large. For this purpose, protons and oxygen ions are injected into the lower part of the external base extraction part to selectively make it resistive and reduce the junction capacitance directly under the base extraction part (Junior High School: Proceedings of the 47th Japan Society of Applied Physics, 613 (1986)). , for example, S engineering C
OS(C05(Side Ba5e'Contact
5 structure) which has a self-line structure and has almost no external base region has been proposed. (T.

N a k a m u r a, T, m i
y az a k i, s.

Takahashi, T., Kure, T.
0kabe and M, Nagat
a: IEEE Trans, Electr
on Devices.

vo 1. ED-29, p p, 59
6-600. 1982) Figure 3(b) shows 5ICO3
FIG. 3 is a cross-sectional view of the structure. With this structure, there is almost no additional capacitance due to the base extension, so the switching speed of the transistor can be dramatically improved. Here, the base extension portion is formed of polycrystalline silicon 302.

[Problems to be solved by the invention] However, in order to actually realize the 5ICOS structure, the process is quite complicated and requires advanced production technology, which increases the number of processes and lowers the yield, leading to high costs. It is expected that

[Means for Solving the Problems] Accordingly, in the present invention, a vertical bipolar transistor is formed on an insulating substrate or an insulating layer, and a base extension portion is formed up to the interface of the insulating substrate or the insulating layer. The purpose of this invention is to produce a bipolar transistor with a large gain and high switching speed through a simple process due to its small collector capacitance (or base-emitter capacitance).

[Example] The present invention will be explained below according to the examples.

FIG. 1 is a sectional view of an embodiment of an npn type bipolar transistor manufactured using the present invention. An n-type wheel crystal silicon layer 102 that will become a collector is formed on an insulating substrate 101 by LPC.
Epitaxial growth is performed using the VD method (low pressure chemical vapor deposition method), and a thin base layer 103 of p-type silicon is formed on top of the epitaxial growth.
is grown by MBE (molecular beam epitaxial) to form an insulating layer 104 thereon (FIG. 1(a)). Here, a window 105 is opened in the insulating layer 104 to allow thermal diffusion of boron so that the base extension 106 can sufficiently reach the insulating substrate (the collector n-layer remains between the base extension and the insulating substrate and has a large additional capacitance). (Fig. 1(b)). After laminating the insulating layer 107 (FIG. 1(C)), a window for an emitter formation portion is created, and an n-type polycrystalline silicon emitter 108 is formed by the LPCVD method (FIG. 1(d)). RCA cleaning (W, Ke
rn and D.Puotinen: RCA
Review, vol, 32. pp.

187-206.1970) or other oxide film removal cleaning, unnecessary levels can be reduced.

Moreover, more desirable bonding characteristics can be obtained by performing such interface cleaning without breaking the vacuum within the emitter forming tray. In addition, here, the collector layer 102 is made of LPC.
Although it is formed by epitaxial growth using the VD method,
APCVD (Atmospheric pressure CVD)-PECVD-MOCVD
It may be formed by vapor phase epitaxial growth using methods such as (organometallic CVD) or MBE, or a non-single crystal silicon film formed by EB (electron beam) evaporation, PECVD-LPCVD, etc. may be formed by SPE (solid phase epitaxial growth). growth method) and ZMR (
A single crystal obtained by a zone melt recrystallization method may also be used. In addition, here, the base layer 103 is made of single crystal silicon formed by MBE, but any of the collector layer forming methods described above may be used, and the surface of the collector layer may also be formed by laser doping or low-speed I/O. /I (
A thin base layer 103 can be formed on the collector layer 102 by ion implantation or the like.

The emitter layer 108 is made of polycrystalline silicon formed by LPCVD, but it may also be formed by PECVD, or it may be made of amorphous or microcrystalline silicon formed by LPCVD, PECVD, EB evaporation, etc. Non-single-crystal silicon, or even single-crystal silicon formed by the method described above (for forming the collector layer and base layer) may be used.

Although the base extension portion 106 is formed by thermal diffusion, it may also be formed by I/I or ion shower. In this case, since the base extension part 106 can be formed without forming the insulating layer 104 on the base, the number of steps can be reduced by at least two in addition to the formation of the window 105. However, in this method, a resist mask or the like is formed on the part that will become the base-emitter junction interface, so after removing the resist and before forming the insulating layer, or just before forming the emitter 108 (cleaning to remove oxide at the base-emitter junction interface). Immediately after the cleaning is completed, it is better to perform cleaning to remove any impurities. Also, Si on the base
Form an insulating layer like C2 and use it as a mask to connect I/I
etc. may be done.

FIG. 2 shows an example in which a collector-top type bipolar transistor was manufactured using the semiconductor device manufacturing method of the present invention. First, as shown in FIGS. 2(a) and 2(b), a low-resistance, high-concentration n-type single-crystal silicon layer (emitter wiring) 202 is placed on an insulating substrate 2, and an n-type single-crystal silicon emitter portion 2
03. A base portion 204 of n-type single crystal silicon and a collector portion 205 of n-type single crystal silicon are formed and patterned for element isolation. Here, 206 is an insulating layer.

After that, as shown in FIG. 2(C), by forming the base extension part 207 so that no emitter layer remains between the base extension part and the insulating substrate, a fast transistor operation can be realized. . FIG. 2(d) is a diagram of this transistor seen from above. In addition, in this manufacturing method, the emitter, base, and collector are all manufactured by self-line (each part is formed in the process of forming the base extension part), so reproducibility is very good when manufacturing the element.

Furthermore, a Peter junction bipolar transistor (HBT) is created in the same process by replacing the emitter part in FIG. 1 108 and FIG. Especially in the case of the structure shown in Fig. 2, the ion voltage is high in the pn junction formed of a material with a wide bandgap, so the amount of minority carriers accumulated in the junction is suppressed to a low level, and as a result, the amount of minority carriers accumulated in the junction is kept low. The increase in emitter capacitance caused by the junction between the base portion and the emitter portion 207 is suppressed, and even higher-speed transistor operation is possible.Furthermore, by using the semiconductor device manufacturing method of the present invention, the impurity concentration in the base portion can be lowered. Therefore, it is possible to easily manufacture a ballistic conduction transistor in which carriers accelerated by the Peter junction reach the collector portion without being scattered at the base portion.

In addition, thermal diffusion method is also possible as a method for forming the base extension part, but impurity redistribution occurs due to high temperature and pn
Since the position of the junction shifts, it is preferable to use a method such as ion implantation that is low temperature and has good directivity, especially when applied to a collector top type heterojunction bipolar transistor.

By forming the bipolar transistor thus manufactured in combination with a CMO9 transistor on the same substrate, a high-speed iCMO8 circuit can be manufactured.

Although the embodiments have been described above, the present invention can be applied not only to the above embodiments but also to a wide range of semiconductor devices using heterojunctions. Further, in the above embodiment, an npn type bipolar transistor is formed, but a pnp type bipolar transistor may be formed. As the semiconductor material, an elemental semiconductor such as Ge or a compound semiconductor such as GaAS may be used, and as the impurity to be doped, P-B-As.In or the like may be used. Furthermore, it is very effective when forming on an insulating layer or on an insulating film between the eyebrows above a semiconductor device to form a three-dimensional LSI.

[Effects of the Invention] As described above, by using the present invention, it is possible to realize a high-speed, high-gain bipolar transistor with low external resistance in the base extraction part and small additional capacitance under the base extraction part through a simple process. . Further, by implementing the present invention by using different materials for the emitter portion, base portion, and band gag, it is possible to realize a heterojunction ballistic type transistor with simple steps.

Furthermore, since the semiconductor device is formed on an insulating substrate or an insulating layer, element isolation is significantly easier than when forming on a semiconductor substrate.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are diagrams showing an embodiment in which a bipolar transistor is formed on an insulating substrate using the present invention. FIGS. 2(a) to 2(d) are diagrams showing an example in which a collector top type bipolar transistor is formed on an insulating substrate using the semiconductor device manufacturing method of the present invention. FIGS. 3(a) and 3(b) are diagrams showing conventional bipolar transistors. Applicant: Seiko Epson Co., Ltd. Agent: Patent attorney: Masayoshi Kamiyanagi (1 person) Al'i surface (a) Cross section B (b) Figure 2 (a) (a) Figure 3<b)

Claims (2)

[Claims] (1) A semiconductor device formed on an insulating substrate or an insulating layer and including a p-type or n-type conductive semiconductor in a part thereof, such as a junction between a p-type semiconductor and an n-type semiconductor, or a p-type or n-type semiconductor 1. A semiconductor device characterized by having a junction between a semiconductor and an intrinsic semiconductor in a part thereof. (2) The semiconductor device according to item 1, wherein the base extension portion is formed up to the interface of the insulating substrate or the interface of the insulating layer.