JPS62217659A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62217659A JPS62217659A JP6122886A JP6122886A JPS62217659A JP S62217659 A JPS62217659 A JP S62217659A JP 6122886 A JP6122886 A JP 6122886A JP 6122886 A JP6122886 A JP 6122886A JP S62217659 A JPS62217659 A JP S62217659A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- silicon
- type
- polycrystalline silicon
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 12
- 230000003321 amplification Effects 0.000 abstract description 9
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052799 carbon Inorganic materials 0.000 abstract description 4
- -1 carbon ions Chemical class 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 101000614017 Homo sapiens Lysine-specific demethylase 3A Proteins 0.000 description 1
- 102100040581 Lysine-specific demethylase 3A Human genes 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- HJELPJZFDFLHEY-UHFFFAOYSA-N silicide(1-) Chemical compound [Si-] HJELPJZFDFLHEY-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、バイポーラトランジスタにおいて、エミッタ
に炭化硅素（８ｉ０）ｔ−用いてｔ光増幅率を高めるこ
とにより、動作速度の向上を計ったものである。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention aims to improve the operating speed of a bipolar transistor by increasing the optical amplification factor by using silicon carbide (8i0) t- for the emitter.
本発明は半導体装置、特にバイポーラトランジスタに関
する。バイポーラトランジスタは、他の半導体装置と同
様に高速動作が要求される。The present invention relates to semiconductor devices, particularly bipolar transistors. Bipolar transistors, like other semiconductor devices, are required to operate at high speed.
このため、高速動作に適する大きい電流増幅率を持りパ
イポーラトランジスタが必要とされる。Therefore, a bipolar transistor with a large current amplification factor suitable for high-speed operation is required.
従来の多結晶ンリコンエミッタを用いたプレーナｍｎｐ
ｎバイポーラトランジスタの断面構造’ｔｓｇａ図に示
す。Planar mnp using conventional polycrystalline silicon emitter
The cross-sectional structure of an n-bipolar transistor is shown in the TSGA diagram.
図中１９はｐ型の半導体基板であり、２０はｎ現の高濃
度にドーピングされた埋め込み層であり、２１はエピタ
平シャル成長されたｎ型のコレクタ層で４ｆｉ、２２は
ｐ型のベース領域でおシ、２８はｎ型のエミッタ領域で
あシ、２４はコレクタ引き出し用のｎ型領域で、２５は
基板表面を保護する ８ｉ（ｈ膜であり、２６はベース
電極のｐ型多結晶シリコン、２７はエミッタ電極のｎ型
多結晶シリコン、２８はコレクタ電極のｎ型多結晶シリ
コンである。In the figure, 19 is a p-type semiconductor substrate, 20 is a heavily doped n-type buried layer, 21 is an epitaxially grown n-type collector layer of 4fi, and 22 is a p-type base. 28 is an n-type emitter region, 24 is an n-type region for extracting the collector, 25 is an 8i (h film) that protects the substrate surface, and 26 is a p-type polycrystalline base electrode. 27 is n-type polycrystalline silicon for the emitter electrode, and 28 is n-type polycrystalline silicon for the collector electrode.
さらに、図には示していないが、これら多結晶シリコン
上にはアルミニウムの電極が＋ｆｆｌケられる０
図示のように、従来のパイボーラトランジスタのエミッ
タ部分は、ｎ型多結晶シリコンとｎ型単結晶シリコンよ
り構成されている。Furthermore, although not shown in the figure, aluminum electrodes are formed on these polycrystalline silicon layers. Composed of silicon.
従来のバイポーラトランジスタは、エミッタ領域が多結
晶シリコンと単結晶シリコンで構成されているために、
エミッタからベースへ電子が注入される時のエネルギー
障壁と、ベースからエミッタへ正孔が注入される時のエ
ネルギー障壁は等しく、不要な正孔のエミッタへの注入
が回避できないため、電流増幅率が向上されず、動作速
度の向上が困難という問題を生じていた。Conventional bipolar transistors have an emitter region composed of polycrystalline silicon and single-crystalline silicon, so
The energy barrier when electrons are injected from the emitter to the base is equal to the energy barrier when holes are injected from the base to the emitter, and since unnecessary hole injection into the emitter cannot be avoided, the current amplification factor is However, there was a problem in that it was difficult to improve the operating speed.
第１図は本発明によるｎｐｎバイポーラトランジスタの
エミッタ・ベース接合のエネルギーバンド図を模式的に
示したものである。FIG. 1 schematically shows an energy band diagram of an emitter-base junction of an npn bipolar transistor according to the present invention.
図中１はｎ型多結晶シリコンであり、２は炭素ケイオン
注入する前はｎｆｉ単結晶シリコン。In the figure, 1 is n-type polycrystalline silicon, and 2 is NFI single crystal silicon before carbon silicon ion implantation.
炭素注入後はｎ型ＳｉＣとなる。３はｐ型単結晶シリコ
ン、４は伝導帯下端のエネルギーレベル、５はフェルミ
エネルギーのレベル、６は価電子帯上端のエネルギーレ
ベルを示す。７は炭素注入前にｎ型単結晶シリコンがエ
ミツタ層として存在する時の価電子帯上端のエネルギー
レベルである。After carbon implantation, it becomes n-type SiC. 3 indicates p-type single crystal silicon, 4 indicates the energy level at the lower end of the conduction band, 5 indicates the Fermi energy level, and 6 indicates the energy level at the upper end of the valence band. 7 is the energy level at the top of the valence band when n-type single crystal silicon exists as an emitter layer before carbon implantation.
本発明は、多結晶シリコン（１）と単結晶シリコン（２
）の界面に炭素ケイオン注入し、単結晶シリコンのｎ型
層の一部もしくは全部ｔＳｉＣ層とし、エネルギーバン
ドギャップを広げることを特徴とする。The present invention combines polycrystalline silicon (1) and single crystal silicon (2).
) is characterized by implanting silicon carbon ions into the interface of the single crystal silicon to make part or all of the n-type layer of single crystal silicon into a tSiC layer to widen the energy band gap.
なか、？ｉＸ１図においてはｎ型単結晶シリコンの全部
がＳｉＣ層となった場合について示しである。inside,? The iX1 diagram shows a case where all of the n-type single crystal silicon becomes a SiC layer.
本発明によるバイポーラトランジスタのエミッタ・ベー
ス接合のエミッタ部分は、ｎ型単結晶シリコンの一部あ
るいは全部がシリコンよりエネルギーギャップの大きい
８ｉＣとなっているため、ベース（８）からエミッタ伐
）へ正孔が注入される時のエネルギー障壁は、エミッタ
（２）からベース（８）へ電子が注入される時のエネル
ギー障壁より大きい。このため、エミッタ１！流トべ一
ス電流の比はＳｉＣの存在しなりｈＱ合より大きくする
ことが可能であり、高い電流増幅率を持つバイポーラト
ランジスタが実現できる◇〔実施例〕
第２図に本発明によるバイポーラトランジスタの断面構
造を示す。以下このｆＭ造について説明する。In the emitter part of the emitter-base junction of the bipolar transistor according to the present invention, part or all of the n-type single crystal silicon is 8iC, which has a larger energy gap than silicon, so that holes flow from the base (8) to the emitter junction. The energy barrier when electrons are injected is larger than the energy barrier when electrons are injected from the emitter (2) to the base (8). For this reason, emitter 1! The ratio of current to base current can be made larger than the hQ ratio due to the presence of SiC, and a bipolar transistor with a high current amplification factor can be realized. The cross-sectional structure of is shown. This fM structure will be explained below.
基板はＰ型シリコン８を用い、ｎ十埋め込み層９を形成
し、コレクタ領域となる。ｎ−のシリコン１０？！−エ
ピタキシャル成長させる。１４はコレクタ引き出し用ｎ
十層、１１はベースとなる２層、１２はエミッタとなる
ｎ十層で、それぞれ不純物ドーピングによシ形成する。P-type silicon 8 is used as the substrate, and an n-type buried layer 9 is formed to form a collector region. n- silicon 10? ! -Grow epitaxially. 14 is for collector drawer n
10 layers, 11 are two layers serving as a base, and 12 are n10 layers serving as an emitter, each of which is formed by impurity doping.
１５は絶縁用及び基板表面保護用の８！０！である。１
６はベース電極のｐ型多結晶シリコン。15 is 8!0 for insulation and substrate surface protection! It is. 1
6 is p-type polycrystalline silicon for the base electrode.
１７はエミッタ電極のｎ型多結晶シリコン。17 is n-type polycrystalline silicon of the emitter electrode.
１３はコレクタ電極のｎ型多結晶シリコンである。１Ｂ
はエミッタ多結晶シリコンの表面から選択的にこの部分
だけに炭素をイオン注入することによって形成された８
ｉＣ７ｉＪであり、この層の存在によって電流増幅率の
増大がもたらされる。13 is n-type polycrystalline silicon of the collector electrode. 1B
is formed by selectively implanting carbon ions only in this part of the surface of the emitter polycrystalline silicon.
iC7iJ, and the presence of this layer brings about an increase in current amplification factor.
本発明によれば、エミッタ領域の多結晶シリコンと単結
晶シリコンの界面に８ｉＣｆｒＪｌ形成したので、従来
のトランジスタに比べ、電流増幅率を向上することがで
き、高速動作に適する。According to the present invention, since 8iCfrJl is formed at the interface between polycrystalline silicon and single crystal silicon in the emitter region, the current amplification factor can be improved compared to conventional transistors, making it suitable for high-speed operation.
また、本発明のバイポーラトランジスタの８ｉＣと単結
晶シリコンとの界面は単結晶シリコンバルク内に形成さ
れるため、８ｉ０１１２エミフタ上に堆積して製造した
バイポーラトランジスタと比べ、界面阜位密既が減少で
きる。In addition, since the interface between 8iC and single crystal silicon in the bipolar transistor of the present invention is formed within the single crystal silicon bulk, the interface density can be reduced compared to a bipolar transistor manufactured by depositing it on an 8i0112 emitter. .
このため、ベース電流の界面再結合による成分を減少さ
せることができ、この点にひいても電光増幅率を向上さ
せることが可能である。Therefore, the component of the base current due to interfacial recombination can be reduced, and in this respect as well, it is possible to improve the lightning amplification factor.
【図面の簡単な説明】
第１図は本発明の原理を説明する図。
第２図は本発明の詳細な説明する図。
第３図は従来例ケ説明する図である。
図に２いて、１０はコレクタ領域、 ｔ ｔハベース領
域、１２はエミッタ領域、１３は炭化硅素領域、１７は
エミッタ電極を示す。
厘理乞説明する霞
ギ１ （￥］BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating the principle of the present invention. FIG. 2 is a diagram illustrating the present invention in detail. FIG. 3 is a diagram illustrating a conventional example. In the figure, 10 indicates a collector region, tt base region, 12 an emitter region, 13 a silicon carbide region, and 17 an emitter electrode. Kasumigi explaining the request 1 (￥)
Claims (1)
を有し、該エミッタ領域１２とエミッタ電極１７との界
面に炭化硅素領域１３が設けられてなることを特徴とす
る半導体装置。Collector region 10, base region 11 and emitter region 12
A semiconductor device comprising: a silicon carbide region 13 provided at an interface between the emitter region 12 and an emitter electrode 17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6122886A JPS62217659A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6122886A JPS62217659A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62217659A true JPS62217659A (en) | 1987-09-25 |
Family
ID=13165147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6122886A Pending JPS62217659A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62217659A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03218674A (en) * | 1989-03-29 | 1991-09-26 | Canon Inc | Semiconductor device and photoelectric conversion device provided therewith |
| CN101872786A (en) * | 2010-06-11 | 2010-10-27 | 东南大学 | Silicon carbide high pressure N-type metal oxide transistor with floating buried layer and method |
-
1986
- 1986-03-19 JP JP6122886A patent/JPS62217659A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03218674A (en) * | 1989-03-29 | 1991-09-26 | Canon Inc | Semiconductor device and photoelectric conversion device provided therewith |
| CN101872786A (en) * | 2010-06-11 | 2010-10-27 | 东南大学 | Silicon carbide high pressure N-type metal oxide transistor with floating buried layer and method |
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