JP2006173297A - Igbt - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IGBT which optimum sets the on-loss, switching speed and serge withstanding power being IGBT characteristics when the withstand voltage of a pn parasitic diode is high and low. <P>SOLUTION: A first buffer layer 2a near a silicon substrate 1 and second buffer layer 2b on other portions have a high and low concentrations of an n-type impurity, respectively, resulting in some concentration difference. This raises the concentration of the n-type impurity near the substrate 1, and hence an IGBT is obtained with a high switching speed and a sufficient L-load surge withstand power. The concentration of the n-type impurity is not high in all the buffer layers, this preventing the on-voltage being excessively high with leaving the on-loss low. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an IGBT structure capable of easily adjusting a PN diode breakdown voltage.

  FIG. 28 shows a cross-sectional configuration of a punch-through type N-type IGBT as an example of a conventionally used IGBT. As shown in this figure, in the punch-through type N-type IGBT, an N + type buffer layer J2 is formed on a P + type substrate J1, and an N− type drift layer J3 is formed on the buffer layer J2. It has a configuration (for example, see Patent Documents 1 and 2).

  In general, the higher the N-type impurity concentration in the buffer layer J2 and the thicker the buffer layer J2, the faster the IGBT switching speed and the better the L load surge resistance. On the other hand, it is known that the on-voltage increases.

Further, when the IGBT is used for mounting on a vehicle, the withstand voltage of the PN parasitic diode by the P + type substrate J1 and the buffer layer J2 is prevented so that the IGBT is not energized even if the battery terminal is reversely connected. Used. The breakdown voltage of such a PN parasitic diode is set according to the element design. When it is desired to set the breakdown voltage of the PN parasitic diode low, the design is, for example, 25 V or less, and when it is desired to set it high, the design is, for example, 40 V or more.
Japanese Patent No. 2918399 Japanese Patent No. 2526653

  However, in order for the buffer layer to perform the buffer function, the impurity concentration and thickness are determined to some extent. Therefore, when all the buffer layers are configured with a substantially uniform impurity concentration, the impurity concentration and thickness of the buffer layer are inevitably determined. For this reason, the following problems occur.

  That is, when it is desired to reduce the breakdown voltage of the PN parasitic diode, the on-voltage increases due to the high impurity concentration of the buffer layer, resulting in a problem that the chip size must be increased. Further, when it is desired to increase the breakdown voltage of the PN parasitic diode, there is a problem that the switching speed is slowed because the buffer layer concentration is low. Therefore, when the breakdown voltage of the PN parasitic diode is desired to be lowered or increased, the on-loss, switching speed, and surge resistance, which are IGBT characteristics, cannot be optimally set in either case, which is insufficient.

  Note that Patent Document 1 discloses a configuration in which an intermediate layer having a low impurity concentration is provided on the buffer layer. However, in order to suppress an increase in surge voltage during turn-off, the concentration of the intermediate layer is extremely low. It does not serve as a buffer layer.

  In view of the above points, the present invention provides an IGBT capable of optimally setting on-loss, switching speed, and surge resistance, which are IGBT characteristics, when the breakdown voltage of a PN parasitic diode is desired to be lowered or increased. Objective.

  In order to achieve the above object, according to the first aspect of the present invention, a first buffer layer (2a) of the second conductivity type is formed on the main surface side of the substrate (1) of the first conductivity type. A second conductivity type second buffer layer (2b) having an impurity concentration lower than that of the first buffer layer (2a) is formed on the surface of (2a).

  According to such a configuration, since the concentration of the second conductivity type impurity can be increased in the vicinity of the substrate (1), it is possible to obtain an IGBT having a high switching speed and sufficient L load surge withstand capability. Become. In addition, since the concentration of the second conductivity type impurity is not increased in all the buffer layers, the ON voltage does not become too high, and the ON loss can be kept small. As a result, when it is desired to reduce the breakdown voltage of the PN parasitic diode, an IGBT capable of optimally setting the on-loss, switching speed, and surge resistance, which are IGBT characteristics, can be obtained.

  In the invention according to claim 2, the distance from the position where the concentration of the second conductivity type impurity in the first buffer layer (2a) reaches the peak to the PN junction between the first buffer layer (2a) and the substrate (1) is set. When the width of the depletion layer at the PN junction at the time of reverse bias is W1, the concentration of the second conductivity type impurity in the first buffer layer (2a) is set so that the relationship of W1 ≦ D1 ≦ W1 + 3 μm is established. It is characterized by setting.

  Thus, by determining the position of the distance D1 from the location where the concentration of the second conductivity type impurity peaks in the first buffer layer (2a) to the collector layer, the film thickness of the first buffer layer (2a) can be reduced. Unnecessarily thickening can be suppressed. As a result, it is possible to suppress the film thickness of the first buffer layer (2a) where the concentration of the second conductivity type impurity is high as much as possible, and it is possible to reduce the increase in the ON voltage.

  In the invention according to claim 3, the first conductivity type layer (1a) having a higher concentration of the first conductivity type impurities than the substrate (1) is provided on the main surface or surface layer portion of the substrate (1). The first buffer layer (2a) is formed on the first conductivity type layer (1a).

  As described above, the first conductivity type layer (1a) in which the concentration of the first conductivity type impurities is higher than that of the substrate (1) is formed on the main surface or the surface layer portion of the substrate (1), thereby further increasing the first conductivity type layer (1a). The PN parasitic diode formed between the one conductivity type layer (1a) and the first buffer layer (2a) can be used as an IGBT having a low withstand voltage.

  Even in such a configuration, as shown in claim 4, the first buffer layer (2a) and the first conductive layer are located from the position where the concentration of the second conductive type impurity in the first buffer layer (2a) reaches a peak. If the distance from the die layer (1a) to the PN junction is D1 and the depletion layer width at the PN junction at the time of reverse bias is W1, the relationship of W1 ≦ D1 ≦ W1 + 3 μm is established. The same effect as item 2 can be obtained.

  The invention according to claim 5 is characterized in that the first buffer layer (2a) of the second conductivity type is formed on the surface layer portion of the substrate (1) of the first conductivity type.

  Thus, it is possible to form the first buffer layer (2a) described in claim 1 on the surface layer portion of the substrate (1).

  In this case, as shown in claim 6, it is preferable that the first buffer layer (2a) is terminated inside the end surface of the substrate (1). In this way, it is possible to prevent current leakage at the end face of the substrate (1).

  In the invention according to claim 7, in the surface layer portion of the substrate (1), the concentration of the first conductivity type impurity is higher than that of the substrate (1) in a place where the first buffer layer (2a) is not formed. A set first conductivity type layer (1a) is formed.

  Thus, the 1st conductivity type layer (1a) shown in Claim 3 can also be formed in the place where the 1st buffer layer (2a) is not formed among the surface layer parts of a substrate (1).

The concentration of the first conductivity type impurities in the first and second buffer layers (2a, 2b) described above is 1 × 10 ¹⁷ to 1 × 10 ^{17 for} the first buffer layer (2a), for example, as shown in claim 8. 1 × 10 ¹⁹ cm ⁻³ and the second buffer layer (2b) are set to 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ .

  The invention according to claim 9 is characterized in that the buffer layer (2) has a concentration gradient in which the concentration of the second conductivity type impurity continuously decreases from the substrate (1) to the drift layer.

  Thus, even if the buffer layer (2) is formed by providing a concentration gradient in which the concentration of the second conductivity type impurity continuously decreases from the substrate (1) to the drift layer, the same effect as in claim 1 is obtained. be able to.

  In this case, as shown in claim 10, the distance from the position where the concentration of the second conductivity type impurity in the buffer layer (2) peaks to the PN junction between the buffer layer (2) and the substrate (1) is D1. If the concentration of the second conductivity type impurity in the buffer layer (2) is set so that the relationship of W1 ≦ D1 ≦ W1 + 3 μm is established when the depletion layer width at the PN junction during reverse bias is W1, An effect similar to that of the second aspect can be obtained.

  In the invention according to claim 11, the first conductivity type layer (1a) having a higher concentration of the first conductivity type impurities than the substrate (1) is formed on the main surface or surface layer portion of the substrate (1). It is characterized by doing.

  Thus, if the first conductivity type layer (1a) is formed on the main surface or surface layer of the substrate (1), a PN junction diode between the first conductivity type layer (1a) and the buffer layer (2). Therefore, the same effect as that of the third aspect can be obtained.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, a case where the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is lowered to about 20 V (for example, 23 V or less) will be described.

  FIG. 1 shows a cross-sectional configuration of an IGBT to which the first embodiment of the present invention is applied. FIG. 2 is a schematic diagram showing the impurity concentration distribution in the AA cross section in FIG. 1 and the depletion layer width at the time of reverse bias. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings.

  As shown in FIG. 1, the IGBT has one surface of a P + type silicon substrate 1 functioning as a collector layer as a main surface, and an N + type first buffer layer 2a and an N ++ type second buffer layer 2b on the main surface. The semiconductor substrate 4 is formed using the buffer layer 2 and the N− type drift layer 3 formed of

  A P-type base region 5 is formed in the surface layer portion of the drift layer 3, and an N + -type emitter region 6 is terminated in the P-type base region 5 in the surface layer portion of the P-type base region 5. Is formed.

  A portion sandwiched between the drift layer 3 and the emitter region 6 in the surface portion of the P-type base region 5 is defined as a channel region, and a gate electrode 8 is formed on the channel region via a gate insulating film 7. Is formed. The gate electrode 8 is covered with an interlayer insulating film 9.

  A contact hole is formed in the interlayer insulating film 9, and an emitter electrode 10 that is in contact with the emitter region 6 and the base region 5 is formed through the contact hole. A collector electrode 11 is formed on the back side of the silicon substrate 1. As described above, the IGBT of the present embodiment is configured.

  In such a configuration, in the present embodiment, the impurity concentrations C1, C2, and C3 of the first buffer layer 2a, the second buffer layer 2b, and the drift layer 3 are as shown in FIG. The relationship (C1> C2> C3) is established that the drift layer 3 is the highest and the drift layer 3 is the lowest. Further, the thicknesses t1, t2, and t3 of the first buffer layer 2a, the second buffer layer 2b, and the drift layer 3 are such that the first buffer layer 2a is the thinnest and the drift layer 3 is the thickest (t1> t2> t3) holds.

  Here, the first and second buffer layers 2a and 2b are semiconductor layers that exhibit a general buffer function by these two buffer layers. For this reason, even in the second buffer layer 2b having a low N-type impurity concentration among the first and second buffer layers 2a and 2b, the concentration is at least one digit higher than the drift layer 3 (a concentration of 10 times or more). ), Preferably 20 times or more.

For example, for each part of the semiconductor substrate 4, the P-type impurity concentration of the silicon substrate 1 is 1 to 5 × 10 ¹⁸ cm ⁻³ , and the N-type impurity concentration of the first buffer layer 2 a is 1 × 10 ¹⁷ to 1 × 10 ^19. cm ⁻³ , the impurity concentration of the N-type impurity in the second buffer layer 2 b is 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ , and the drift layer 3 is 1 to 5 × 10 ¹⁴ cm ⁻³ .

  Further, with respect to the first buffer layer 2a, as shown in FIG. 2, the concentration of the N-type impurity in the first buffer layer 2a with respect to the width W1 of the depletion layer generated between the collector layer and the buffer layer during reverse biasing. The concentration is set so that the distance D1 from the location where the peak reaches to the collector layer satisfies the relationship of W1 ≦ D1 ≦ W1 + 3 μm.

  Further, the film thicknesses of the first and second buffer layers 2a and 2b are set to such values that a function equivalent to the buffer function in the conventional buffer layer can be obtained by these two buffer layers. For example, when the film thickness of a single-layer buffer layer provided in a conventional IGBT is 15 μm and the sheet resistance value determined from the impurity concentration is 0.05 Ω · cm, the IGBT of this embodiment has the first The thickness of the buffer layer 2a is 5 μm, the sheet resistance value is 0.023 Ω · cm, the thickness of the second buffer layer 2b is 10 μm, and the sheet resistance value is 0.087 Ω · cm.

  The film thickness and sheet resistance value of the first and second buffer layers 2a and 2b can be adjusted as appropriate. For example, for the first buffer layer 2a, the film thickness is 3 to 8 μm and the sheet resistance value is 0. With respect to 02 to 0.03 Ω · cm and the second buffer layer 2b, the film thickness can be set to 5 to 10 μm and the sheet resistance value can be set to 0.05 to 0.2 Ω · cm.

  According to the IGBT having such a configuration, the following effects can be obtained.

  The breakdown voltage of the PN parasitic diode formed between the P + type silicon substrate 1 functioning as a collector layer and the buffer layer 2 is only a part of the buffer layer 2, that is, only in the vicinity of the silicon substrate 1 in the buffer layer 2. is there. For this reason, as in the present embodiment, the vicinity of the silicon substrate 1 is the first buffer layer 2a having a high concentration of N-type impurities, and the other portions are the second buffer layer 2b having a low concentration, thereby providing a concentration difference. .

  Therefore, since the concentration of the N-type impurity can be increased in the vicinity of the silicon substrate 1, it is possible to obtain an IGBT that has a high switching speed and a sufficient L load surge withstand capability. Further, since the concentration of the N-type impurity is not increased in all the buffer layers, the ON voltage does not become too high, and the ON loss can be kept small. As a result, when it is desired to reduce the breakdown voltage of the PN parasitic diode, an IGBT capable of optimally setting the on-loss, switching speed, and surge resistance, which are IGBT characteristics, can be obtained.

  In this embodiment, with respect to the width W1 of the depletion layer generated between the collector layer and the buffer layer during reverse bias, the distance from the location where the concentration of the N-type impurity in the first buffer layer 2a peaks to the collector layer The density is set so that D1 satisfies the relationship of W1 ≦ D1 ≦ W1 + 3 μm.

  This is for controlling the film thickness of the first buffer layer 2a, and by determining the position of the distance D1 from the location where the concentration of the N-type impurity peaks in the first buffer layer 2a to the collector layer. It can suppress that the film thickness of 1 buffer layer 2a becomes unnecessarily thick. As a result, the film thickness of the first buffer layer 2a where the concentration of the N-type impurity is high can be suppressed as much as possible, and the increase in the on-voltage can be reduced.

  Further, in the present embodiment, not only the first buffer layer 2a but also the second buffer layer 2b having a lower N-type impurity concentration than the first buffer layer 2a is provided. For this reason, the total film thickness of the buffer layer can be increased as compared with the case where the buffer layer is configured by only the first buffer layer 2a.

  Thereby, it is possible to prevent the P-type impurities from reaching the drift layer 3 due to the diffusion of the P-type impurities from the P + -type silicon substrate 1. Therefore, it is possible to improve the L load surge resistance.

  Next, the manufacturing method of the IGBT of this embodiment will be described with reference to the manufacturing process diagram of the IGBT shown in FIG.

First, as shown in FIG. 3A, for example, a P + type silicon substrate 1 having an impurity concentration of 1 to 5 × 10 ¹⁸ cm ⁻³ is prepared, and the main surface of the silicon substrate 1 is formed on the main surface of FIG. As shown in b), an N ++ type first buffer layer 2a is formed. At this time, epitaxial growth is performed so that the concentration of the N-type impurity in the first buffer layer 2a is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 3C, an N + type second buffer layer 2b is formed on the surface of the first buffer layer 2a. At this time, the epitaxial growth is performed so that the concentration of the N-type impurity in the second buffer layer 2b is 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ .

Subsequently, as illustrated in FIG. 3D, the N− type drift layer 3 is formed on the surface of the second buffer layer 2 b. At this time, the epitaxial growth is performed so that the concentration of the N-type impurity in the drift layer 3 is 1 to 5 × 10 ¹⁴ cm ⁻³ . Thus, triple epitaxy is performed in which the first buffer layer 2a, the second buffer layer 2b, and the drift layer 3 are continuously formed by epitaxial growth. Since these layers are formed by the same epitaxial growth, the concentration of N-type impurities is adjusted by adjusting the growth conditions using the same epitaxial growth apparatus.

  Thereafter, by performing ion implantation, a P-type base region 5 and an N + -type emitter region 6 are formed, a gate insulating film 7 is formed by gate oxidation, and a doped polysilicon is patterned to form a gate electrode. The IGBT shown in FIG. 1 can be manufactured by performing a well-known IGBT manufacturing process such as forming 8.

(Second Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the case where the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is lowered to about 20 V (for example, 23 V or less) will be described.

  FIG. 4 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 5 is a schematic diagram showing an impurity concentration distribution in the BB cross section of FIG. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings. However, since the basic structure of the IGBT in the present embodiment is the same as that in the first embodiment, only different portions will be described.

  In the present embodiment, the concentration distribution is not shown in the depth direction as shown in FIGS. 4 and 5 instead of the buffer layer having the two-layer structure of the first and second buffer layers 2a and 2b as in the first embodiment. The buffer layer is formed such that the concentration of the N-type impurity continuously decreases as the depth becomes shallower (closer to the drift layer 3). Other parts are the same as those in the first embodiment.

  This buffer layer is basically configured so that the concentration of N-type impurities decreases in order from the P + type silicon substrate 1 side to the N− type drift layer 3, but the P + type silicon substrate 1. The N-type impurity concentration is lower than the position away from the boundary portion. That is, the N-type impurity concentration peaks at a position slightly away from the boundary with the P + type silicon substrate 1 in the buffer layer. The concentration is set such that the distance D1 from the peak location to the collector layer satisfies the relationship of W1 ≦ D1 ≦ W1 + 3 μm with respect to the width W1 of the depletion layer generated between the collector layer and the buffer layer at the time of reverse bias. It has been done.

  Even with the buffer layer having such a configuration, the same effects as those of the first embodiment can be obtained. The IGBT manufacturing method of the present embodiment is the same as that of the first embodiment except that the amount of N-type impurities to be introduced is gradually reduced in the epitaxial growth when forming the buffer layer.

(Third embodiment)
A third embodiment of the present invention will be described. In this embodiment, the case where the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is lowered to about 20 V (for example, 23 V or less) will be described.

  FIG. 6 is a diagram showing a cross-sectional configuration of the IGBT in this embodiment, and FIG. 7 is a schematic diagram showing the impurity concentration distribution in the CC cross section of FIG. 6 and the depletion layer width during reverse bias. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings. However, since the basic structure of the IGBT in the present embodiment is the same as that in the first embodiment, only different portions will be described.

  In this embodiment, the buffer layer is not devised as in the first and second embodiments, but as shown in FIGS. 6 and 7, the surface of the P + type silicon substrate 1, that is, the silicon substrate 1 and A P ++ type layer 1a having a P type impurity concentration higher than that of the silicon substrate 1 is arranged between the buffer layer and the buffer layer. Other parts are the same as those in the first and second embodiments.

For example, the P ++ type layer 1a has a P-type impurity concentration of about 1 to 9 × 10 ¹⁹ cm ⁻³ . When the distance from the position where the P-type impurity concentration reaches the peak in the P ++ type layer 1a to the PN junction by the P ++ type layer 1a and the buffer layer is Dp, it is generated between the P ++ type layer 1a and the buffer layer at the time of reverse bias. The concentration is set so that the relationship of Wp ≦ D1 ≦ W1 + 3 μm is satisfied with respect to the width Wp of the depletion layer.

  According to such a configuration, the P ++ type layer 1a can reduce the breakdown voltage of the PN parasitic diode formed between the P ++ type layer 1a and the buffer layer at the time of reverse bias. For this reason, an increase in on-voltage can be suppressed, and the same effect as in the first embodiment can be obtained.

  Next, the manufacturing method of the IGBT of this embodiment will be described with reference to the manufacturing process diagram of the IGBT shown in FIG.

First, as shown in FIG. 8A, for example, a P + type silicon substrate 1 having an impurity concentration of 1 to 5 × 10 ¹⁸ cm ⁻³ is prepared, and the main surface of the silicon substrate 1 is formed on the main surface of FIG. As shown in b), a P ++ type layer 1a is formed. At this time, epitaxial growth is performed so that the concentration of the P-type impurity in the P ++ type layer 1a is 1 to 9 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 8C, an N + type buffer layer is formed on the surface of the P ++ type layer 1a. At this time, epitaxial growth is performed so that the concentration of the N-type impurity in the buffer layer is 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ .

  Thereafter, in FIG. 8D and FIG. 8E, the same processes as those shown in FIG. 3D and FIG. 3E in the first embodiment are performed. Thereby, the IGBT of this embodiment can be manufactured.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. This embodiment is a combination of the first embodiment and the third embodiment, and is applied when the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is lowered to 10 V or less, for example.

  FIG. 9 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 10 is a schematic diagram showing an impurity concentration distribution in the DD cross section of FIG. As shown in this figure, the IGBT of the present embodiment is provided with the first and second buffer layers 2a and 2b as described in the first embodiment, and the P + type silicon substrate 1 and the first buffer layer. The P ++ type layer 1a shown in the third embodiment is provided between the buffer layer 2a and the buffer layer 2a. Regarding the concentration distribution of the first buffer layer 2a and the concentration distribution of the P ++ type layer 1a, the position where the impurity concentration reaches a peak is determined by the distance from the PN junction formed by the first buffer layer 2a and the P ++ type layer 1a. However, the distance relationship is the same as in the first and third embodiments. Other portions are the same as those in the first and third embodiments.

  Thus, it can also combine with 1st Embodiment and 3rd Embodiment. According to such a configuration, it can be used as an IGBT having a low breakdown voltage of the PN parasitic diode formed between the first buffer layer 2a and the P ++ type layer 1a.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. This embodiment is a combination of the second embodiment and the third embodiment, and is applied when the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is lowered to, for example, 10 V or less.

  FIG. 11 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 12 is a schematic diagram showing an impurity concentration distribution in the EE cross section of FIG. As shown in this figure, the IGBT of this embodiment is provided with a buffer layer having a gradient in concentration distribution as described in the second embodiment, and a P + type silicon substrate 1 and a buffer layer. And the P ++ type layer 1a shown in the third embodiment. Regarding the concentration distribution of the buffer layer and the concentration distribution of the P ++ type layer 1a, the position where the impurity concentration peaks is determined by the distance from the PN junction formed by the buffer layer and the P ++ type layer 1a. Although different from the first and third embodiments, the distance relationship is the same as that of the second and third embodiments. Other portions are the same as those in the second and third embodiments.

  Thus, it can also combine with 2nd Embodiment and 3rd Embodiment. According to such a configuration, it can be used as an IGBT having a smaller breakdown voltage of the PN parasitic diode formed between the buffer layer and the P ++ type layer 1a.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. In the present embodiment, the first buffer layer 2 a shown in the first embodiment is partially formed on a P + type silicon substrate 1. Therefore, this embodiment is also applied when the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is lowered to about 20 V (for example, 23 V or less).

  FIG. 13 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 14 is a schematic diagram showing the impurity concentration distribution in the FF cross section of FIG. 13 and the depletion layer width at the time of reverse bias. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings. However, since the basic structure of the IGBT in the present embodiment is the same as that in the first embodiment, only different portions will be described.

  As can be seen from FIG. 13, in this embodiment, a plurality of first buffer layers 2 a are arranged on the surface layer portion of the P + type silicon substrate 1 so as to be separated from each other. The first buffer layer 2a is configured not to be formed in an end face of the semiconductor substrate 4, that is, a dicing region that is a portion to be diced when the IGBT is divided into chips.

  According to such a configuration, basically the same effect as that of the first embodiment can be obtained, and the first buffer layer 2a is not formed in the dicing region. There is also an effect that current leakage can be prevented. That is, since a defective layer by dicing is formed on the end face of the semiconductor substrate 4, it is possible to increase the current resistance by preventing the breakdown voltage of the PN parasitic diode from being reduced only in this portion.

  In the present embodiment, the first buffer layer 2a is disposed at a plurality of locations apart from each other. With such a configuration, it is possible to adjust the ON voltage and the switching speed by adjusting the distance between the plurality of first buffer layers 2a. Therefore, it is possible to perform an IGBT design according to more demands.

  Next, a method for manufacturing the IGBT of the present embodiment will be described with reference to a manufacturing process diagram of the IGBT shown in FIG.

First, as shown in FIG. 15A, for example, a P + type silicon substrate 1 having an impurity concentration of 1 to 5 × 10 ¹⁸ cm ⁻³ is prepared. As shown in b), the first buffer layer 2a is formed on the surface layer portion of the silicon substrate 1 by performing ion implantation, vapor phase diffusion, or the like. At this time, the N-type impurity concentration of the first buffer layer 2a is adjusted to 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 15C, an N + type second buffer layer 2b is formed on the surface of the silicon substrate 1 including the surface of the first buffer layer 2a. At this time, epitaxial growth is performed so that the concentration of the N-type impurity in the buffer layer is 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ .

  Thereafter, in FIGS. 15D and 15E, the same processes as those shown in FIGS. 3D and 3E in the first embodiment are performed. Thereby, the IGBT of this embodiment can be manufactured.

(Seventh embodiment)
A seventh embodiment of the present invention will be described. FIG. 16 is a cross-sectional view of an IGBT according to the seventh embodiment of the present invention. In the present embodiment, the P ++ type layer 1a shown in the third embodiment is formed on the surface layer portion of the P ++ type silicon substrate 1 as in the sixth embodiment. Thus, even if the P ++ type layer 1a is formed on the surface layer portion of the silicon substrate 1, the same effect as that of the third embodiment can be obtained, and the end face of the semiconductor substrate 4 can be obtained similarly to the sixth embodiment. An effect that current leakage can be prevented can also be obtained.

  As for the method of manufacturing the IGBT of this embodiment, the impurity in the step of forming the first buffer layer 2a shown in the sixth embodiment (step of FIG. 15B) is simply changed from N-type to P-type. Since the others are the same, the description is omitted.

(Eighth embodiment)
An eighth embodiment of the present invention will be described. FIG. 17 is a cross-sectional view of an IGBT according to the eighth embodiment of the present invention. In the present embodiment, the first buffer layer 2a shown in the sixth embodiment and the P ++ type layer 1a shown in the seventh embodiment are both partially formed on the surface layer portion of the P + type silicon substrate 1. With such a configuration, it is possible to obtain the effect of the seventh embodiment in addition to the effect of the sixth embodiment, and it can be used as an IGBT having a smaller breakdown voltage of the PN parasitic diode.

(Ninth embodiment)
A ninth embodiment of the present invention will be described. In this embodiment, unlike the first to eighth embodiments, a case will be described in which the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is increased to 40 V or higher.

  FIG. 18 shows a cross-sectional configuration of an IGBT to which the ninth embodiment of the present invention is applied. FIG. 19 is a schematic diagram showing the impurity concentration distribution in the GG section in FIG. 18 and the depletion layer width at the time of reverse bias. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings.

  As shown in FIG. 18, in the present embodiment as well, the first and second buffer layers 2a and 2b are formed on the surface of a P + type silicon substrate 1 as in the first embodiment. However, in the present embodiment, the concentration is set such that the first buffer layer 2a has a lower N-type impurity concentration than the second buffer layer 2b.

  Thus, by setting the concentration of the N-type impurity of the first buffer layer 2a low at the boundary position of the PN junction portion constituting the PN parasitic diode, the on-voltage can be lowered, and the withstand voltage of the PN parasitic diode can be reduced. Can be set high. As a result, it can be used for an IGBT having a high breakdown voltage of a PN parasitic diode.

  The IGBT manufacturing method of this embodiment is the same as that of the first embodiment except that the concentrations of the first and second buffer layers 2a and 2b are different from those of the first embodiment, and a description thereof will be omitted.

(10th Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the case where the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is increased to 40 V or more will be described.

  20 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 21 is a schematic diagram showing an impurity concentration distribution in the HH cross section of FIG. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings. However, since the basic structure of the IGBT in the present embodiment is the same as that in the ninth embodiment, only different portions will be described.

  In the present embodiment, the concentration distribution is not shown in the depth direction as shown in FIGS. 20 and 21 instead of the buffer layer having the two-layer structure of the first and second buffer layers 2a and 2b as in the ninth embodiment. The buffer layer is such that the concentration of N-type impurities increases continuously as the depth becomes shallower (closer to the drift layer 3). Other parts are the same as those in the ninth embodiment. In other words, the density distribution is set to be opposite to that of the second embodiment.

  Even with the buffer layer having such a configuration, the same effects as those of the ninth embodiment can be obtained. The IGBT manufacturing method of this embodiment is the same as that of the second embodiment except that the concentration of the buffer layer is different from that of the second embodiment.

(Eleventh embodiment)
An eleventh embodiment of the present invention will be described. In this embodiment, the case where the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is increased to 40 V or more will be described.

  FIG. 22 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 23 is a schematic diagram showing an impurity concentration distribution in the II cross section of FIG. Hereinafter, the configuration of the IGBT in the present embodiment will be described with reference to these drawings. However, since the basic structure of the IGBT in the present embodiment is the same as that in the ninth embodiment, only different portions will be described.

In this embodiment, the buffer layer is not devised as in the ninth and tenth embodiments, but as shown in FIGS. 22 and 23, the surface of the P + type silicon substrate 1, that is, the silicon substrate 1 and A P− type layer having a P type impurity concentration lower than that of the silicon substrate 1 is disposed between the buffer layer and the buffer layer. For example, the P− type layer has a P type impurity concentration of about 0.1 to 5 × 10 ¹⁷ cm ⁻³ . Other parts are the same as those in the ninth and tenth embodiments.

  By using the P-type layer having such a configuration, the breakdown voltage of the PN parasitic diode formed between the P-type layer and the buffer layer at the time of reverse bias can be increased. For this reason, it is possible to prevent the on-voltage from increasing, and it is possible to obtain the same effect as in the ninth and tenth embodiments.

  The IGBT manufacturing method is the same as that of the P− type layer except that the concentration of the P− type layer is different from that of the P ++ type layer 1a shown in the third embodiment, and thus the description thereof is omitted here.

(Twelfth embodiment)
A twelfth embodiment of the present invention will be described. This embodiment is a combination of the ninth embodiment and the eleventh embodiment, and is applied when the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer during reverse bias is very high.

  FIG. 24 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 25 is a schematic diagram showing an impurity concentration distribution in the JJ cross section of FIG. As shown in this figure, the IGBT of this embodiment is provided with the first and second buffer layers 2a and 2b as described in the ninth embodiment, and the P + type silicon substrate 1 and the first buffer layer. The P-type layer shown in the eleventh embodiment is provided between the buffer layer 2a and the buffer layer 2a. Other portions are the same as those in the ninth and eleventh embodiments.

  Thus, the ninth embodiment and the eleventh embodiment can be combined. According to such a configuration, it can be used as an IGBT having a higher breakdown voltage of the PN parasitic diode formed between the first buffer layer 2a and the P− type layer.

(13th Embodiment)
A thirteenth embodiment of the present invention will be described. The present embodiment is a combination of the tenth embodiment and the eleventh embodiment, and is applied when the breakdown voltage of the PN parasitic diode between the collector layer and the buffer layer at the time of reverse bias is increased.

  FIG. 26 is a diagram showing a cross-sectional configuration of the IGBT in the present embodiment, and FIG. 27 is a schematic diagram showing an impurity concentration distribution in the KK cross section of FIG. As shown in this figure, the IGBT of this embodiment is provided with a buffer layer having a gradient in concentration distribution as described in the tenth embodiment, and a P + type silicon substrate 1 and a buffer layer. And a P-type layer shown in the eleventh embodiment. Other parts are the same as those in the tenth and eleventh embodiments.

  As described above, the tenth embodiment and the eleventh embodiment can be combined. According to such a configuration, it can be used as an IGBT having a higher breakdown voltage of a PN parasitic diode formed between the buffer layer and the P− type layer.

(Other embodiments)
The impurity concentration of each part shown in the above embodiments is merely an example, and does not exclude application of impurity concentration not shown here.

  In each of the above embodiments, an N-channel type IGBT has been described as an example. However, the present invention can also be applied to a P-channel IGBT in which the conductivity type of each part is reversed.

It is the figure which showed the cross-sectional structure of IGBT with which 1st Embodiment of this invention was applied. FIG. 2 is a schematic diagram illustrating an impurity concentration distribution in a section AA in FIG. 1 and a depletion layer width at the time of reverse bias. It is a manufacturing-process figure of IGBT shown in FIG. It is the figure which showed the cross-sectional structure of IGBT with which 2nd Embodiment of this invention was applied. FIG. 5 is a schematic diagram showing an impurity concentration distribution in a BB cross section in FIG. 4 and a depletion layer width at the time of reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 3rd Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the CC cross section in FIG. 6, and the depletion layer width at the time of reverse bias. FIG. 7 is a manufacturing process diagram of the IGBT shown in FIG. 6. It is the figure which showed the cross-sectional structure of IGBT with which 4th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the DD cross section in FIG. 9, and the depletion layer width at the time of reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 5th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the EE cross section in FIG. 11, and the depletion layer width at the time of reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 6th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the FF cross section in FIG. 13, and the depletion layer width | variety at the time of a reverse bias. FIG. 14 is a manufacturing process diagram of the IGBT shown in FIG. 13. It is the figure which showed the cross-sectional structure of IGBT with which 7th Embodiment of this invention was applied. It is the figure which showed the cross-sectional structure of IGBT with which 8th Embodiment of this invention was applied. It is the figure which showed the cross-sectional structure of IGBT with which 9th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the GG cross section in FIG. 18, and the depletion layer width | variety at the time of a reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 10th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the HH cross section in FIG. 20, and the depletion layer width | variety at the time of a reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 10th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the II cross section in FIG. 22, and the depletion layer width | variety at the time of a reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 11th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the JJ cross section in FIG. 24, and the depletion layer width | variety at the time of reverse bias. It is the figure which showed the cross-sectional structure of IGBT with which 11th Embodiment of this invention was applied. It is the schematic diagram which showed the impurity concentration distribution in the KK cross section in FIG. 22, and the depletion layer width at the time of reverse bias. It is the figure which showed the cross-sectional structure of the conventional IGBT.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 1a ... P ++ type layer, 2 ... Buffer layer, 2a ... 1st buffer layer, 2b ... 2nd buffer layer, 3 ... Drift layer, 4 ... Semiconductor substrate, 5 ... Base region, 6 ... Emitter region, 7 ... Gate insulating film, 8 ... Gate electrode, 9 ... Interlayer insulating film, 10 ... Emitter electrode, 11 ... Collector electrode.

Claims (11)

A first conductivity type substrate (1);
A first buffer layer (2a) of the second conductivity type formed on the main surface side of the substrate (1) of the first conductivity type;
A second conductivity type second buffer layer (2b) formed on a surface of the first buffer layer (2a) and having a lower impurity concentration than the first buffer layer (2a);
A second conductivity type drift layer (3) formed on the second buffer layer (2b) and having a lower impurity concentration than the second buffer layer (2b);
A first conductivity type base region (5) formed in a surface layer portion of the second conductivity type drift layer (3);
A second conductivity type emitter region (6) formed to terminate in the base region (5) at a surface layer portion of the base region (5);
A gate insulating film (7) formed on the surface of the channel region with a channel region between the emitter region (6) and the drift region (3),
A gate electrode (8) formed on the surface of the gate insulating film (7);
An emitter electrode (10) configured to be electrically connected to the emitter region (6) and the base region (5);
And an collector electrode (11) formed on the back surface of the substrate (1). The distance from the position where the concentration of the second conductivity type impurity in the first buffer layer (2a) reaches the peak to the PN junction between the first buffer layer (2a) and the substrate (1) is D1, and the reverse bias is applied. The concentration of the second conductivity type impurity in the first buffer layer (2a) is set so that the relationship of W1 ≦ D1 ≦ W1 + 3 μm is established when the width of the depletion layer at the PN junction is W1. The IGBT according to claim 1. A first conductivity type layer (1a) in which the concentration of the first conductivity type impurities is higher than that of the substrate (1) is formed on the main surface or the surface layer portion of the substrate (1). The IGBT according to claim 1, wherein the first buffer layer (2a) is formed on the layer (1a). The distance from the position where the concentration of the second conductivity type impurity in the first buffer layer (2a) reaches a peak to the PN junction between the first buffer layer (2a) and the first conductivity type layer (1a) is D1. When the depletion layer width at the PN junction at the time of reverse bias is W1, the concentration of the second conductivity type impurity in the first buffer layer (2a) is such that the relationship of W1 ≦ D1 ≦ W1 + 3 μm is established. The IGBT according to claim 3, wherein the IGBT is set. A first conductivity type substrate (1);
A second conductivity type first buffer layer (2a) formed on a surface layer portion of the first conductivity type substrate (1);
A second conductivity type second buffer layer (2b) formed on a surface of the first buffer layer (2a) and having a lower impurity concentration than the first buffer layer (2a);
A second conductivity type drift layer (3) formed on the second buffer layer (2b) and having a lower impurity concentration than the second buffer layer (2b);
A first conductivity type base region (5) formed in a surface layer portion of the second conductivity type drift layer (3);
A second conductivity type emitter region (6) formed to terminate in the base region (5) at a surface layer portion of the base region (5);
A gate insulating film (7) formed on the surface of the channel region with a channel region between the emitter region (6) and the drift region (3),
A gate electrode (8) formed on the surface of the gate insulating film (7);
An emitter electrode (10) configured to be electrically connected to the emitter region (6) and the base region (5);
And an collector electrode (11) formed on the back surface of the substrate (1). The IGBT according to claim 5, wherein the first buffer layer (2a) is configured to terminate inside an end face of the substrate (1). In the surface layer portion of the substrate (1), the first conductivity type in which the concentration of the first conductivity type impurity is set higher than that of the substrate (1) in a place where the first buffer layer (2a) is not formed. The IGBT according to claim 5 or 6, wherein a mold layer (1a) is formed. The concentration of the first conductivity type impurity in the first buffer layer (2a) is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ , and the concentration of the first conductivity type impurity in the second buffer layer (2b) is 1 × 10. The IGBT according to claim 1, wherein the IGBT is ^{16 to} 5 × 10 ¹⁷ cm ⁻³ . A first conductivity type substrate (1);
A second conductivity type buffer layer (2) formed on the main surface of the first conductivity type substrate (1);
A second conductivity type drift layer (3) formed on the buffer layer (2) and having a lower impurity concentration than the buffer layer (2);
A first conductivity type base region (5) formed in a surface layer portion of the second conductivity type drift layer (3);
A second conductivity type emitter region (6) formed to terminate in the base region (5) at a surface layer portion of the base region (5);
A gate insulating film (7) formed on the surface of the channel region with a channel region between the emitter region (6) and the drift region (3),
A gate electrode (8) formed on the surface of the gate insulating film (7);
An emitter electrode (10) configured to be electrically connected to the emitter region (6) and the base region (5);
A collector electrode (11) formed on the back surface of the substrate (1),
The IGBT according to claim 1, wherein the buffer layer (2) has a concentration gradient in which the concentration of the second conductivity type impurity continuously decreases from the substrate (1) to the drift layer. The distance from the position where the concentration of the second conductivity type impurity in the buffer layer (2) reaches a peak to the PN junction between the buffer layer (2) and the substrate (1) is D1, and the PN junction at the time of reverse bias The concentration of the second conductivity type impurity in the buffer layer (2) is set so that the relationship of W1 ≦ D1 ≦ W1 + 3 μm is established when the width of the depletion layer at is W1. Item 10. The IGBT according to Item 9. A first conductivity type substrate (1);
A first conductivity type layer (1a) formed on the main surface or surface layer of the substrate (1) and having a higher concentration of first conductivity type impurities than the substrate (1);
A second conductivity type buffer layer (2) formed on the surface of the first conductivity type layer (1a);
A second conductivity type drift layer (3) formed on the buffer layer (2) and having a lower impurity concentration than the buffer layer (2);
A first conductivity type base region (5) formed in a surface layer portion of the second conductivity type drift layer (3);
A second conductivity type emitter region (6) formed to terminate in the base region (5) at a surface layer portion of the base region (5);
A gate insulating film (7) formed on the surface of the channel region with a channel region between the emitter region (6) and the drift region (3),
A gate electrode (8) formed on the surface of the gate insulating film (7);
An emitter electrode (10) configured to be electrically connected to the emitter region (6) and the base region (5);
And an collector electrode (11) formed on the back surface of the substrate (1).

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