CN117747648A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- CN117747648A CN117747648A CN202311556157.8A CN202311556157A CN117747648A CN 117747648 A CN117747648 A CN 117747648A CN 202311556157 A CN202311556157 A CN 202311556157A CN 117747648 A CN117747648 A CN 117747648A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000011084 recovery Methods 0.000 claims abstract description 33
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 14
- 239000002184 metal Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000002441 reversible effect Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 230000002452 interceptive effect Effects 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses a semiconductor device, which comprises: a base; a drift layer; a first trench, the spacing trench including two sub-trench portions arranged at intervals in a first direction, the sub-trench portions including a plurality of gate trench groups and a plurality of dummy gate trenches; the second grooves are arranged between the two sub-groove parts at intervals in the first direction; one of the two first connecting grooves connects one end of the plurality of second grooves in the first direction, the other end of the plurality of second grooves in the first direction, and the first connecting groove is connected with one end of the dummy gate groove adjacent to the second grooves; and the second connecting groove is used for connecting one end, adjacent to the second groove, of the gate grooves in the gate groove group. Therefore, the method can prevent the mutual interference of the insulated gate bipolar transistor region and the fast recovery diode region in the process, ensure the respective performances of the two regions and improve the current passing capability of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device.
Background
RC-IGBT (reverse conducting type insulated gate bipolar transistor reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor) and FRD (fast recovery diode Fast Recovery Diode) on the same chip, so that the IGBT has the characteristics of forward conduction and reverse conduction, and has the advantages of small size, high power density, low cost, high reliability and the like.
In the related art, in the structure of the RC-IGBT, the FRD region is often formed by cutting off the trench to separate the IGBT region from the FRD region, but this may not only deteriorate the current-carrying capability of the device, but also the FRD region is easily affected by the process such as the IGBT region injection, thereby deteriorating the performance of the FRD region and thus the RC-IGBT.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, an object of the present invention is to provide a semiconductor device which is better in operation performance and reliability.
The semiconductor device according to an embodiment of the present invention includes: a base body having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type, the drift layer being provided between a first main surface and a second main surface; a plurality of first trenches extending from the first main surface toward the second main surface and reaching into the drift layer, the plurality of first trenches extending in a first direction, the plurality of first trenches being arranged at intervals in a second direction, portions of the plurality of first trenches being interval trenches; the spacer trench comprises two sub-trench portions which are arranged at intervals in a first direction, the sub-trench portions comprise a plurality of gate trench groups and a plurality of dummy gate trenches, the gate trench groups are arranged at intervals in a second direction, at least one dummy gate trench is arranged between two adjacent gate trench groups, the gate trench groups comprise at least two gate trenches arranged at intervals in the second direction, the gate trenches are electrically connected with a gate of the semiconductor device, and the dummy gate trenches are electrically connected with an emitter of the semiconductor device; a second trench extending from the first main surface toward the second main surface and into the drift layer, the second trench extending in a first direction, the second trench being provided in plurality and being spaced apart from each other in a second direction, the second trench being provided between the two sub-trench portions at a first direction interval; a first connection trench extending from the first main surface toward the second main surface and reaching into the drift layer, the first connection trench extending in a second direction, two first connection trenches, one of the two first connection trenches connecting one end of the plurality of second trenches in the first direction and the other connecting the other end of the plurality of second trenches in the first direction, and the first connection trench being connected with one end of the dummy gate trench adjacent to the second trench; and a second connection trench extending from the first main surface toward the second main surface and into the drift layer, the second connection trench extending in a second direction, the second connection trench connecting one end of the gate trenches in the gate trench group adjacent to the second trench.
Therefore, one of the two first connecting grooves is connected with one end of the plurality of second grooves in the first direction, the other one is connected with the other end of the plurality of second grooves in the first direction, the first connecting groove is connected with one end of the dummy gate groove adjacent to the second grooves, and the second connecting groove is connected with one end of the gate groove in the gate groove group adjacent to the second grooves, so that the mutual interference of an insulated gate bipolar transistor area and a fast recovery diode area in the manufacturing process can be prevented, the respective performances of the two areas are ensured, the through-flow capacity of the semiconductor device can be improved, and the working performance of the semiconductor device can be improved.
In some examples of the present invention, an end of the dummy gate trench adjacent to the second trench protrudes from an end of the gate trench adjacent to the second trench, and the end of the dummy gate trench adjacent to the second trench extends toward the second trench and is connected to the first connection trench.
In some examples of the present invention, the plurality of second trenches includes a plurality of first sub-trenches, and the plurality of first sub-trenches and the plurality of dummy gate trenches are in one-to-one correspondence and are connected to each other.
In some examples of the present invention, the plurality of second trenches further includes a plurality of second sub-trenches, and the plurality of second sub-trenches and the plurality of gate trenches are disposed in one-to-one correspondence in the first direction and spaced apart from each other.
In some examples of the present invention, two sides of the second direction of the plurality of second trenches are a first boundary trench and a second boundary trench, and an area surrounded by the first boundary trench, the second boundary trench and the two first connection trenches is a fast recovery diode area.
In some examples of the present invention, the region surrounded by the first boundary trench, the second boundary trench, and the two first connection trenches is an insulated gate bipolar transistor region.
In some examples of the invention, the first connection groove and the second connection groove are spaced apart in a first direction.
In some examples of the present invention, the first connection groove and the second connection groove are spaced apart by a distance D1 in the first direction, two adjacent first grooves are spaced apart by a distance D2 in the second direction, two adjacent second grooves are spaced apart by a distance D3 in the second direction, and D1, D2, and D3 satisfy the relationship: d1 =d2=d3.
In some examples of the invention, D1 satisfies the relationship: d1 is less than or equal to 1 mu m and less than or equal to 2 mu m.
In some examples of the invention, D1 satisfies the relationship: d1 is less than or equal to 1.5 mu m and less than or equal to 2 mu m.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention along A-A;
fig. 4 is a partial schematic view of a semiconductor device according to another embodiment of the present invention;
fig. 5 is a partial schematic view of a semiconductor device according to another embodiment of the present invention;
fig. 6 is a cross-sectional view of structure 1 according to an embodiment of the invention;
FIG. 7 is a cross-sectional view of structure 2 according to an embodiment of the invention;
FIG. 8 is a cross-sectional view of structure 3 according to an embodiment of the invention;
FIG. 9 is a cross-sectional view of structure 4 according to an embodiment of the invention;
fig. 10 is a cross-sectional view of structure 5 according to an embodiment of the invention.
Reference numerals:
100. a semiconductor device; 101. an insulated gate bipolar transistor region; 102. a fast recovery diode region;
10. a drift layer; 11. a well region; 12. a second emitter layer; 13. a dielectric layer; 14. an emitter metal layer; 15. a field stop layer; 16. a collector layer; 17. a first emitter layer; 18. a collector metal layer;
20. a first trench; 21. spacing the grooves; 221. a sub-groove portion; 222. a gate trench set; 2221. a gate trench; 223. a dummy gate trench;
30. a second trench; 31. a second sub-trench; 32. a first sub-trench; 33. a first boundary trench; 34. a second boundary trench;
40. a first connection groove; 50. A second connection trench;
70. oxidizing the insulating layer; 71. Polycrystalline silicon;
80. a base; 81. a first major face; 82. a second major face.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
A semiconductor device 100 according to an embodiment of the present invention is described below with reference to fig. 1 to 10. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P denote conductivity types of semiconductors, and in the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type.
As shown in connection with fig. 1 to 7, a semiconductor device 100 according to the present invention may mainly include: a substrate 80, a drift layer 10 of a first conductivity type, a first trench 20 and a second trench 30.
Specifically, the drift layer 10 of the first conductivity type is disposed in the body 80 and between the first main surface 81 and the second main surface 82, the body 80 is further provided with the well region 11 of the second conductivity type, the well region 11 is disposed at a side of the drift layer 10 close to the first main surface 81, the well region 11 is further provided with the second emitter layer 12 of the first conductivity type, the body 80 is further provided with the field stop layer 15 of the first conductivity type, the field stop layer 15 is disposed at a side of the drift layer 10 close to the second main surface 82, and a side of the field stop layer 15 close to the second main surface 82 is provided with the collector layer 16 of the second conductivity type and the first emitter layer 17 of the first conductivity type. The dielectric layer 13 is provided on the first main surface 81, the emitter metal layer 14 is provided on the side of the dielectric layer 13 facing away from the first main surface 81, and the collector metal layer 18 is provided on the second main surface 82 of the substrate 80, so that the basic structure of the semiconductor device 100 can be configured.
The semiconductor device 100 may include an active region and a termination region disposed at the periphery of the active region, where a region corresponding to the collector layer 16 is an insulated gate bipolar transistor region 101, and a region corresponding to the first emitter layer 17 is a fast recovery diode region 102, that is: the active region of the semiconductor device 100 may include an insulated gate bipolar transistor region 101 and a fast recovery diode region 102, the emitter metal layer 14 may serve as an emitter lead-out terminal of the insulated gate bipolar transistor region 101, an anode lead-out terminal of the fast recovery diode region 102, and the collector metal layer 18 may serve as a collector lead-out terminal of the insulated gate bipolar transistor region 101, and a cathode lead-out terminal of the fast recovery diode region 102, so that the insulated gate bipolar transistor region 101 may realize forward conduction of the semiconductor device 100, and the fast recovery diode region 102 may realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 may have characteristics of both forward conduction and reverse conduction.
Further, the first trenches 20 extend from the first main surface 81 toward the second main surface 82 and reach into the drift layer 10, and the first trenches 20 extend in the first direction, and by arranging the first trenches 20 in plurality, the plurality of first trenches 20 are arranged at intervals in the second direction, wherein a portion of the plurality of first trenches 20 is the interval trench 21, the interval trench 21 may mainly include two sub-trench portions 221 arranged at intervals in the first direction, the sub-trench portions 221 may include a plurality of gate trench groups 222 and a plurality of dummy gate trenches 223, the plurality of gate trench groups 222 are arranged at intervals in the second direction, at least one dummy gate trench 223 is arranged between adjacent two gate trench groups 222, and the gate trench groups 222 include at least two gate trenches 2221 arranged at intervals in the second direction.
Specifically, the gate trench 2221 and the dummy gate trench 223 are each provided with an oxide insulating layer 70, and polysilicon 71 is deposited. The second emitter layer 12 is disposed on two sides of the gate trench 2221 in the second direction, the gate trench 2221 has a conductive channel and a through-current capability, and can be electrically connected with a gate, so that the insulated gate bipolar transistor region 101 and even the semiconductor device 100 can work normally, the second emitter layer 12 is not disposed on two sides of the dummy gate trench 223 in the second direction, and the dummy gate trench 223 can be electrically connected with an emitter, so that the miller capacitance is reduced and the current density is reduced on the premise of ensuring the voltage-withstanding capability of the semiconductor device 100, and the short-circuit capability of the semiconductor device 100 can be improved.
Further, the second trenches 30 extend from the first main surface 81 toward the second main surface 82 and reach into the drift layer 10, the second trenches 30 extend in the first direction, and by arranging the second trenches 30 in a plurality of first spaced trenches 21 in one-to-one correspondence, not only the junction depths and the doping concentrations of the well regions 11 of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 can be made the same, the same withstand voltage can be ensured in the two regions, but also the process steps of the semiconductor device 100 can be simplified, and by arranging the second trenches 30 between the two sub-trench portions 221 at intervals in the first direction, the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 can be separated, so that the respective performances of the two regions can be ensured, and the working performance of the semiconductor device 100 can be ensured.
As shown in connection with fig. 1-3, the semiconductor device 100 may further include: the first connection trenches 40 extend from the first main surface 81 toward the second main surface 82 and into the drift layer 10, the first connection trenches 40 extend in the second direction, the first connection trenches 40 are provided in two, one of the two first connection trenches 40 connects one end of the plurality of second trenches 30 in the first direction, the other connects the other end of the plurality of second trenches 30 in the first direction, and the first connection trenches 40 are connected with one end of the dummy gate trench 223 adjacent to the second trenches 30.
Specifically, one ends of the plurality of second trenches 30 are flush with each other, the other ends of the plurality of second trenches 30 are flush with each other, by providing the first connection trenches 40 such that the first connection trenches 40 extend from the first main face 81 toward the second main face 82 and reach into the drift layer 10, the first connection trenches 40 extend in the second direction, and the first connection trenches 40 are provided in two, so that one of the two first connection trenches 40 can extend in the second direction while one ends of the plurality of second trenches 30 are communicated, and the other of the two first connection trenches 40 can extend in the second direction while the other ends of the plurality of second trenches 30 are communicated.
On the one hand, two first connecting grooves 40 may be made to enclose the plurality of second grooves 30, namely: the two first connection trenches 40 can separate the igbt region 101 and the fast recovery diode region 102, so as to prevent the igbt region 101 and the fast recovery diode region 102 from interfering with each other in the process, and ensure the respective performances of the two regions, and on the other hand, the two first connection trenches 40 can increase the current capacity of the fast recovery diode region 102, so that the operation performance of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved.
Further, considering that the dummy gate trench 223 and the second trench 30 are equipotential, the dummy gate trench 223 and the second trench 30 are both connected to the emitter, by connecting one end of the dummy gate trench 223 adjacent to the second trench 30 to the first connection trench 40, not only connection between the dummy gate trench 223 and the second trench 30 can be achieved through the first connection trench 40, connection of the dummy gate trench 223 and the second trench 30 to the emitter, respectively, can be facilitated, a production process of the semiconductor device 100 can be simplified, and a current passing capability of the semiconductor device 100 can be further improved.
As shown in connection with fig. 1-3, the semiconductor device 100 may further include: and a second connection trench 50 extending from the first main surface 81 toward the second main surface 82 and into the drift layer 10, the second connection trench 50 extending in the second direction, the second connection trench 50 connecting one end of the gate trench 2221 in the gate trench group 222 adjacent to the second trench 30.
Specifically, the gate trenches 2221 in each gate trench group 222 are flush adjacent to one end of the second trench 30, and by providing the second connection trench 50, when the second connection trench 50 is extended in the second direction, the gate trenches 2221 in the gate trench group 222 can be connected adjacent to one end of the second trench 30, so that not only the current-carrying capability of the semiconductor device 100 can be improved, but also the gate trenches 2221 in the gate trench group 222 can be enclosed adjacent to one end of the second trench 30, so as to avoid mutual interference between the gate trench group 222 and the second trench 30 in the process, namely: the igbt region 101 and the fast recovery diode region 102 can be prevented from interfering with each other in the process, and the respective performances of the two regions can be ensured.
Thus, by connecting one of the two first connection trenches 40 to one end of the plurality of second trenches 30 in the first direction and the other end of the plurality of second trenches 30 in the first direction, and connecting the first connection trench 40 to one end of the dummy gate trench 223 adjacent to the second trenches 30, and connecting the second connection trench 50 to one end of the gate trench 2221 in the gate trench group 222 adjacent to the second trenches 30, it is possible to not only prevent the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process, ensure the respective performances of the two regions, but also to improve the current passing capability of the semiconductor device 100, and thus to improve the operation performance of the semiconductor device 100.
As shown in fig. 1 to 3, an end of the dummy gate trench 223 adjacent to the second trench 30 protrudes from an end of the gate trench 2221 adjacent to the second trench 30, and the end of the dummy gate trench 223 adjacent to the second trench 30 extends toward the second trench 30 and is connected to the first connection trench 40.
Specifically, the end of the dummy gate trench 223 adjacent to the second trench 30 protrudes from the end of the gate trench 2221 adjacent to the second trench 30, and on the premise that the second connection trench 50 is provided to connect the gate trenches 2221 in each gate trench group 222, the end of the dummy gate trench 223 adjacent to the second trench 30 extends toward the second trench 30, so that the dummy gate trench 223 is connected with the first connection trench 40, which not only facilitates the connection between the dummy gate trench 223 and the corresponding second trench 30 and the emitter, thereby simplifying the manufacturing process of the semiconductor device 100, but also improves the current-through capability of the semiconductor device 100 and improves the working performance of the semiconductor device 100.
As shown in fig. 1 to 3, the plurality of second trenches 30 may include a plurality of first sub-trenches 32, where the plurality of first sub-trenches 32 and the plurality of dummy gate trenches 223 are in one-to-one correspondence and are connected to each other, so that not only can the circuit distribution of the semiconductor device 100 be more uniform, but also the dummy gate trenches 223 and the corresponding first sub-trenches 32 can be conveniently etched synchronously, and the manufacturing process of the semiconductor device 100 can be simplified.
Further, as shown in fig. 1 to 3, the plurality of second trenches 30 may further include a plurality of second sub-trenches 31, where the plurality of second sub-trenches 31 and the plurality of gate trenches 2221 are in one-to-one correspondence in the first direction and are spaced apart from each other, so that on the premise of avoiding interference between the second sub-trenches 31 and the gate trenches 2221 in the process, not only the circuit distribution of the semiconductor device 100 is more uniform, the working performance of the semiconductor device 100 is improved, but also the gate trenches 2221 and the corresponding second sub-trenches 31 are conveniently etched synchronously, and the manufacturing flow of the semiconductor device 100 is simplified.
It should be noted that, in other embodiments of the present invention, as shown in fig. 4 and 5, when there is no dummy gate trench 223 between two adjacent gate trench groups 222, namely: when the dummy gate trench 223 is not disposed in the igbt region 101, but only the gate trench 2221 is understood to be that the plurality of gate trenches 2221 of each sub-trench portion 22 form one gate trench group 222, only the second connecting trench 50 is required to connect one end of the plurality of gate trenches 2221 adjacent to the second trench 30, and one end of the plurality of second trenches 30 is required to connect one end of the plurality of first connecting trenches 40 in the first direction, and the other end of the plurality of second trenches 30 in the first direction, so that not only the igbt region 101 and the fast recovery diode region 102 can be prevented from interfering with each other in the process, the respective performances of the two regions can be ensured, but also the current-carrying capacity of the two regions can be increased, and the working performance of the semiconductor device 100 can be improved.
In the above, the two sides of the second direction of the plurality of second trenches 30 are defined as the first boundary trench 33 and the second boundary trench 34, respectively, so that the inside of the region surrounded by the first boundary trench 33, the second boundary trench 34 and the two first connection trenches 4 is the fast recovery diode region 102, and the outside of the region surrounded by the first boundary trench 33, the second boundary trench 34 and the two first connection trenches 40 is the insulated gate bipolar transistor region 101.
Considering that the first connection trench 40 is located at the junction of the fast recovery diode region 102 and the fast recovery diode region 101, by arranging the first connection trench 40 and the second connection trench 50 at intervals in the first direction, not only the fast recovery diode region 102 and the fast recovery diode region 101 can be spaced apart, but also mutual interference between the fast recovery diode region 102 and the fast recovery diode region 101 in the process can be avoided more effectively and reliably, performance of the fast recovery diode region 102 and the fast recovery diode region 101 can be ensured, and current-carrying capacity of the semiconductor device 100 can be increased, and operation performance of the semiconductor device 100 can be improved.
As shown in fig. 2 and 3, the first connection grooves 40 and the second connection grooves 50 are spaced apart by a distance D1 in the first direction, the adjacent two first grooves 20 are spaced apart by a distance D2 in the second direction, and the adjacent two second grooves 30 are spaced apart by a distance D3 in the second direction, the distances D1, D2, and D3 satisfy the relation: d1 =d2=d3.
Specifically, by setting the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction, the spacing distance between two adjacent first trenches 20 in the second direction, and the spacing distance between two adjacent second trenches 30 in the second direction to be equal, the distribution of the first connection trench 40 and the second connection trench 50 can be made more uniform, the uniformity of the circuit distribution of the semiconductor device 100 can be improved, and the operation performance of the semiconductor device 100 can be improved.
In addition, the processes in the first trench 20, the second trench 30, the first connection trench 40 and the second connection trench 50 are the same, the oxide insulating layer 70 may be generated and the polysilicon 71 may be deposited therein, and the widths of the first trench 20, the second trench 30, the first connection trench 40 and the second connection trench 50 may be set to be the same, and the depths may be set to be the same, so that the first trench 20, the second trench 30, the first connection trench 40 and the second connection trench 50 may be simultaneously etched, and the process steps of the semiconductor device 100 may be simplified.
Further, D1 satisfies the relation: d1 is less than or equal to 1.5 mu m and less than or equal to 2 mu m. Specifically, by setting the spacing distance of the first connection trench 40 and the second connection trench 50 in the first direction within a reasonable range, not only can the spacing distance of the first connection trench 40 and the second connection trench 50 in the first direction be prevented from being too small, but also the separation effect of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 can be prevented from being poor, resulting in that the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 still have mutual interference in the process, and the spacing distance of the first connection trench 40 and the second connection trench 50 in the first direction can be prevented from being too large, resulting in that the overall area of the semiconductor device 100 is too large, so that the balance between the separation effect of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 and the overall area of the semiconductor device 100 can be realized, the structural design of the semiconductor device 100 can be further optimized, and the working performance of the semiconductor device 100 can be improved.
Further, D1 satisfies the relation: 1.5 μm.ltoreq.D1.ltoreq.2μm, so that the separation distance of the first connection trench 40 and the second connection trench 50 in the first direction can be set within a more preferable range, thereby further ensuring the balance between the separation effect of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 and the overall area of the semiconductor device 100, further optimizing the structural design of the semiconductor device 100, and improving the operation performance of the semiconductor device 100.
The method of fabricating the semiconductor device 100 is described below by way of example with reference to fig. 3 and fig. 6-10, the semiconductor device 100 being an RC-IGBT:
as shown in fig. 6, an N-substrate material is provided. Forming structure 1.
As shown in fig. 7, on the basis of the structure 1, the first trenches 20, the second trenches 30, the first connection trenches 40, and the second connection trenches 50 are etched, and an oxide insulating layer 70 is grown. Forming structure 2.
As shown in fig. 8, on the basis of the structure 2, polysilicon 71 is deposited and etched, and then P-well region 11 and n+ second emitter layer 12 are sequentially implanted to form the structure 3.
As shown in fig. 9, on the basis of the structure 3, a dielectric layer 13 is deposited, and contact holes are etched in the dielectric layer 13, forming the structure 4.
As shown in fig. 10, on the basis of the structure 4, an emitter metal layer 14 is prepared by metal layer sputtering, forming the structure 5.
As shown in fig. 3, on the basis of the structure 5, a collector metal layer 18 is prepared by sequentially performing back surface n+ field stop layer 15 implantation, back surface p+ collector layer 16 implantation, back surface FRD region n+ first emitter layer 17 implantation, laser annealing, and back surface metal sputtering. The semiconductor device 100 is finally formed.
Other configurations and operations of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description of the present invention, it should be understood that the terms "center," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A semiconductor device, comprising:
a base body (80), wherein the base body (80) has a first main surface (81) and a second main surface (82) on the opposite side of the first main surface (81);
a drift layer (10) of a first conductivity type, the drift layer (10) being provided between a first main surface (81) and a second main surface (82);
a first trench (20), wherein the first trench (20) extends from the first main surface (81) toward the second main surface (82) and reaches into the drift layer (10), the first trench (20) extends in a first direction and is provided in plurality, the first trenches (20) are provided at intervals in a second direction, and a part of the first trenches (20) is a spacing trench (21);
the spacer trench (21) comprises two sub-trench portions (221) which are arranged at intervals in a first direction, the sub-trench portions (221) comprise a plurality of gate trench groups (222) and a plurality of dummy gate trenches (223), the plurality of gate trench groups (222) are arranged at intervals in a second direction, at least one dummy gate trench (223) is arranged between two adjacent gate trench groups (222), the gate trench groups (222) comprise at least two gate trenches (2221) which are arranged at intervals in the second direction, wherein the gate trenches (2221) are electrically connected with a gate of the semiconductor device (100), and the dummy gate trenches (223) are electrically connected with an emitter of the semiconductor device (100);
a second trench (30), wherein the second trench (30) extends from the first main surface (81) toward the second main surface (82) and reaches into the drift layer (10), the second trench (30) extends in a first direction, the second trench (30) is provided in plurality and is spaced apart from each other in a second direction, and the second trench (30) is provided between the two sub-trench portions (221) at intervals in the first direction;
-first connection trenches (40), the first connection trenches (40) extending from the first main face (81) towards the second main face (82) and reaching into the drift layer (10), the first connection trenches (40) extending in a second direction, the first connection trenches (40) being two, one of the two first connection trenches (40) connecting one end of a plurality of the second trenches (30) in the first direction and the other connecting the other end of a plurality of the second trenches (30) in the first direction, and the first connection trenches (40) being connected with one end of the dummy gate trench (223) adjacent to the second trenches (30);
-a second connection trench (50), the second connection trench (50) extending from the first main face (81) towards the second main face (82) and into the drift layer (10), the second connection trench (50) extending in a second direction, the second connection trench (50) connecting the gate trenches (2221) of the gate trench group (222) adjacent to one end of the second trench (30).
2. The semiconductor device according to claim 1, wherein an end of the dummy gate trench (223) adjacent to the second trench (30) protrudes from an end of the gate trench (2221) adjacent to the second trench (30), and wherein an end of the dummy gate trench (223) adjacent to the second trench (30) is disposed extending toward the second trench (30) and connected to the first connection trench (40).
3. The semiconductor device according to claim 2, wherein the plurality of second trenches (30) includes a first sub-trench (32), the first sub-trench (32) is a plurality, and the plurality of first sub-trenches (32) and the plurality of dummy gate trenches (223) are in one-to-one correspondence and are connected to each other.
4. A semiconductor device according to claim 3, wherein the plurality of second trenches (30) further includes a plurality of second sub-trenches (31), the plurality of second sub-trenches (31) and the plurality of gate trenches (2221) being arranged in one-to-one correspondence in the first direction and being spaced apart from each other.
5. The semiconductor device according to claim 1, wherein two of the second direction sides of the plurality of second trenches (30) are a first boundary trench (33) and a second boundary trench (34), respectively, and a fast recovery diode region (102) is formed in a region surrounded by the first boundary trench (33), the second boundary trench (34), and the two first connection trenches (40).
6. The semiconductor device according to claim 5, wherein an insulated gate bipolar transistor region (101) is outside a region surrounded by the first boundary trench (33), the second boundary trench (34) and the two first connection trenches (40) in common.
7. The semiconductor device according to claim 6, wherein the first connection trench (40) and the second connection trench (50) are disposed at intervals in a first direction.
8. The semiconductor device according to claim 1, wherein the first connection trench (40) and the second connection trench (50) are spaced apart by a distance D1 in a first direction, two adjacent first trenches (20) are spaced apart by a distance D2 in a second direction, two adjacent second trenches (30) are spaced apart by a distance D3 in the second direction, and D1, D2, and D3 satisfy the relation: d1 =d2=d3.
9. The semiconductor device according to claim 8, wherein D1 satisfies a relation: d1 is less than or equal to 1 mu m and less than or equal to 2 mu m.
10. The semiconductor device according to claim 9, wherein D1 satisfies a relation: d1 is less than or equal to 1.5 mu m and less than or equal to 2 mu m.
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| CN117637830A (en) * | 2023-11-20 | 2024-03-01 | 海信家电集团股份有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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