CN108766885B - Manufacturing method of composite gate IGBT chip with three-dimensional channel - Google Patents
Manufacturing method of composite gate IGBT chip with three-dimensional channel Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention discloses a manufacturing method of a composite gate IGBT chip with a three-dimensional channel, which comprises the following steps: forming a first oxide layer on the upper surface of the wafer substrate; etching a first preset position on the first oxide layer to expose the lower wafer substrate; injecting P-type impurities into a second preset position of the exposed wafer substrate, and diffusing the P-type impurities into the first junction depth to form a P well; etching a third preset position on the P well to form a groove, wherein the depth of the groove is greater than that of the P well; forming a second oxide layer on the inner surface of the groove and the upper surface of the exposed wafer substrate; forming a polycrystalline silicon layer in the groove and on the first oxide layer and the second oxide layer, wherein the groove is filled with the polycrystalline silicon in the groove; and etching the fourth preset position on the polycrystalline silicon layer to expose the groove opening of the groove and part of the second oxide layer above the P well. The IGBT chip manufactured by the manufacturing method has better voltage resistance, and simultaneously increases the channel density, thereby greatly improving the current density of the chip.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a manufacturing method of a composite gate IGBT chip with a three-dimensional channel.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), and is widely applied to the fields of rail transit, a smart grid, industrial frequency conversion, new energy development and the like due to the characteristics of low on-state voltage, high current density, high input impedance, high response speed and the like.
The gate of existing Insulated Gate Bipolar Transistors (IGBTs) is typically a planar gate or a trench gate. When the grid electrode of the Insulated Gate Bipolar Transistor (IGBT) is a planar grid, the Insulated Gate Bipolar Transistor (IGBT) is simple in manufacturing process, low in requirements on process equipment and good in voltage resistance of the planar grid; however, the channel region of the planar gate is on the surface, and the channel density is limited by the surface area of the chip, so that the conductance modulation effect of the planar gate is weaker, and the conduction voltage drop of the planar gate is higher. When the grid of an Insulated Gate Bipolar Transistor (IGBT) is a trench gate, a channel is converted from the transverse direction to the longitudinal direction, so that a one-dimensional current channel is realized, the JFET effect in a planar gate channel is effectively eliminated, the channel density is not limited by the surface area of a chip, and the channel density is greatly improved, so that the current density of the chip is greatly improved; however, with the increase of the trench gate density, the saturation current of the chip is too large, and the short-circuit performance of the chip is weakened, so that the safe working area of the chip is affected, and the voltage resistance of the chip is also reduced.
Therefore, a method for manufacturing an Insulated Gate Bipolar Transistor (IGBT) chip with high voltage endurance capability and capable of well avoiding the influence of the excessive saturation current of the chip on the safe working area of the chip is needed.
Disclosure of Invention
The invention aims to solve the technical problem that an insulated gate bipolar transistor chip manufactured by the prior art cannot greatly improve the current density of the chip and simultaneously ensure larger voltage-resisting capacity and wide safe working area.
In order to solve the technical problem, the invention provides a method for manufacturing a composite gate IGBT chip with a three-dimensional channel, which comprises the following steps:
forming a first oxide layer on the upper surface of the wafer substrate;
etching a first preset position on the first oxidation layer to expose the lower wafer substrate;
injecting P-type impurities into a second preset position of the exposed wafer substrate, and diffusing the P-type impurities into the first junction depth to form a P well;
etching a third preset position on the P well to form a groove, wherein the depth of the groove is greater than that of the P well;
forming a second oxide layer on the inner surface of the groove and the upper surface of the exposed wafer substrate;
forming a polysilicon layer in the groove and on the first oxide layer and the second oxide layer, wherein the groove is filled with the polysilicon in the groove;
etching a fourth preset position on the polycrystalline silicon layer to expose a groove opening of the groove and part of the second oxide layer above the P well; and forming a planar grid by the polysilicon on the first oxide layer and the second oxide layer, and forming a trench grid by the polysilicon in the trench.
Preferably, after the forming the planar gate and the trench gate, the method further includes:
and injecting P-type impurities and N-type impurities into the P well corresponding to the fourth preset position, and enabling the P-type impurities and the N-type impurities to diffuse to a second junction depth to form a P + + region and an N + + region which are in contact with each other, wherein the second junction depth is smaller than the first junction depth.
Preferably, the P + + regions and the N + + regions are alternately disposed in the P well.
Preferably, the concentration of the P-type impurity in the P + + region is greater than the concentration of the P-type impurity in the P-well.
Preferably, after the P + + region and the N + + region are formed, the method further includes:
forming an insulating layer on the polycrystalline silicon layer, the exposed second oxide layer and the groove opening;
forming a passivation layer on the insulating layer;
etching a fifth preset position of the passivation layer, and etching the insulating layer and the second oxide layer at corresponding positions below the fifth preset position to expose part of the P + + region and part of the N + + region to form a contact groove;
and depositing a metal layer in the contact groove and on the passivation layer to form a source electrode.
Preferably, the contact grooves are located on two sides of the trench gate, so that the source electrode is in contact connection with each of the P + + region and the N + + region on the wafer substrate.
Preferably, the first oxide layer has a thickness greater than that of the second oxide layer, and the first oxide layer and the second oxide layer are smoothly connected.
Preferably, between the step of etching the first oxide layer and the step of forming the P-well, the method further comprises:
and injecting the N-type impurities into a second preset position of the exposed wafer substrate, and diffusing the N-type impurities to a third junction depth to form an N well, wherein the third junction depth is greater than the second junction depth.
Preferably, the method for manufacturing the composite gate IGBT chip with a three-dimensional channel according to the present invention further includes: and forming the back structure of the composite gate IGBT chip.
Preferably, the specific steps of forming the back structure of the composite gate IGBT chip are as follows:
injecting N-type impurities into the lower surface of the wafer substrate, and diffusing the N-type impurities to form a buffer layer;
injecting P-type impurities into the buffer layer, and diffusing the P-type impurities to form an anode layer;
a back metal layer is formed on the anode layer.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
by applying the manufacturing method of the composite gate IGBT chip with the three-dimensional channel, provided by the embodiment of the invention, the planar gate and the trench gate are integrated on the same chip through the same process to form the three-dimensional channel, so that the grid electrode of the manufactured composite gate IGBT chip comprises the planar gate and the trench gate, and the IGBT chip manufactured by the manufacturing method has better pressure resistance, and simultaneously, the channel density is increased, thereby greatly improving the current density of the chip. Meanwhile, the composite gate IGBT chip with the three-dimensional channel, which is manufactured by the manufacturing method, increases the thickness of the gate oxide layer in the non-channel region by setting the thickness of the first oxide layer to be larger than that of the second oxide layer, thereby reducing the output capacitance of the IGBT chip and reducing the parasitic capacitance effect when the IGBT chip is switched on and switched off.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic flow chart illustrating a method for manufacturing a structure of an upper surface of a composite gate IGBT chip having a three-dimensional channel according to a first embodiment of the present invention;
fig. 2 is a schematic process diagram illustrating a manufacturing method of a back structure of a composite gate IGBT chip with a three-dimensional channel according to a first embodiment of the present invention;
fig. 3 is a schematic process diagram illustrating a manufacturing method of a composite gate IGBT chip structure with a three-dimensional channel according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a composite gate IGBT chip with a three-dimensional channel manufactured by the method for manufacturing a composite gate IGBT chip with a three-dimensional channel according to the first embodiment of the present invention;
fig. 5 shows a schematic structural diagram of a composite gate IGBT chip with a three-dimensional channel manufactured by the method for manufacturing a composite gate IGBT chip with a three-dimensional channel according to the second embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
An Insulated Gate Bipolar Transistor (IGBT) has advantages of a low on-state voltage, a high current density, a high input impedance, a high response speed, and the like, and thus is widely used in various fields. The gate of existing Insulated Gate Bipolar Transistors (IGBTs) is typically a planar gate or a trench gate. The Insulated Gate Bipolar Transistor (IGBT) chip with the planar gate has the advantages of simple manufacturing process, lower requirements on manufacturing equipment and better voltage resistance, but the conducting voltage drop of the IGBT chip is higher because the channel density of the planar gate is limited by the surface area of the chip. The Insulated Gate Bipolar Transistor (IGBT) chip with the trench gate can convert a channel from a transverse direction to a longitudinal direction, so that a one-dimensional current channel is realized, the current density of the chip is greatly improved, but the saturation current of the chip is too large along with the increase of the density of the trench gate, the short-circuit performance of the chip is weakened, and the safe working area of the chip is influenced.
Example one
In order to solve the technical problems in the prior art, the embodiment of the invention provides a manufacturing method of a composite gate IGBT chip with a three-dimensional channel.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing an upper surface structure of a composite gate IGBT chip having a three-dimensional channel according to a first embodiment of the present invention; fig. 3 shows a schematic process diagram of a method for manufacturing a composite gate IGBT chip with a three-dimensional channel according to a first embodiment of the present invention.
Referring to fig. 1 and 3, the method for manufacturing the composite gate IGBT chip with a three-dimensional channel according to the present embodiment includes the following steps.
In step S101, a first oxide layer 1 is formed on the upper surface of the wafer substrate 2.
Preferably, the wafer substrate 2 can be a silicon wafer, and the first oxide layer 1 is silicon dioxide. Specifically, a layer of uniform silicon dioxide is formed on the upper surface of the silicon wafer in a deposition mode or directly formed on the upper surface of the silicon wafer in a thermal oxidation mode. The thickness of the silicon dioxide is between 0.5 μm and 2.5 μm.
It should be noted that in other embodiments of the present invention, the oxide layer may be formed on the wafer substrate 2 in other reasonable manners, but the present invention is not limited thereto.
Step S102, etching a first predetermined position on the first oxide layer 1 to expose the lower wafer substrate 2.
Specifically, a first preset position on the first oxide layer 1 is etched by a wet etching method, and the wafer substrate 2 below is exposed, so that a window is formed on the first oxide layer 1. Wherein, the silicon dioxide on both sides of the window and the exposed wafer substrate 2 are smoothly connected, so that the fracture phenomenon does not occur in the subsequent forming process of the polysilicon layer and the like. Specifically, the silicon dioxide on both sides of the window may be etched to form an inclined plane connecting the upper surface of the first oxide layer 1 and the upper surface of the exposed wafer substrate 2.
It should be noted that the first preset position does not only indicate one specific position, and since the IGBT chip includes a plurality of cells located on the wafer substrate 2, and each cell structure of the IGBT chip formed in this embodiment is the same, a plurality of positions of the first oxide layer 1 need to be etched to form a plurality of windows in the step of etching the first oxide layer 1 to form the windows, and therefore the first preset position includes all positions on the wafer substrate 2 where the windows need to be formed. For further understanding, the operation of the window positions in the subsequent steps is for each window position on the wafer substrate 22, and will not be described below.
Step S103, implanting P-type impurities into the second predetermined position of the exposed wafer substrate 2, and diffusing the P-type impurities into the first junction depth to form the P-well 5.
Specifically, photoresist is used as a mask plate, P-type impurities are injected to a second preset position of the exposed wafer substrate 2 and diffused to a first junction depth to form a P well 5, furthermore, the P-type impurities are boron, photoresist is formed on the first oxide layer 1 and the exposed wafer substrate 2, the photoresist is exposed by using a mask tool, the second preset position of the wafer substrate 2 is exposed, P-type impurities boron is injected to the second preset position of the wafer substrate 2, and the dosage range of the injected boron is 1 × 1014cm-2To 3 × 1014cm-2(ii) a The remaining photoresist is stripped and the implanted P-type impurity boron is driven in to diffuse the first junction depth to form the P-well 5, preferably in the range of 5 to 6 μm.
It should be noted that after the P-type impurity is injected into the wafer substrate 2, a protective oxide layer can be formed on the exposed wafer substrate and then the P-type impurity is pushed in, the protective oxide layer can be arranged to effectively avoid the loss of the P-type impurity in the diffusion process, and in order not to affect the subsequent steps, the protective oxide layer is etched after the P-well 5 is formed. Under certain conditions, the loss in the advancing process of the P-type impurities is not large and can be ignored, so the forming step of the protective oxide layer can be omitted. In other embodiments of the present invention, other reasonable ways to avoid the loss of P-type impurities during the propelling process can be adopted, and the present invention is not limited thereto.
And step S104, etching a third preset position on the P well 5 area to form a groove, wherein the depth of the groove is greater than that of the P well 5.
Specifically, photoresist is used as a mask plate, and a third preset position on the P trap 5 area is etched to form a groove. Preferably, the trench is located in the middle of the P-well 5 region, and the depth of the trench is greater than the depth of the P-well 5, that is, the trench divides the P-well 5 region into two parts which are axisymmetric left and right. Further, a photoresist layer is formed on the exposed wafer substrate 2, the first oxide layer 1 and the P-well 5 region, the photoresist is exposed by using a mask tool, a third preset position on the P-well 5 region is exposed, the third preset position on the P-well 5 region is etched, a groove deeper than the P-well 5 is formed, and the rest of the photoresist is stripped.
In step S105, a second oxide layer 6 is formed on the inner surface of the trench and the upper surface of the exposed wafer substrate 2.
Specifically, a uniform silicon dioxide layer, i.e., the second oxide layer 6, is formed on the inner surface of the trench and the exposed wafer substrate 2 by thermal oxidation. Preferably, the thickness of the second oxide layer 6 ranges from 1000nm to 1500 nm.
It should be noted that, according to the thickness ranges of the first oxide layer 1 and the second oxide layer 6, the thickness of the first oxide layer 1 is greater than that of the second oxide layer 6, and the second oxide layer 6 is disposed on the exposed wafer substrate 2 after etching the first oxide layer 1, so that the upper surface of the first oxide layer 1 is gently connected to the upper surface of the second oxide layer 6.
Step S106, a polysilicon layer 7 is formed in the trench and on the first oxide layer 1 and the second oxide layer 6, and the trench is filled with the polysilicon in the trench.
Specifically, polysilicon is deposited in the trench and on the first oxide layer 1 and the second oxide layer 6 to form a polysilicon layer 7, and the polysilicon in the trench fills the trench. The polysilicon layer 7 in the non-trench is uniform in thickness, ranging from 1 μm to 2 μm.
Step S107, etching a fourth preset position on the polycrystalline silicon layer 7 to expose a groove opening of the groove and the second oxide layer 6 above partial P wells 5 at two sides of the groove opening; so that the polysilicon in the non-trench on the first oxide layer 1 and the second oxide layer 6 forms a planar gate and the polysilicon in the trench forms a trench gate.
And step S108, injecting a P-type impurity and an N-type impurity into the P well 5 corresponding to the fourth preset position, and enabling the P-type impurity and the N-type impurity to diffuse to a second junction depth to form a P + + region 14 and an N + + region 13 which are in contact with each other, wherein the second junction depth is smaller than the first junction depth.
Specifically, P-type impurities and N-type impurities are alternately injected into the P-well 5 corresponding to the fourth preset position along the extending direction of the trench, and the P-type impurities and the N-type impurities are pushed to diffuse to a second junction depth, so that a P + + region 14 and an N + + region 13 which are adjacent to each other are formed, and the second junction depth is smaller than the first junction depth.
It should be noted that P + + region 14 and N + + region 13 are formed symmetrically with respect to the trench axis, i.e., P + + region 14 and N + + region 13 are formed on both sides of the trench. Meanwhile, it should be noted that the P + + region 14 and the N + + region 13 are formed by diffusion on the basis of the P well 5, so that the overlapping portion of the original P well 5 and the newly formed P + + region 14 and N + + region 13 is the P + + region 14 and N + + region 13, and in the process of forming the P + + region 14 and N + + region 13 by advancing the P-type impurities and N-type impurities, the P-type impurities in the P well 5 are also diffused again, so that the P well portion finally formed and surrounding the P + + region 14 and N + + region 13 is the P well 5 without advancing. The concentration of the P-type impurity in the P + + region 14 is greater than the concentration of the P-type impurity in the P well 5.
In step S109, an insulating layer 8 is formed on the polysilicon layer 7, the exposed second oxide layer 6 and the trench opening.
Specifically, an insulating layer 8 is formed on the etched polysilicon layer 7, the exposed second oxide layer 6 and the trench opening to insulate the polysilicon from a subsequent passivation layer 9. Preferably, the insulating layer 8 material is silicon dioxide.
Step S110, depositing a passivation layer 9 on the insulating layer 8, wherein the thickness of the passivation layer 9 ranges from 0.5 μm to 2 μm.
Step S111, etching a fifth preset position of the passivation layer 9, and etching the insulating layer 8 and the second oxide layer 6 at corresponding positions below the fifth preset position to expose a part of the P + + region 14 and a part of the N + + region 13, thereby forming a contact trench 12.
Specifically, a fifth preset position of the passivation layer 9 is etched, and the insulating layer 8 and the second oxide layer 6 at corresponding positions below the fifth preset position are etched to expose a portion of the P + + region 14 and a portion of the N + + region 13 on two sides of the trench, respectively, so as to form two contact grooves 12 parallel to the trench. The contact grooves 12 are used to connect the subsequently formed metal layer 10 in contact with each of the P + + regions 14 and N + + regions 13 on the wafer substrate 2. To further define the contact connection of the metal layer with the P + + region 14 and the N + + region 13 on the wafer substrate 2, a portion of the corresponding P + + region 14 and N + + region 13 below the contact trench may be further etched (without etching through the P + + region 14 and N + + region 13) during the etching of the contact trench to ensure that no second oxide layer remains in the corresponding location.
In step S112, a metal layer 10 is deposited in the contact hole and on the passivation layer 9 to form a source electrode. Preferably, the metal layer 10 material is aluminum.
In the above steps of the process for forming the upper surface structure of the composite gate IGBT chip with the three-dimensional channel, a certain structure needs to be formed on the lower surface of the IGBT chip in the actual production process, and fig. 2 shows a flowchart of a method for manufacturing the back surface structure of the composite gate IGBT chip with the three-dimensional channel in the first embodiment of the present invention. Referring to fig. 2, the back structure is formed as follows.
In step S201, an N-type impurity is implanted into the lower surface of the wafer substrate 2 and diffused to form the buffer layer 3.
Specifically, an N-type impurity is implanted into the lower surface of the wafer substrate 2 at an implantation dose of 1 × 1012cm-2To 1 × 1013cm-2And the N-type impurities are pushed and diffused, so that a uniform buffer layer 3 is formed on the lower surface of the wafer substrate 2.
In step S202, P-type impurities are implanted into the buffer layer 3 and diffused to form the anode layer 4.
Specifically, P-type impurities are implanted into the buffer layer 3 at an implant dose of 1e13 to 2e14cm-2, and the P-type impurities are driven to diffuse, so that the anode layer 4 is formed on the buffer layer 3, and the junction depth is about 0.5um to 4 um.
In step S203, a back metal layer 11 is formed on the anode layer 4.
It should be noted that the formation process of the structure on the upper surface of the composite gate IGBT chip having the three-dimensional channel and the formation process of the back surface structure may be performed simultaneously, for example, step S201 may be performed simultaneously with step S101, step S202 may be performed simultaneously with step S103, and step S203 may be performed simultaneously with step S112.
It should be noted that the diffusion process of all impurities in the present invention includes not only longitudinal diffusion but also lateral diffusion. The planar grid and the groove grid are realized by adopting a self-alignment process, so that the process deviation caused by multiple photoetching alignment is reduced, and the process cost is reduced.
Fig. 4 shows a schematic structural diagram of a composite gate IGBT chip with a three-dimensional channel manufactured by the method for manufacturing a composite gate IGBT chip with a three-dimensional channel according to the first embodiment of the present invention.
By applying the manufacturing method of the composite gate IGBT chip with the three-dimensional channel, provided by the embodiment of the invention, the planar gate and the trench gate are integrated on the same chip through the same process to form the three-dimensional channel, so that the grid electrode of the manufactured composite gate IGBT chip comprises the planar gate and the trench gate, and the IGBT chip manufactured by the manufacturing method has better pressure resistance, and simultaneously, the channel density is increased, thereby greatly improving the current density of the chip. Meanwhile, the composite gate IGBT chip with the three-dimensional channel, which is manufactured by the manufacturing method, increases the thickness of the gate oxide layer in the non-channel region by setting the thickness of the first oxide layer 1 to be larger than that of the second oxide layer 6, so that the output capacitance of the IGBT chip is reduced, and the parasitic capacitance effect of the IGBT chip during switching is reduced. The planar grid and the groove grid in the three-dimensional channel formed by the invention can pass through metal during working, so that the planar grid and the groove grid can be jointly used as the grid of the IGBT chip, and the planar grid and the groove grid can be simultaneously turned on and turned off.
Example two
In order to solve the technical problems in the prior art, the embodiment of the invention also provides another manufacturing method of the composite gate IGBT chip with the three-dimensional channel.
Fig. 5 shows a schematic structural diagram of a composite gate IGBT chip with a three-dimensional channel manufactured by the method for manufacturing a composite gate IGBT chip with a three-dimensional channel according to the second embodiment of the present invention.
The embodiment method is that step 1021 is added between step S102 and step S103 on the basis of the first embodiment, and specifically, the following steps are added:
step 1021, implanting the N-type impurity into the second predetermined position of the exposed wafer substrate 2, and diffusing the N-type impurity to a third junction depth to form the N-well 15, wherein the third junction depth is greater than the first junction depth.
In this case, step 103 should be: and injecting P-type impurities into the N well 15 at a position corresponding to the second preset position, and diffusing the P-type impurities to a first junction depth to form a P well 5. Other steps are the same as those in the first embodiment, and are not described again here.
It should be noted that, when the P well 5, the P + + region 14 and the N + + region 13 are formed respectively by performing diffusion on impurities in the subsequent process, the previously formed N well 15 is also diffused again, and the finally formed N well 15 of the composite gate IGBT chip with a three-dimensional channel should be the portion of the N well 15 which surrounds the outside of the P well 5 and is not diffused any more at last. The corresponding P-well 5 is the portion that overlaps the original N-well 15, but does not overlap the P + + region 14 and the N + + region 13.
The diffusion process of all the impurities in this embodiment also includes longitudinal diffusion and lateral diffusion.
By applying the embodiment of the invention, on the basis of the beneficial effect achieved by the first embodiment, the N-type doped region is additionally arranged on the periphery of the P well 5, and the conductance modulation effect of the composite gate IGBT chip with the three-dimensional channel in the drift region is further increased.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A manufacturing method of a composite gate IGBT chip with a three-dimensional channel is characterized by comprising the following steps:
forming a first oxide layer on the upper surface of the wafer substrate;
etching a first preset position on the first oxidation layer to expose the lower wafer substrate;
injecting P-type impurities into a second preset position of the exposed wafer substrate, and diffusing the P-type impurities into the first junction depth to form a P well;
etching a third preset position on the P well to form a groove, wherein the depth of the groove is greater than that of the P well;
forming a second oxide layer on the inner surface of the groove and the upper surface of the exposed wafer substrate;
forming a polysilicon layer in the groove and on the first oxide layer and the second oxide layer, wherein the groove is filled with the polysilicon in the groove;
etching a fourth preset position on the polycrystalline silicon layer to expose a groove opening of the groove and a part of the second oxidation layer above the P trap, so that polycrystalline silicon on the first oxidation layer and the second oxidation layer form a planar grid, and polycrystalline silicon in the groove forms a groove grid;
injecting P-type impurities and N-type impurities into the P well corresponding to the fourth preset position, and enabling the P-type impurities and the N-type impurities to diffuse to a second junction depth to form a P + + region and an N + + region which are in contact with each other, wherein the second junction depth is smaller than the first junction depth; wherein a region formed by the P + + region and the N + + region is in contact with the trench and extends to a position below the planar gate;
forming an insulating layer on the polycrystalline silicon layer, the exposed second oxide layer and the groove opening;
forming a passivation layer on the insulating layer;
and etching a fifth preset position of the passivation layer, and etching the insulating layer and the second oxide layer at corresponding positions below the fifth preset position to expose part of the P + + region and part of the N + + region to form a contact groove.
2. The method of claim 1, wherein said P + + regions and N + + regions are alternately disposed in said P-well.
3. The method of claim 1, wherein a concentration of P-type impurities in the P + + region is greater than a concentration of P-type impurities in the P-well.
4. The method of any one of claims 1 to 3, further comprising, after forming the contact groove:
and depositing a metal layer in the contact groove and on the passivation layer to form a source electrode.
5. The method according to claim 4, wherein the contact grooves are located on two sides of the trench gate, so that the source electrode is in contact connection with each of the P + + region and the N + + region on the wafer substrate.
6. The method according to claim 1, wherein the first oxide layer has a thickness greater than that of the second oxide layer, and the first oxide layer and the second oxide layer are smoothly connected.
7. The method of claim 1, further comprising, between the etching the first oxide layer and the forming the P-well:
and injecting the N-type impurities into a second preset position of the exposed wafer substrate, and diffusing the N-type impurities to a third junction depth to form an N well, wherein the third junction depth is greater than the second junction depth.
8. The method of claim 1, further comprising: and forming the back structure of the composite gate IGBT chip.
9. The manufacturing method according to claim 8, wherein the step of forming the back structure of the composite gate IGBT chip comprises the following steps:
injecting N-type impurities into the lower surface of the wafer substrate, and diffusing the N-type impurities to form a buffer layer;
injecting P-type impurities into the buffer layer, and diffusing the P-type impurities to form an anode layer;
a back metal layer is formed on the anode layer.
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| CN205231070U (en) * | 2015-12-30 | 2016-05-11 | 杭州士兰集成电路有限公司 | IGBT device |
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Effective date of registration: 20200928 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |