CN115566060B - IGBT device and preparation method thereof - Google Patents
IGBT device and preparation method thereof Download PDFInfo
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- CN115566060B CN115566060B CN202211408017.1A CN202211408017A CN115566060B CN 115566060 B CN115566060 B CN 115566060B CN 202211408017 A CN202211408017 A CN 202211408017A CN 115566060 B CN115566060 B CN 115566060B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract
The invention provides an IGBT device and a preparation method thereof, wherein the device comprises: a substrate on which an IGBT emitter, an IGBT gate and an IGBT collector are formed; the dummy grid is arranged between the grid and the IGBT emitter; the NMOS tube is arranged between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode is electrically connected with the dummy grid electrode; and the NPN triode is arranged between the dummy grid electrode and the IGBT emitter electrode, the collector electrode of the NPN triode is electrically connected with the dummy grid electrode, the emitter electrode is electrically connected with the IGBT emitter electrode, and the base electrode is electrically connected with the IGBT emitter electrode through an inductor. According to the invention, the change of the potential of the dummy grid is controlled in different working states (on state and off process) of the device, so that the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to an IGBT device and a preparation method thereof.
Background
An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (bipolar transistor) and a MOS (insulated gate field effect transistor). The IGBT device has the advantages of reduced saturation voltage, high current density, small driving power and high switching speed, and is suitable for a power supply management system with the withstand voltage of more than 600V.
The losses of the IGBT device generally include a conduction loss and a switching loss, and in designing the device, a compromise is generally required between the conduction loss and the switching loss, and in order to optimize the switching loss of the device, a dummy gate is generally used to reduce the switching loss of the device, but the arrangement of the dummy gate increases the conduction loss of the IGBT device.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an IGBT device and a method for manufacturing the same, which are used for solving the problem of larger conduction loss or/and switching loss of the IGBT device in the prior art.
To achieve the above and other related objects, the present invention provides an IGBT device comprising: a substrate, on which an IGBT emitter, an IGBT gate and an IGBT collector of the IGBT device are formed; a dummy gate disposed between the gate and the IGBT emitter; the NMOS tube is arranged on the substrate and between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the NMOS tube is electrically connected with the dummy grid electrode; and the NPN triode is arranged on the substrate, between the dummy grid and the IGBT emitter, the collector of the NPN triode is electrically connected with the dummy grid, the emitter is electrically connected with the IGBT emitter, and the base is electrically connected with the IGBT emitter through an inductor.
Optionally, when the IGBT device is turned on, the IGBT gate applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, so that the IGBT gate is connected to the dummy gate, and a channel is formed under the dummy gate to reduce the turn-on loss of the IGBT device.
Optionally, when the IGBT device is turned off, the current of the IGBT emitter decreases, and there is a voltage change in inductance between the NPN triode and the IGBT emitter, so that the NPN triode is in an amplified state and turned on, so that the dummy gate is connected to the IGBT emitter, thereby reducing turn-off loss of the IGBT device.
Optionally, the threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is only less than or equal to 5V.
Optionally, the IGBT gate and the dummy gate are arranged in a ring shape, the dummy gate surrounds the IGBT emitter periphery, and the IGBT gate surrounds the dummy gate periphery.
Optionally, the substrate includes a first surface and a second surface opposite to each other, the IGBT emitter and the IGBT gate are disposed on the first surface of the substrate, and the IGBT collector is disposed on the second surface of the substrate, or/and the IGBT device further includes a field stop layer disposed in the substrate and disposed close to the IGBT collector.
Optionally, the inductance value of the inductor is 10nH to 20nH.
The invention also provides a preparation method of the IGBT device, which comprises the following steps: providing a substrate, and forming an IGBT emitter, an IGBT gate, an IGBT collector and a dummy gate of an IGBT device on the substrate, wherein the dummy gate is arranged between the gate and the IGBT emitter; an NMOS tube is arranged on the substrate, the NMOS tube is arranged between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode is electrically connected with the dummy grid electrode; and an NPN triode is arranged on the substrate, the NPN triode is arranged between the dummy grid and the IGBT emitter, the collector of the NPN triode is electrically connected with the dummy grid, the emitter is electrically connected with the IGBT emitter, and the base is electrically connected with the IGBT emitter through an inductor.
Optionally, disposing an NMOS transistor and an NPN transistor on the substrate includes the steps of: forming a P well and an N well in the substrate through an ion implantation process; forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate and a gate of an NMOS tube through patterning; forming a source electrode and a drain electrode of an NMOS tube in the P well through an ion implantation process, and forming a base electrode and an emitter electrode of an NPN triode in the N well; forming an insulating layer on the substrate, forming a contact hole in the insulating layer, forming a metal layer on the contact hole and the insulating layer, forming a wiring layer through patterning, enabling a source electrode and a grid electrode of the NMOS tube to be electrically connected with the IGBT grid electrode, enabling a drain electrode to be electrically connected with the dummy grid electrode, enabling a collector electrode of the NPN triode to be electrically connected with the dummy grid electrode, enabling an emitter electrode to be electrically connected with the IGBT emitter electrode, and enabling a base electrode to be connected with a contact point.
Optionally, the method further comprises the steps of: and an inductor is connected between a contact point of the base electrode of the NPN triode and the IGBT emitter through an external pin, and the inductance value of the inductor is 10 nH-20 nH.
Optionally, when the IGBT device is turned on, the IGBT gate applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, so that the IGBT gate is connected to the dummy gate, and a channel is formed below the dummy gate to reduce the turn-on loss of the IGBT device; when the IGBT device is turned off, the current of the IGBT emitter is reduced, and the inductance between the NPN triode and the IGBT emitter has voltage change, so that the NPN triode is in an amplified state and is turned on, the dummy gate is connected with the IGBT emitter, and the turn-off loss of the IGBT device is reduced.
Optionally, the threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is only less than or equal to 5V.
Optionally, the IGBT gate and the dummy gate are arranged in a ring shape, the dummy gate surrounds the IGBT emitter periphery, and the IGBT gate surrounds the dummy gate periphery.
Optionally, the substrate includes a first surface and a second surface opposite to each other, the IGBT emitter and the IGBT gate are disposed on the first surface of the substrate, and the IGBT collector is disposed on the second surface of the substrate, or/and the IGBT device further includes a field stop layer disposed in the substrate and disposed close to the IGBT collector.
As described above, the IGBT device and the method of manufacturing the same of the present invention have the following advantageous effects:
when the IGBT device is conducted, the threshold voltage is applied to the IGBT gate, and the threshold voltage is simultaneously applied to the gate of the NMOS tube to conduct the NMOS tube, so that the IGBT gate is connected with the dummy gate, and a channel is formed below the dummy gate to reduce the conduction loss of the IGBT device. When the IGBT device is turned off, the current of the IGBT emitter is reduced, and the inductance between the NPN triode and the IGBT emitter has voltage change, so that the NPN triode is in an amplifying state and is turned on, the dummy grid is connected with the IGBT emitter, and the turn-off loss of the IGBT device is reduced. According to the invention, through controlling the change of the potential of the dummy grid electrode in different working states of the device, the heating of the device can be effectively improved, the power density is increased, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.
The NMOS transistor and the NPN triode are arranged among the IGBT grid electrode, the dummy grid electrode and the IGBT emitter electrode, the area of the device is not required to be occupied additionally, the turn-off loss and the turn-on loss of the device can be reduced simultaneously under the condition of smaller volume, the manufacturing process of the NMOS transistor is compatible with the conventional manufacturing process of the IGBT device, additional manufacturing equipment is not required to be added, and the manufacturing cost of the device can be effectively controlled.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some of the embodiments of the present application.
Fig. 1 is a schematic diagram of a layout structure of an IGBT device according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of an IGBT device according to an embodiment of the invention.
Fig. 3 to 8 show schematic structural diagrams of steps of a method for manufacturing an IGBT device according to an embodiment of the invention.
Description of element reference numerals
10 IGBT grid
11. Dummy gate
12 IGBT emitter
13 NMOS tube
14 NPN triode
15. Inductance
101. Substrate and method for manufacturing the same
102 P-well
103 N-well
104 NMOS grid electrode
106 NMOS source electrode
107 NMOS drain electrode
108. Base electrode
109. Emitter electrode
110. Insulating layer
111. First wiring
112. Second wiring
113. Contact point
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 8, the present embodiment provides an IGBT device including: a substrate 101, wherein an IGBT emitter 12, an IGBT gate 10 and an IGBT collector of the IGBT device are formed on the substrate 101; a dummy gate 11 disposed between the gate and the IGBT emitter 12; an NMOS transistor 13, wherein the NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, a source 109 and a gate 104 of the NMOS transistor 13 are electrically connected to the IGBT gate 10, and a drain 107 is electrically connected to the dummy gate 11; and an NPN triode 14, wherein the NPN triode 14 is disposed on the substrate 101 and between the dummy gate 11 and the IGBT emitter 12, a collector 108 of the NPN triode 14 is electrically connected to the dummy gate 11, an emitter 109 is electrically connected to the IGBT emitter 12, and a base 108 is electrically connected to the IGBT emitter 12 through an inductor 15.
The substrate 101 may be, for example, a silicon substrate 101, and the substrate 101 may also include other semiconductors such as germanium, silicon carbide (SiC), or silicon germanium (SiGe), among others. The substrate 101 may include a compound semiconductor and/or an alloy semiconductor, such as gallium nitride, gallium arsenide, or the like. In addition, the substrate 101 may include an epitaxial layer (epitaxial layer) or may be strained to improve performance. In this embodiment, the substrate 101 includes a drift region, such as an N-type lightly doped drift region.
The substrate 101 includes a first surface and a second surface opposite to each other, the IGBT emitter 12 and the IGBT gate 10 are disposed on the first surface of the substrate 101, and the IGBT collector is disposed on the second surface of the substrate 101, or/and the IGBT device further includes a field stop layer disposed in the substrate 101 and disposed close to the IGBT collector.
In one embodiment, the IGBT-emitter 12 of the IGBT-device comprises an n+ type emitter region, and a P-type body region, not shown, arranged between the n+ type emitter region and the N-type drift region.
As shown in fig. 1, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, such as a rectangular ring, a rounded rectangular ring, an elliptical ring, a circular ring, etc., the dummy gate 11 surrounds the periphery of the IGBT emitter 12, the IGBT gate 10 surrounds the periphery of the dummy gate 11, a space is provided between the IGBT gate 10 and the dummy gate 11, and a space is provided between the dummy gate 11 and the IGBT emitter 12.
As shown in fig. 1 and 8, fig. 8 is a schematic cross-sectional structure of the broken line in fig. 1, where the NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, and the NMOS transistor 13 includes a P-well 102 disposed in the substrate 101, an NMOS gate 104 disposed on the P-well 102, and a source 106 and a drain 107 disposed in the P-well 102 on both sides of the NMOS gate 104. In one embodiment, the threshold voltage of the NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the difference between the threshold voltage of the IGBT gate 10 and the threshold voltage of the NMOS transistor 13 is only less than or equal to 5V. For example, the threshold voltage of the gate of the IGBT device may be 15V, and the threshold voltage of the gate of the NMOS transistor 13 may be set between 13.5V and 15V. According to the invention, through controlling the change of the potential of the dummy grid electrode in different working states of the device, the heating of the device can be effectively improved, the power density is increased, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.
As shown in fig. 1 and 8, the NPN transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the IGBT emitter 12, the NPN transistor 14 includes an N-well 103 (as a collector of the NPN transistor) disposed in the substrate 101, an NPN base 108 (P-type) located on the N-well 103, and an emitter 109 (N-type) disposed in the NPN base 108, the base 108 spacing the emitter 109 from the N-well 103.
As shown in fig. 8, the source and gate of the NMOS transistor 13 are electrically connected to the IGBT gate 10 through a first wiring 111, the drain of the NMOS transistor 11 is electrically connected to the collector of the NPN transistor 14 through a second wiring 112, the emitter 109 of the NPN transistor 14 is electrically connected to the IGBT emitter 12, a contact point 113 is provided on the base 108 through a wiring, and the contact point 113 is electrically connected to the IGBT emitter 12 through an inductor 15 when a pin is subsequently provided.
In one embodiment, the inductance value of the inductor 15 is 10nH to 20nH, for example, the inductance value of the inductor 15 may be 13nH.
In one embodiment, when the IGBT device is turned on, the IGBT gate 10 applies a threshold voltage, which is simultaneously applied to the gate of the NMOS transistor 13 to turn on the NMOS transistor 13, thereby connecting the IGBT gate 10 with the dummy gate 11, and a channel is formed under the dummy gate 11 to reduce the turn-on loss of the IGBT device.
In one embodiment, when the IGBT device is turned off, the current of the IGBT emitter 12 decreases, and there is a voltage change in the inductance 15 between the NPN transistor 14 and the IGBT emitter 12, so that the NPN transistor 14 is in an amplified state to be turned on, so that the dummy gate 11 is connected to the IGBT emitter 12, thereby reducing the turn-off loss of the IGBT device.
As shown in fig. 2, the schematic circuit diagram of the IGBT device of this embodiment is specifically that when the IGBT device is in the on state, the voltage of the gate is about 15V, the drain of the NMOS transistor 13 is shorted to the IGBT gate 10 at this time, the dummy gate 11 is shorted to the source, when the voltage of the NMOS gate 104 is 15V, the NMOS transistor 13 is turned on, the potential of the IGBT gate 10 is the same as that of the dummy gate 11, at this time, the channels on both sides of the dummy gate 11 of the device are opened, and VCESAT of the device is reduced, thereby reducing the on loss of the device.
The inductance 15 exists in the IGBT emitter 12 of the IGBT device according TO this embodiment, for example, the inductance 15 integrated in the TO247 is about 13nH, when the device is in the turn-on process, the current of the IGBT emitter 12 decreases, for example, the IGBT device of 650V15A, the current change di/dt in the inductance 15 is about 150A/us in the turn-on process of the device, so that the voltage change at two ends of the inductance 15 of the IGBT emitter 12 is 1.95V, and the NPN triode 14 is in an amplified state TO be turned on, so that the dummy gate 11 and the IGBT emitter 12 are connected together, thereby effectively reducing the turn-off loss of the device.
As shown in fig. 1 to 8, the present embodiment further provides a method for manufacturing an IGBT device, the method comprising the steps of: providing a substrate 101, forming an IGBT emitter 12, an IGBT gate 10, an IGBT collector and a dummy gate 11 of an IGBT device on the substrate 101, wherein the dummy gate 11 is arranged between the IGBT gate 10 and the IGBT emitter 12; an NMOS tube 13 is arranged on the substrate 101, the NMOS tube 13 is arranged between the IGBT gate 10 and the dummy gate 11, a source 106 and a gate 104 of the NMOS tube 13 are electrically connected with the IGBT gate 10, and a drain 107 is electrically connected with the dummy gate 11; an NPN triode 14 is disposed on the substrate 101, the NPN triode 14 is disposed between the dummy gate 11 and the IGBT emitter 12, a collector of the NPN triode 14 is electrically connected to the dummy gate 11, an emitter 109 is electrically connected to the IGBT emitter 12, and a base 108 is electrically connected to the IGBT emitter 12 through an inductor 15.
In one embodiment, as shown in fig. 3 to 8, disposing the NMOS transistor 13 and the NPN transistor 14 on the substrate 101 includes the steps of:
as shown in fig. 3 to 4, step 1) is performed first, and a P-well 102 and an N-well 103 are formed in the substrate 101 by an ion implantation process, respectively; of course, in this process, structures such as P-type body regions of the IGBT device may be fabricated at the same time, so as to save process costs.
As shown in fig. 5, step 2) is then performed to form a gate dielectric layer and a gate layer on the substrate 101, and form the IGBT gate 10, the dummy gate 11, and the gate of the NMOS transistor 13 by a patterning process. The gate dielectric layer may be silicon dioxide, or the like, or may be a high-k dielectric, such as hafnium oxide, or the like, and the gate dielectric layer may be polysilicon, metal, or the like.
As shown in fig. 6, step 3) is performed, the source 106 and the drain 107 of the NMOS transistor 13 are formed in the P-well 102 by an ion implantation process, and the P-type base 108 and the N-type emitter 109 of the NPN transistor 14 are formed in the N-well 103. Of course, in this process, structures such as an emitter region of the IGBT may be simultaneously fabricated, so as to save the process cost.
As shown in fig. 7 to 8, step 4) is finally performed, an insulating layer 110 is formed on the substrate 101, a contact hole is formed in the insulating layer 110, a metal layer is formed on the contact hole and the insulating layer 110, a wiring layer is formed by patterning, the source and the gate of the NMOS transistor 13 are electrically connected to the IGBT gate 10 through the contact hole and the wiring layer, the drain is electrically connected to the dummy gate 11, the collector of the NPN transistor 14 is electrically connected to the dummy gate 11, the emitter 109 is electrically connected to the IGBT emitter 12, and the base 108 is connected to the contact point 113.
In one embodiment, the method further comprises the steps of: an inductor 15 is connected between a contact point 113 of the base electrode 108 of the NPN triode 14 and the IGBT emitter 12 through an external pin, and the inductance value of the inductor 15 is 10 nH-20 nH.
In one embodiment, when the IGBT device is turned on, the IGBT gate 10 applies a threshold voltage, which is simultaneously applied to the gate of the NMOS transistor 13 to turn on the NMOS transistor 13, thereby connecting the IGBT gate 10 with the dummy gate 11, and forming a channel under the dummy gate 11 to reduce the turn-on loss of the IGBT device; when the IGBT device is turned off, the current of the IGBT emitter 12 decreases, and there is a voltage change in the inductance 15 between the NPN triode 14 and the IGBT emitter 12, so that the NPN triode 14 is in an amplified state and turned on, so that the dummy gate 11 is connected to the IGBT emitter 12, thereby reducing the turn-off loss of the IGBT device.
In one embodiment, the threshold voltage of the NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the difference between the threshold voltage of the IGBT gate 10 and the threshold voltage of the NMOS transistor 13 is only less than or equal to 5V.
In one embodiment, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, the dummy gate 11 surrounds the periphery of the IGBT emitter 12, and the IGBT gate 10 surrounds the periphery of the dummy gate 11.
In one embodiment, the substrate 101 includes a first side and a second side opposite to each other, the IGBT emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, and the IGBT collector is disposed on the second side of the substrate 101, or/and the IGBT device further includes a field stop layer disposed in the substrate 101 and disposed adjacent to the IGBT collector.
As described above, the IGBT device and the method of manufacturing the same of the present invention have the following advantageous effects:
when the IGBT device is turned on, the threshold voltage is applied to the IGBT gate 10, and the threshold voltage is simultaneously applied to the gate of the NMOS tube 13 to enable the NMOS tube 13 to be turned on, so that the IGBT gate 10 is connected with the dummy gate 11, and a channel is formed below the dummy gate 11 to reduce the conduction loss of the IGBT device. When the IGBT device is turned off, the current of the IGBT emitter 12 decreases, and there is a voltage change in the inductance 15 between the NPN triode 14 and the IGBT emitter 12, so that the NPN triode 14 is in an amplified state and turned on, so that the dummy gate 11 is connected to the IGBT emitter 12, thereby reducing the turn-off loss of the IGBT device. According to the invention, through controlling the change of the potential of the dummy gate 11 in different working states of the device, the heating of the device can be effectively improved, the power density is increased, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.
The NMOS tube 13 and the NPN triode 14 are arranged among the IGBT grid electrode 10, the dummy grid electrode 11 and the IGBT emitter electrode 12, the area of the device is not required to be occupied additionally, the turn-off loss and the turn-on loss of the device can be reduced simultaneously under the condition of smaller volume, the manufacturing process of the NMOS tube is compatible with the conventional manufacturing process of the IGBT device, additional manufacturing equipment is not required to be added, and the manufacturing cost of the device can be effectively controlled.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (14)
1. An IGBT device, the IGBT device comprising:
a substrate, on which an IGBT emitter, an IGBT gate and an IGBT collector of the IGBT device are formed;
the dummy grid is arranged between the IGBT grid and the IGBT emitter;
the NMOS tube is arranged on the substrate and between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the NMOS tube is electrically connected with the dummy grid electrode;
the NPN triode is arranged on the substrate, between the dummy grid electrode and the IGBT emitter electrode, the collector electrode of the NPN triode is electrically connected with the dummy grid electrode, the emitter electrode of the NPN triode is electrically connected with the IGBT emitter electrode, and the base electrode of the NPN triode is electrically connected with the IGBT emitter electrode through an inductor.
2. The IGBT device of claim 1 wherein: when the IGBT device is conducted, the IGBT gate electrode applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate electrode of the NMOS tube to conduct the NMOS tube, so that the IGBT gate electrode is connected with the dummy gate electrode, and a channel is formed below the dummy gate electrode to reduce the conduction loss of the IGBT device.
3. The IGBT device of claim 1 wherein: when the IGBT device is turned off, the current of the IGBT emitter is reduced, and the inductance between the NPN triode and the IGBT emitter has voltage change, so that the NPN triode is in an amplified state and is turned on, the dummy gate is connected with the IGBT emitter, and the turn-off loss of the IGBT device is reduced.
4. The IGBT device of claim 1 wherein: the threshold voltage of the NMOS tube is smaller than or equal to that of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and that of the NMOS tube is smaller than or equal to 5V.
5. The IGBT device of claim 1 wherein: the IGBT grid and the dummy grid are arranged in a ring shape, the dummy grid surrounds the periphery of the IGBT emitter, and the IGBT grid surrounds the periphery of the dummy grid.
6. The IGBT device of claim 1 wherein: the substrate comprises a first surface and a second surface which are opposite, the IGBT emitter and the IGBT grid are arranged on the first surface of the substrate, the IGBT collector is arranged on the second surface of the substrate, or/and the IGBT device further comprises a field stop layer which is arranged in the substrate and is close to the IGBT collector.
7. The IGBT device of claim 1 wherein: the inductance value of the inductor is 10 nH-20 nH.
8. The preparation method of the IGBT device is characterized by comprising the following steps of:
providing a substrate, and forming an IGBT emitter, an IGBT gate, an IGBT collector and a dummy gate of an IGBT device on the substrate, wherein the dummy gate is arranged between the IGBT gate and the IGBT emitter;
an NMOS tube is arranged on the substrate, the NMOS tube is arranged between the IGBT grid electrode and the dummy grid electrode, the source electrode and the grid electrode of the NMOS tube are electrically connected with the IGBT grid electrode, and the drain electrode of the NMOS tube is electrically connected with the dummy grid electrode;
and an NPN triode is arranged on the substrate, the NPN triode is arranged between the dummy grid electrode and the IGBT emitter electrode, the collector electrode of the NPN triode is electrically connected with the dummy grid electrode, the emitter electrode of the NPN triode is electrically connected with the IGBT emitter electrode, and the base electrode of the NPN triode is electrically connected with the IGBT emitter electrode through an inductor.
9. The method for manufacturing the IGBT device according to claim 8, wherein: the NMOS transistor and the NPN triode are arranged on the substrate, and the method comprises the following steps:
forming a P well and an N well in the substrate through an ion implantation process;
forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate and a gate of an NMOS tube through patterning;
forming a source electrode and a drain electrode of an NMOS tube in the P well through an ion implantation process, and forming a base electrode and an emitter electrode of an NPN triode in the N well;
forming an insulating layer on the substrate, forming a contact hole in the insulating layer, forming a metal layer on the contact hole and the insulating layer, forming a wiring layer through patterning, enabling a source electrode and a grid electrode of the NMOS tube to be electrically connected with the IGBT grid electrode, enabling a drain electrode to be electrically connected with the dummy grid electrode, enabling a collector electrode of the NPN triode to be electrically connected with the dummy grid electrode, enabling an emitter electrode to be electrically connected with the IGBT emitter electrode, and enabling a base electrode to be connected with a contact point.
10. The method for manufacturing the IGBT device according to claim 9, characterized in that: the method also comprises the steps of: and an inductor is connected between a contact point of the base electrode of the NPN triode and the IGBT emitter through an external pin, and the inductance value of the inductor is 10 nH-20 nH.
11. The method for manufacturing the IGBT device according to claim 10, wherein: when the IGBT device is conducted, the IGBT gate electrode applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate electrode of the NMOS tube to conduct the NMOS tube, so that the IGBT gate electrode is connected with the dummy gate electrode, and a channel is formed below the dummy gate electrode to reduce the conduction loss of the IGBT device; when the IGBT device is turned off, the current of the IGBT emitter is reduced, and the inductance between the NPN triode and the IGBT emitter has voltage change, so that the NPN triode is in an amplified state and is turned on, the dummy gate is connected with the IGBT emitter, and the turn-off loss of the IGBT device is reduced.
12. The method for manufacturing the IGBT device according to claim 8, wherein: the threshold voltage of the NMOS tube is smaller than or equal to that of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and that of the NMOS tube is smaller than or equal to 5V.
13. The method for manufacturing the IGBT device according to claim 8, wherein: the IGBT grid and the dummy grid are arranged in a ring shape, the dummy grid surrounds the periphery of the IGBT emitter, and the IGBT grid surrounds the periphery of the dummy grid.
14. The method for manufacturing the IGBT device according to claim 8, wherein: the substrate comprises a first surface and a second surface which are opposite, the IGBT emitter and the IGBT grid are arranged on the first surface of the substrate, the IGBT collector is arranged on the second surface of the substrate, or/and the IGBT device further comprises a field stop layer which is arranged in the substrate and is close to the IGBT collector.
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Denomination of invention: IGBT devices and their preparation methods Effective date of registration: 20231228 Granted publication date: 20230613 Pledgee: Wuding Road Sub branch of Bank of Shanghai Co.,Ltd. Pledgor: Shanghai Gongcheng Semiconductor Technology Co.,Ltd. Registration number: Y2023980075345 |