CN113921603B - Power semiconductor device - Google Patents
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- CN113921603B CN113921603B CN202010658683.5A CN202010658683A CN113921603B CN 113921603 B CN113921603 B CN 113921603B CN 202010658683 A CN202010658683 A CN 202010658683A CN 113921603 B CN113921603 B CN 113921603B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention provides a power semiconductor device, which comprises an active region, a terminal region surrounding the active region and a transition region positioned between the active region and the terminal region, wherein the active region is provided with a first semiconductor device, the transition region is provided with a second semiconductor device, a source electrode of the first semiconductor device and a conductive layer in a second groove are electrically connected with an emitter electrode, the conductive layer in the first groove and a conductive layer in a third groove are electrically connected with a grid electrode, a source electrode of the second semiconductor device, the conductive layer in the second groove and a well region between the second groove and the third groove are electrically connected with an emitter electrode, and the conductive layer in the first groove and the conductive layer in the third groove are electrically connected with the grid electrode. The invention can effectively improve the hole concentration stored in the front of the device when the device is turned on, reduce the conduction voltage drop and the conduction loss, quickly release holes when the device is turned off, reduce the turn-off loss, improve the latch-up resistance of the device and improve the reliability of the device.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a power semiconductor device.
Background
The power device is used as a key switching device for controlling strong current by weak current, and is widely applied to the fields of industry, household appliances, electric locomotives, electric automobiles and the like. The development direction of the power device is to reduce the power loss of the power device under the condition of ensuring the normal switching of the device, which requires the reduction of the on-voltage of the device and the small switching loss.
IGBT (Insulated Gate Bipolar Transistor) the insulated gate bipolar transistor is a compound full-control voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), and has the advantages of high input impedance of MOSFET and low conduction voltage drop of GTR. The GTR saturation voltage is reduced, the current density is high, but the driving current is high; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current density. The IGBT combines the advantages of the two devices, and has small driving power and reduced saturation voltage. Therefore, the application of the semiconductor device is also becoming wider and wider, and the semiconductor device is an important power semiconductor device.
As shown in fig. 1, a schematic structural diagram of an IGBT device, and as shown in fig. 1, the operating principle of the IGBT device is as follows: the Collector (Collector) 106 is pressurized with positive pressure, the Gate (Gate) is pressurized with positive pressure, a channel is formed on the side wall of the Trench Gate (Trench) 103, which is in contact with the P-type well region (Pbody) 102, the electron current starts from the Emitter (Emitter), passes through the metal layer 104 and the n+ type source region 105, then passes through the channel, reaches the N-type drift region 101, then, a part of electrons are recombined with holes injected by the Collector (Collector) 106, and the other part of electrons reach the Collector (Collector) 106 to form a current, and the device is turned on. When negative voltage is applied to the Gate (Gate), the side wall channel of the Trench Gate (Trench) 103 is closed, and no current is conducted, so that the device is turned off.
The power loss of the traditional IGBT device is high, and latch-up is easy to occur, so that the power consumption and the reliability of the IGBT device are required to be improved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a power semiconductor device for solving the problems of the prior art that the power loss of the power semiconductor device is high and latch-up is easy to occur.
To achieve the above and other related objects, the present invention provides a power semiconductor device including an active region, a termination region surrounding the active region, and a transition region between the active region and the termination region, the active region being provided with a first semiconductor device, the transition region being provided with a second semiconductor device; the first semiconductor device includes: a substrate of a first conductivity type comprising opposed first and second major faces; a well region of a second conductivity type provided on the first main surface of the substrate; the groove parts are arranged on the first main surface of the substrate and penetrate through the well region into the substrate, the groove parts comprise at least 3 groove parts which are arranged at intervals, the first groove parts and the third groove parts are configured to sandwich the second groove parts, the inner wall of each groove part is covered with an insulating layer, and the insulating layer is filled with a conductive layer; a source electrode of a first conductivity type disposed in the well region and located on a side surface of the first groove portion; a collector of a second conductivity type disposed on a second major surface of the substrate; wherein the source electrode and the conductive layer in the second groove part are electrically connected with the emitter electrode, and the conductive layer in the first groove part and the conductive layer in the third groove part are electrically connected with the grid electrode; the second semiconductor device includes: a substrate of a first conductivity type comprising opposed first and second major faces; a well region of a second conductivity type provided on the first main surface of the substrate; the groove parts are arranged on the first main surface of the substrate and penetrate through the well region into the substrate, the groove parts comprise at least 3 groove parts which are arranged at intervals, the first groove parts and the third groove parts are configured to sandwich the second groove parts, the inner wall of each groove part is covered with an insulating layer, and the insulating layer is filled with a conductive layer; a source electrode of a first conductivity type disposed in the well region and located on a side surface of the first groove portion; a collector of a second conductivity type disposed on a second major surface of the substrate; the source electrode, the conductive layer in the second groove part and the well region between the second groove part and the third groove part are electrically connected with the emitter electrode, and the conductive layer in the first groove part and the conductive layer in the third groove part are electrically connected with the grid electrode.
Optionally, the power semiconductor device further includes a field stop layer of the first conductivity type disposed on the second main surface of the substrate and between the collector and the substrate.
Alternatively, the source of the first conductivity type is provided only on both sides of the first groove portion, and the source of the first conductivity type is not provided between the second groove portion and the third groove portion.
Optionally, the substrate surface of the first semiconductor device is covered with an isolation layer, the isolation layer and the substrate are provided with a contact hole penetrating through the source electrode and extending to the well region, a metal layer is formed on the isolation layer surface and in the contact hole, and the source electrode is electrically connected with the emitter electrode through the metal layer.
Optionally, the substrate surface of the second semiconductor device is covered with an isolation layer, the isolation layer and the substrate are provided with a first contact hole penetrating through the source electrode and extending to the well region, and a second contact hole located between the second groove portion and the third groove portion and penetrating through to the well region, a metal layer is formed in the isolation layer surface, the first contact hole and the second contact hole, and the source electrode and the well region located between the second groove portion and the third groove portion are electrically connected with an emitter through the metal layer.
Optionally, the conductive layer in the first groove of the first semiconductor device is connected with the grid electrode and is used for realizing the conduction and switching functions of the device; the conducting layer in the third groove part of the first semiconductor device is connected with the grid electrode and is used for adjusting the grid electrode-emitter electrode capacitance and the grid electrode-collector electrode capacitance so as to improve the switching speed of the device; and the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, so that when the power semiconductor device is conducted, the concentration of holes stored in the front surface of the power semiconductor device is increased, and the conduction loss is reduced.
Optionally, a well region between the second groove part and the third groove part of the second semiconductor device is electrically connected with an emitter, so that a hole release channel of the power semiconductor device is provided when the power semiconductor device is turned off, the turn-off loss is reduced, and the latch-up resistance of the power semiconductor device is improved.
Optionally, the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type.
Optionally, the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type.
As described above, the power semiconductor device of the present invention has the following advantageous effects:
according to the invention, through novel groove and connection design, the power semiconductor device is optimized for different areas of the semiconductor device (such as IGBT), so that the power loss of the device can be effectively reduced, and the reliability of the device is improved.
The conducting layer in the first groove part of the first semiconductor device is connected with the grid electrode, so that the conducting and switching functions of the device can be realized; the conducting layer in the third groove part of the first semiconductor device is connected with the grid electrode, so that the grid electrode-emitter electrode capacitance and the grid electrode-collector electrode capacitance can be adjusted, and the switching speed of the device is improved; the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, so that when the power semiconductor device is conducted, the concentration of holes stored in the front surface of the power semiconductor device can be increased, and the conduction loss can be reduced.
According to the invention, aiming at the higher positive stored holes, the second semiconductor device is added in the transition region between the active region and the terminal region, the positive hole concentration of the second semiconductor device is lower, the well region between the second groove part and the third groove part of the second semiconductor device is electrically connected with the emitter, more hole release channels can be provided, holes can be quickly released when the device is turned off, the turn-off loss of the device is reduced, the latch-up resistance of the device is improved, and the reliability of the device is improved.
Drawings
Fig. 1 shows a schematic structure of an IGBT according to the prior art.
Fig. 2 is a schematic plan view of a power semiconductor device according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a first semiconductor device of a power semiconductor apparatus according to an embodiment of the present invention.
Fig. 4 is a schematic structural view of a second semiconductor device of the power semiconductor apparatus according to the embodiment of the present invention.
Fig. 5 is a graph showing the relationship between the device depth and the hole concentration of the first semiconductor device (curve a) and the second semiconductor device (curve B) according to the embodiment of the present invention.
Description of element reference numerals
101 n-type drift region
102 P-type well region
103. Trench gate
104. Metal layer
105 N+ source region
106. Collector electrode
20. Active region
21. Transition zone
22. Termination region
23. Groove(s)
201. Substrate
202. Well region
203. Conductive layer
204. Insulating layer
205. Source electrode
206. Field stop layer
207. Collector electrode
208. Metal layer
209. First contact hole
210. Second contact hole
301. A first groove part
302. A second groove part
303. Third groove part
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 2 to 4, the present embodiment provides a power semiconductor device for solving the problems of the prior art that the power semiconductor device has high power loss and is prone to latch-up.
As shown in fig. 2, the power semiconductor device includes an active region 20, a termination region 22 surrounding the active region 20, and a transition region 21 located between the active region 20 and the termination region 22, as shown in fig. 2, the power semiconductor device may be configured as a rectangle to improve space utilization of a device, a central region of the power semiconductor device is the active region 20, a peripheral region is the termination region 22, the termination region 22 surrounds the active region 20 in a rectangular ring shape, and a transition region 21 is located between the active region 20 and the termination region 22, and the transition region 21 may be located at two ends of the extending direction of the trench 23, as shown by a dashed box in fig. 2.
As shown in fig. 3, the active region 20 is provided with a first semiconductor device including a first conductive-type substrate 201, a second conductive-type well region 202, a trench portion, a first conductive-type source 205, and a second conductive-type collector 207. In order to improve the compressive capacity of the power semiconductor device, the power semiconductor device further includes a field stop layer 206 of the first conductivity type disposed on the second main surface of the substrate 201 and located between the collector 207 and the substrate 201, and the doping ions of the field stop layer 206 may be hydrogen ions or the like.
The first conductivity type substrate 201 includes opposite first and second major faces. The substrate 201 may be a semiconductor substrate such as a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, etc., and is not limited to the examples listed herein. The substrate 201 may be N-doped or P-doped, in this embodiment, the substrate 201 is an N-doped silicon substrate, the doped ions may be phosphorus, etc., and in other embodiments, the substrate 201 may be P-doped, for example, the doped ions may be boron, etc., which may be selected according to the actual requirements of the device.
The well region 202 of the second conductivity type is disposed on the first main surface of the substrate 201. In this embodiment, the well region 202 of the second conductivity type is of a P-type conductivity, and the doping ions thereof may be boron or the like.
The groove is disposed on the first main surface of the substrate 201, penetrates the well region 202 into the substrate 201, and includes at least 3 grooves arranged at intervals, the first groove 301 and the third groove 303 are configured to sandwich the second groove 302, and the first groove 301, the second groove 302 and the third groove 303 may be arranged in parallel, as an example. The inner wall of each groove is covered with an insulating layer 204, and the insulating layer 204 is filled with a conductive layer 203. For example, the insulating layer 204 may be a silicon dioxide layer or a high-k dielectric layer, and the conductive layer 203 may be a conductive material such as polysilicon or metal. The present invention is not limited to the arrangement of the first groove 301 and the third groove 303 with the second groove 302 interposed therebetween, but the number of the first groove 301, the second groove 302, and the third groove is not limited to this, and the arrangement may be the first groove 301, the second groove 302, and the third groove 303, or may be, for example, the first groove 301, the second groove 302, and the third groove 303, the first groove 301, the second groove 302, the third groove 303, and the third groove 303 may be used, for example, or the third groove 303, the second groove 302, the first groove 301, the second groove 302, the third groove 303, and the like may be used, for example, and the present invention is not limited to the examples described herein.
The source 205 of the first conductivity type is disposed in the well 202 and is located at a side of the first trench 301. In this embodiment, the source 205 is of N-type conductivity, and the doping ions may be phosphorus or the like. Further, the first conductive type source electrode 205 is provided only on both sides of the first groove 301, and the first conductive type source electrode 205 is not provided between the second groove 302 and the third groove 303.
The collector 207 of the second conductivity type is provided on the second main surface of the substrate 201. In this embodiment, the collector 207 is of P-type conductivity, and the doping ions may be boron or the like.
As shown in fig. 3, the source electrode 205 and the conductive layer 203 in the second groove 302 are electrically connected to the emitter electrode, and the conductive layer 203 in the first groove 301 and the conductive layer 203 in the third groove 303 are electrically connected to the gate electrode. As an example, the surface of the substrate 201 of the first semiconductor device is covered with an isolation layer, the isolation layer and the substrate 201 have a contact hole extending through the source electrode 205 to the well region 202 therein, a metal layer 208 is formed on the isolation layer surface and in the contact hole 209, and the source electrode 205 is electrically connected to the emitter electrode through the metal layer 208. The conductive layer in the first groove 301 of the first semiconductor device is connected with the gate, so as to realize the conduction and switching functions of the device; the conductive layer in the third groove 303 of the first semiconductor device is connected with the grid electrode and used for adjusting the capacitance of the grid electrode-emitter electrode and the capacitance of the grid electrode-collector electrode, so that the switching speed of the device is improved; the well region between the second groove 302 and the third groove 303 of the first semiconductor device is isolated from the emitter, so as to increase the hole concentration stored in the front surface of the power semiconductor device and reduce the conduction loss when the power semiconductor device is turned on. For the first semiconductor device, the first conductivity type is selected as an N-type conductivity, and the second conductivity type is selected as a P-type conductivity. However, in other embodiments, the first conductivity type may be P-type conductivity and the second conductivity type may be N-type conductivity.
As shown in fig. 4, the transition region 21 is provided with a second semiconductor device including a first conductive type substrate 201, a second conductive type well region 202, a trench portion, a first conductive type source electrode 205, and a second conductive type collector electrode 207. In order to improve the compressive capacity of the power semiconductor device, the power semiconductor device further includes a field stop layer 206 of the first conductivity type disposed on the second main surface of the substrate 201 and located between the collector 207 and the substrate 201, and the doping ions of the field stop layer 206 may be hydrogen ions or the like.
The first conductivity type substrate 201 includes opposite first and second major faces. The well region 202 of the second conductivity type is disposed on the first major surface of the substrate. In this embodiment, the well region 202 of the second conductivity type is of a P-type conductivity, and the doping ions thereof may be boron or the like. The second semiconductor device and the first semiconductor device are formed on the same wafer, and the substrate and the well region 202 of the second semiconductor device and the substrate and the well region 202 of the first semiconductor device are the same.
The groove portion is disposed on the first main surface of the substrate, penetrates through the well region 202 into the substrate, and includes at least 3 groove portions arranged at intervals, the first groove portion 301 and the third groove portion 303 are configured to sandwich the second groove portion 302, and as an example, the first groove portion 301, the second groove portion 302 and the third groove portion 303 may be arranged in parallel. The inner wall of each groove is covered with an insulating layer 204, and the insulating layer 204 is filled with a conductive layer 203. For example, the insulating layer 204 may be a silicon dioxide layer or a high-k dielectric layer, and the conductive layer 203 may be a conductive material such as polysilicon or metal. The present invention is not limited to the arrangement of the first groove 301 and the third groove 303 with the second groove 302 interposed therebetween, but the number of the first groove 301, the second groove 302, and the third groove is not limited to this, and the arrangement may be the first groove 301, the second groove 302, and the third groove 303, or may be, for example, the first groove 301, the second groove 302, and the third groove 303, the first groove 301, the second groove 302, the third groove 303, and the third groove 303 may be used, for example, or the third groove 303, the second groove 302, the first groove 301, the second groove 302, the third groove 303, and the like may be used, for example, and the present invention is not limited to the examples described herein.
The source 205 of the first conductivity type is disposed in the well 202 and is located at a side of the first trench 301. In this embodiment, the source 205 is of N-type conductivity, and the doping ions may be phosphorus or the like. Further, the first conductive type source electrode 205 is provided only on both sides of the first groove 301, and the first conductive type source electrode 205 is not provided between the second groove 302 and the third groove 303.
The collector 207 of the second conductivity type is provided on the second main face of the substrate. In this embodiment, the collector 207 is of P-type conductivity, and the doping ions may be boron or the like.
As shown in fig. 4, the source electrode 205, the conductive layer 203 in the second trench 302, and the well 202 between the second trench 302 and the third trench 303 are electrically connected to the emitter electrode, and the conductive layer 203 in the first trench 301 and the conductive layer 203 in the third trench 303 are electrically connected to the gate electrode. As an example, the substrate surface of the second semiconductor device is covered with an isolation layer, the isolation layer and the substrate have therein a first contact hole 209 penetrating the source electrode 205 and extending to the well region 202, and a second contact hole 210 located between the second trench portion 302 and the third trench portion 303 and penetrating to the well region 202, a metal layer 208 is formed in the isolation layer surface, the first contact hole 209, and the second contact hole 210, and the source electrode 205 and the well region 202 located between the second trench portion 302 and the third trench portion 303 are electrically connected to an emitter through the metal layer 208. The well region 202 between the second groove 302 and the third groove 303 of the second semiconductor device is electrically connected with an emitter, so as to provide a hole release channel of the power semiconductor device when the power semiconductor device is turned off, reduce turn-off loss, and improve the latch-up resistance of the power semiconductor device.
For the second semiconductor device, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. However, in other embodiments, the first conductivity type may be P-type conductivity and the second conductivity type may be N-type conductivity.
Fig. 5 is a graph showing the relationship between the device depth and the hole concentration of the first semiconductor device (curve a) and the second semiconductor device (curve B) according to the present invention, wherein the first semiconductor device in the active region 20 can effectively increase the hole concentration stored in the front surface of the device, thereby reducing the device turn-on voltage drop (Vcesat) and the turn-on loss. The higher hole concentration stored in the front surface needs to be released quickly when the device is turned off, so that a second semiconductor device is added at the transition part between the edge of the active region 20 and the terminal region 22, as shown in fig. 5, the front surface hole concentration of the second semiconductor device is lower, the second contact hole 210210 of the well region 202 between the second groove part 302 and the third groove part 303 of the second semiconductor device can provide more hole release channels, the holes can be released quickly when the device is turned off, the turn-off loss of the device is reduced, the latch-up resistance of the device is improved, and the reliability of the device is improved.
As described above, the power semiconductor device of the present invention has the following advantageous effects:
according to the invention, through novel groove and connection design, the power semiconductor device (such as IGBT) is optimized for different areas of the semiconductor device, so that the power loss of the device can be effectively reduced, and the reliability of the device is improved.
The conducting layer in the first groove part of the first semiconductor device is connected with the grid electrode, so that the conducting and switching functions of the device can be realized; the conducting layer in the third groove part of the first semiconductor device is connected with the grid electrode, so that the grid electrode-emitter electrode capacitance and the grid electrode-collector electrode capacitance can be adjusted, and the switching speed of the device is improved; the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, so that when the power semiconductor device is conducted, the concentration of holes stored in the front surface of the power semiconductor device can be increased, and the conduction loss can be reduced. Aiming at the higher positive stored holes, a second semiconductor device is added in a transition region 21 between an active region 20 and a terminal region 22, the concentration of positive holes of the second semiconductor device is lower, a well region 202 between a second groove part 302 and a third groove part 303 of the second semiconductor device is electrically connected with an emitter, more hole release channels can be provided, holes can be quickly released when the device is turned off, the turn-off loss of the device is reduced, the latch-up resistance of the device is improved, and the reliability of the device is improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A power semiconductor device, characterized in that the power semiconductor device comprises an active region, a termination region surrounding the active region, and a transition region between the active region and the termination region, the active region being provided with a first semiconductor device, the transition region being provided with a second semiconductor device;
the first semiconductor device includes:
a substrate of a first conductivity type comprising opposed first and second major faces;
a well region of a second conductivity type provided on the first main surface of the substrate;
the groove parts are arranged on the first main surface of the substrate and penetrate through the well region into the substrate, the groove parts comprise at least 3 groove parts which are arranged at intervals, the first groove parts and the third groove parts are configured to sandwich the second groove parts, the inner wall of each groove part is covered with an insulating layer, and the insulating layer is filled with a conductive layer;
a source electrode of a first conductivity type disposed in the well region and located on a side surface of the first groove portion;
a collector of a second conductivity type disposed on a second major surface of the substrate;
wherein the source electrode and the conductive layer in the second groove part are electrically connected with the emitter electrode, and the conductive layer in the first groove part and the conductive layer in the third groove part are electrically connected with the grid electrode;
the second semiconductor device includes:
a substrate of a first conductivity type comprising opposed first and second major faces;
a well region of a second conductivity type provided on the first main surface of the substrate;
the groove parts are arranged on the first main surface of the substrate and penetrate through the well region into the substrate, the groove parts comprise at least 3 groove parts which are arranged at intervals, the first groove parts and the third groove parts are configured to sandwich the second groove parts, the inner wall of each groove part is covered with an insulating layer, and the insulating layer is filled with a conductive layer;
a source electrode of a first conductivity type disposed in the well region and located on a side surface of the first groove portion;
a collector of a second conductivity type disposed on a second major surface of the substrate;
the source electrode, the conductive layer in the second groove part and the well region between the second groove part and the third groove part are electrically connected with the emitter electrode, and the conductive layer in the first groove part and the conductive layer in the third groove part are electrically connected with the grid electrode.
2. The power semiconductor device according to claim 1, wherein: the power semiconductor device further includes a field stop layer of the first conductivity type disposed on the second major surface of the substrate and between the collector and the substrate.
3. The power semiconductor device according to claim 1, wherein: the first conductive type source is provided only on both sides of the first groove, and the first conductive type source is not provided between the second groove and the third groove.
4. The power semiconductor device according to claim 1, wherein: the surface of the substrate of the first semiconductor device is covered with an isolation layer, the isolation layer and the substrate are provided with contact holes penetrating through the source electrode and extending to the well region, metal layers are formed in the isolation layer surface and the contact holes, and the source electrode is electrically connected with the emitter electrode through the metal layers.
5. The power semiconductor device according to claim 1, wherein: the substrate surface of the second semiconductor device is covered with an isolation layer, a first contact hole penetrating through the source electrode and extending to the well region, and a second contact hole located between the second groove portion and the third groove portion and penetrating through to the well region are arranged in the isolation layer and the substrate, a metal layer is formed in the isolation layer surface, the first contact hole and the second contact hole, and the source electrode and the well region located between the second groove portion and the third groove portion are electrically connected with an emitter through the metal layer.
6. The power semiconductor device according to claim 1, wherein: the conducting layer in the first groove part of the first semiconductor device is connected with the grid electrode and is used for realizing the conducting and switching functions of the device; the conducting layer in the third groove part of the first semiconductor device is connected with the grid electrode and is used for adjusting the grid electrode-emitter electrode capacitance and the grid electrode-collector electrode capacitance so as to improve the switching speed of the device; and the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, so that when the power semiconductor device is conducted, the concentration of holes stored in the front surface of the power semiconductor device is increased, and the conduction loss is reduced.
7. A power semiconductor device according to claim 1 or 6, characterized in that: the well region between the second groove part and the third groove part of the second semiconductor device is electrically connected with the emitter, and is used for providing a hole release channel of the power semiconductor device when the power semiconductor device is turned off, reducing turn-off loss and improving the latch-up resistance of the power semiconductor device.
8. The power semiconductor device according to claim 1, wherein: the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type.
9. The power semiconductor device according to claim 1, wherein: the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type.
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| CN101179074A (en) * | 2006-11-10 | 2008-05-14 | 国际商业机器公司 | Integration semiconductor device and manufacturing method thereof |
| JP2015162610A (en) * | 2014-02-27 | 2015-09-07 | 株式会社東芝 | semiconductor device |
| CN206976354U (en) * | 2017-07-25 | 2018-02-06 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure of deep trench |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101179074A (en) * | 2006-11-10 | 2008-05-14 | 国际商业机器公司 | Integration semiconductor device and manufacturing method thereof |
| JP2015162610A (en) * | 2014-02-27 | 2015-09-07 | 株式会社東芝 | semiconductor device |
| CN206976354U (en) * | 2017-07-25 | 2018-02-06 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure of deep trench |
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