CN114334648B - Manufacturing process of soaking trench gate IGBT and soaking trench gate IGBT structure - Google Patents
Manufacturing process of soaking trench gate IGBT and soaking trench gate IGBT structure Download PDFInfo
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- 238000002791 soaking Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000002184 metal Substances 0.000 claims abstract description 72
- 238000002347 injection Methods 0.000 claims description 42
- 239000007924 injection Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 238000009826 distribution Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000005684 electric field Effects 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 4
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention provides a soaking trench gate IGBT structure, which comprises: an effective IGBT cell and a grid thermosensitive control unit; the effective IGBT cell is arranged as a trench gate type IGBT cell; the grid thermosensitive control unit comprises two thermistors and two diodes; one thermistor and one diode are connected in series to form a first series branch circuit for controlling the opening speed of the grid electrode, one end of the first series branch circuit is connected with the trench grid, and the other end of the first series branch circuit is connected with the grid electrode metal; the other thermistor and the other diode are reversely connected in series to form a second series branch circuit for controlling the turn-off speed of the grid electrode, one end of the second series branch circuit is connected with the trench grid, and the other end of the second series branch circuit is connected with the grid electrode metal. The invention realizes that the single cell automatically adjusts the switching speed according to the self temperature through the groove gate and the thermosensitive gate resistor which are independently arranged, so that the cell with high temperature reduces the loss, thereby achieving the purpose of reducing the junction temperature of the cell. Thermal equalization is achieved for the entire IGBT chip.
Description
Technical Field
The invention relates to the field of semiconductor power devices, in particular to a manufacturing process of a soaking trench gate IGBT and a soaking trench gate IGBT structure.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic device compounded by a MOS field effect transistor and a bipolar transistor; the power transistor integrates the advantages of two devices, has the advantages of a voltage control switch of a MOSFET, high working frequency and simple driving control circuit, has the advantages of reduced on-voltage of the power transistor, bipolar conduction, large on-state current and small loss, and is widely applied to various fields of national economy such as energy, traffic, household appliances, aerospace and the like.
The traditional trench gate IGBT has the defects that the cell current is uneven, the cell temperature in a local area continuously rises, and the avalanche effect causes irreversible damage due to unreasonable device design or severe application working conditions in the use process of customers.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a manufacturing process of a soaking trench gate IGBT and a soaking trench gate IGBT structure, which improve cell current distribution in the working state of an IGBT chip, realize heat balance for the whole IGBT chip, reduce failure risk caused by chip heat concentration, and further improve the reliability and stability of a device. In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention is as follows:
In a first aspect, an embodiment of the present invention provides a process for manufacturing a soaking trench gate IGBT, including the following steps:
Step S10, an N-type substrate is provided as an N-type base region; etching is carried out through a grid groove distribution mask plate, so that each cell is provided with an independent grid groove;
Step S20, an oxide layer is manufactured in a gate groove of an N-type substrate and removed, and a gate oxide layer in the gate groove and an insulating medium layer on one side of the surface of the substrate are grown again; polysilicon is deposited on the front surface of the N-type substrate and filled in the gate groove, the polysilicon is etched through the diode distribution mask, two polysilicon strips for manufacturing the diode are left on the insulating dielectric layer of the cell, and a trench gate is formed in the gate groove; one end of the polysilicon strip facing the trench gate is connected with the trench gate;
Step S30, carrying out N-type doping on the polysilicon left in the previous step, carrying out P+ type anode injection doping on the polysilicon strips through a diode anode injection mask plate to form two diodes carried by each cell, wherein the anode of one diode D1 is contacted with a trench gate, and the cathode of the other diode D2 is contacted with the trench gate;
Step S40, two thermistors are manufactured above the insulating medium layer on one side of the front surface of the N-type substrate, wherein a thermistor Rg1 for connecting a diode D1 is a positive temperature coefficient, and a thermistor Rg2 for connecting a diode D2 is a negative temperature coefficient;
S50, performing boron implantation on the other side of the front surface of the N-type substrate through a well region implantation mask plate to form a P-type well region; the P-type well region of each cell is arranged independently and discontinuously;
step S60, phosphorus injection is carried out on the other side of the front surface of the N-type substrate by the grid oxide layer at the other side of the trench grid through the source region injection mask plate, so as to form an N+ type source region; the N+ source region of each cell is arranged independently and discontinuously;
Step S70, depositing an insulating layer on the front surface of the N-type substrate; carrying out first hole photoetching through a first contact hole mask, forming gate contact holes above one ends of the thermistors Rg1 and Rg2, and forming interconnecting holes above the other ends of the thermistors Rg1 and Rg2, above the cathode of the diode D1 and above the anode of the diode D2;
depositing metal, etching through a grid metal mask plate to form grid metal and first interconnection metal, wherein the grid metal connects one ends of the thermistors Rg1 and Rg2 in each cell, the first interconnection metal connects the other end of the thermistor Rg1 in a single cell with the cathode of the diode D1, and connects the other end of the thermistor Rg2 in the single cell with the anode of the diode D2;
Step S80, depositing an insulating layer on the front surface of the N-type substrate; performing second via hole lithography through a second contact hole mask, and forming a continuous emitter contact hole above the edge of one side of the N+ type source region, which is away from the trench gate; injecting P-type ions into the upper part of the P-type well region through the continuous emitter contact hole to form a deep P region;
Depositing metal and etching through an emitter metal mask plate to form emitter metal; the emitter metal connects the N+ type source region and the deep P region through the metal in the emitter contact hole; the emitter metal connects N+ type source regions in each cell;
And step S90, thinning the back surface of the N-type substrate, then carrying out N-type ion implantation to form an electric field stop layer, then carrying out P+ type ion implantation, carrying out thermal annealing activation to form a collector heavily doped P-type region, and then depositing metal to form collector metal.
Further, a plurality of gate trench patterns a1 for gate trench etching are distributed in an array on the gate trench distribution mask; the grid groove distribution mask plate is a positive plate.
Further, polysilicon strip patterns a2 for etching to form polysilicon strips are distributed on the diode distribution mask; the diode distribution mask is a shadow mask.
Further, diode anode injection patterns a3 are distributed on the diode anode injection mask; the anode injection mask of the diode is a positive plate.
Further, well region injection patterns a4 are distributed on the well region injection mask plate; the well region injection mask is a positive plate.
Further, n+ type source region injection patterns a5 are distributed on the source region injection mask; the source region injection mask is a positive plate.
Further, a grid contact hole pattern a6 and a first interconnection hole pattern a7 are distributed in the first contact hole layout; a grid metal pattern a8 and a first interconnection metal pattern a9 are distributed in the grid metal layout; the first contact hole mask plate is a positive plate, and the grid metal mask plate is a negative plate.
Further, emitter contact hole patterns a10 are distributed in the second contact hole mask, and emitter metal patterns a11 are distributed in the emitter metal mask.
In a second aspect, an embodiment of the invention provides a soaking trench gate IGBT structure, which comprises an N-type base region, wherein an electric field stop layer, a collector heavily doped P-type region and collector metal are sequentially arranged on the back surface of the N-type base region; it is characterized in that the method comprises the steps of,
A groove gate of each cell is arranged in the N-type base region, and a gate oxide layer is arranged between the groove gate and the N-type base region; an insulating medium layer is arranged at the top of an N-type base region at one side of the trench gate, and diodes D1 and D2 and thermistors Rg1 and Rg2 are arranged above the insulating medium layer of each cell, wherein the thermistor Rg1 is a positive temperature coefficient, and the thermistor Rg2 is a negative temperature coefficient; one end of each cell thermistor Rg1 and Rg2 is connected with gate metal; in a single unit cell, the other end of the thermistor Rg1 is connected with the cathode of the diode D1, the anode of the diode D1 is in contact connection with the trench gate, the other end of the thermistor Rg2 is connected with the anode of the diode D2, and the cathode of the diode D2 is in contact connection with the trench gate; a P-type well region and a deep P region are distributed in the N-type base region at the other side of the trench gate from bottom to top; an N+ type source region is further arranged above the P type well region and close to the gate oxide layer at the other side of the trench gate; the N+ type source region is in short circuit connection with the deep P region; the N+ source region of each cell is connected with the emitter metal.
Further, the doping concentration of the deep P region is higher than that of the P-type well region.
The technical scheme provided by the embodiment of the application has the beneficial effects that: compared with the prior art, the application improves the cell current distribution in the working state of the IGBT chip, realizes heat balance for the whole IGBT chip, reduces the failure risk caused by heat concentration of the chip, and further improves the reliability and stability of the device.
Drawings
Fig. 1 is a schematic diagram of an IGBT structure in an embodiment of the invention.
Fig. 2 is a schematic diagram of a gate trench distribution mask in an embodiment of the invention.
Fig. 3 is a schematic diagram of a diode distribution mask in an embodiment of the present invention.
Fig. 4 is a schematic diagram of a diode anode implantation mask in an embodiment of the invention.
Fig. 5 is a schematic diagram of a well region implantation mask in an embodiment of the present invention.
Fig. 6 is a schematic diagram of a source region implantation mask in an embodiment of the present invention.
Fig. 7 is a schematic diagram of a first contact hole mask and a gate metal mask in an embodiment of the present invention.
Fig. 8 is a schematic diagram of a second contact hole mask and an emitter metal mask in an embodiment of the invention.
Fig. 9 is an equivalent circuit diagram in an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The manufacturing process of the soaking trench gate IGBT provided by the embodiment of the invention comprises the following steps of:
step S10, an N-type substrate 4 is provided as an N-type base region; etching is carried out through a grid groove distribution mask plate, so that each cell is provided with an independent grid groove;
The gate trench distribution mask is shown in fig. 2, and a plurality of gate trench patterns a1 for gate trench etching are distributed on the gate trench distribution mask in an array; the grid groove distribution mask plate is a positive plate; it should be noted that, in the present application, each mask corresponds to 4 cells;
Step S20, an oxide layer is manufactured and removed in a gate groove of the N-type substrate 4, a gate oxide layer 6 in the gate groove and an insulating medium layer 7 on one side of the surface of the substrate are grown again, and the gate oxide layer 6 and the insulating medium layer 7 are generated simultaneously; polysilicon is deposited on the front surface of the N-type substrate 4 and fills the gate groove, the polysilicon is etched through the diode distribution mask, two polysilicon strips for manufacturing the diode are left on the insulating dielectric layer 7 of the cell, and a trench gate 5 is formed in the gate groove; one end of the polysilicon strip facing the trench gate 5 is connected with the trench gate 5;
The diode distribution mask is shown in fig. 3, and polysilicon strip patterns a2 for etching to form polysilicon strips are distributed on the diode distribution mask; the diode distribution mask plate is a shadow mask plate;
Step S30, carrying out N-type doping on the polysilicon (comprising the trench gate polysilicon and the polysilicon strips) left in the previous step, carrying out P+ type anode injection doping on the polysilicon strips through a diode anode injection mask plate to form two diodes carried by each cell, wherein the anode of one diode D1 is contacted with the trench gate 5, and the cathode of the other diode D2 is contacted with the trench gate 5;
The diode anode injection mask used for P+ type anode injection doping of the polysilicon strips is shown in fig. 4, and is a positive plate; diode anode injection patterns a3 are distributed on the diode anode injection mask;
Step S40, two thermistors are manufactured above the insulating medium layer 7 on one side of the front surface of the N-type substrate 4, wherein a thermistor Rg1 for connecting a diode D1 is a positive temperature coefficient, and a thermistor Rg2 for connecting a diode D2 is a negative temperature coefficient;
s50, performing boron implantation on the other side of the front surface of the N-type substrate 4 through a well region implantation mask plate to form a P-type well region 9; the P-type well region 9 of each cell is arranged independently and discontinuously;
The well region injection mask is shown in fig. 5, and well region injection patterns a4 are distributed on the well region injection mask; the well region injection mask is a positive plate;
Step S60, phosphorus injection is carried out on the other side of the front surface of the N-type substrate 4 by the gate oxide layer 6 at the other side of the trench gate 5 through a source region injection mask plate, so as to form an N+ type source region 11; the N+ type source region 11 of each cell is arranged independently and discontinuously;
The source region injection mask is shown in fig. 6, and N+ type source region injection patterns a5 are distributed on the source region injection mask; the source region injection mask is a positive plate;
Step S70, depositing an insulating layer on the front surface of the N-type substrate 4, for example, boron-phosphorus-silicon glass can be deposited as the insulating layer; carrying out first hole photoetching through a first contact hole mask, forming a grid contact hole 12 above one end of the thermistors Rg1 and Rg2, and forming an interconnection hole 13 above the other ends of the thermistors Rg1 and Rg2, above the cathode of the diode D1 and above the anode of the diode D2;
depositing metal, etching through a grid metal mask plate to form grid metal and first interconnection metal, wherein the grid metal connects one ends of the thermistors Rg1 and Rg2 in each cell, the first interconnection metal connects the other end of the thermistor Rg1 in a single cell with the cathode of the diode D1, and connects the other end of the thermistor Rg2 in the single cell with the anode of the diode D2;
Referring to fig. 7, a first contact hole mask and a gate metal mask are combined and shown in fig. 7 for simplicity, and gate contact hole patterns a6 and first interconnection hole patterns a7 are distributed in the first contact hole layout; a grid metal pattern a8 and a first interconnection metal pattern a9 are distributed in the grid metal layout; the first contact hole mask plate is a positive plate, and the grid metal mask plate is a negative plate;
Step S80, depositing an insulating layer on the front surface of the N-type substrate 4, for example, boron-phosphorus-silicon glass can be deposited as the insulating layer; performing second via hole lithography through the second contact hole mask, and forming a continuous emitter contact hole 14 above the edge of one side of the N+ type source region 11, which is away from the trench gate 5; injecting P-type ions through the continuous emitter contact hole 14 to form a deep P region 10 at the upper part of the P-type well region 9;
depositing metal and etching through an emitter metal mask plate to form emitter metal; the emitter metal connects the n+ type source region 11 and the deep P region 10 through the metal in the emitter contact hole 14; the emitter metal connects the N+ type source regions 11 in each cell;
The second contact hole mask plate and the emitter metal mask plate are shown in fig. 8, and for simplicity, the two mask plates are combined in fig. 8, an emitter contact hole pattern a10 is distributed in the second contact hole mask plate, and an emitter metal pattern a11 is distributed in the emitter metal mask plate;
step S90, thinning the back surface of the N-type substrate 4, then carrying out N-type ion implantation to form an electric field stop layer 3, then carrying out P+ type ion implantation and thermal annealing activation to form a collector heavily doped P-type region 2, and then depositing metal to form a collector metal 1.
Through the process, the soaking trench gate IGBT structure comprises an N-type base region, wherein an electric field stop layer 3, a collector heavily doped P-type region 2 and collector metal 1 are sequentially arranged on the back surface of the N-type base region;
A groove gate 5 of each cell is arranged in the N-type base region, the groove gate 5 of each cell is independently arranged, and a gate oxide layer 6 is arranged between the groove gate 5 and the N-type base region; an insulating medium layer 7 is arranged at the top of the N-type base region at one side of the trench gate 5, and diodes D1 and D2 and thermistors Rg1 and Rg2 are arranged above the insulating medium layer 7 of each cell, wherein the thermistor Rg1 is a positive temperature coefficient, and the thermistor Rg2 is a negative temperature coefficient; one end of each cell thermistor Rg1 and Rg2 is connected with gate metal; in a single unit cell, the other end of the thermistor Rg1 is connected with the cathode of the diode D1, the anode of the diode D1 is in contact connection with the trench gate 5, the other end of the thermistor Rg2 is connected with the anode of the diode D2, and the cathode of the diode D2 is in contact connection with the trench gate 5; a P-type well region 9 and a deep P region 10 are distributed in the N-type base region at the other side of the trench gate 5 from bottom to top; an N+ type source region 11 is further arranged above the P-type well region 9 and close to the gate oxide layer 6 at the other side of the trench gate 5; the N+ type source region 11 is in short circuit connection with the deep P region 10; the N+ source region 11 of each cell is connected with emitter metal;
As a preference in this embodiment, the doping concentration of the deep P region 10 is higher than that of the P-type well region 9;
in the above specific embodiment, the thermistor Rg2 is connected with the anode of the diode D2, the cathode of the diode D2 is in contact connection with the trench gate 5 in the cell, the gate turn-on speed is controlled, when the IGBT is turned on, the current flows through the thermistor Rg2 and the diode D2, the resistance value of the thermistor Rg2 decreases with the increase of temperature, thereby causing the IGBT to turn on faster, the IGBT can be turned on rapidly, the turn-on loss is obviously reduced, and the self temperature rise is reduced; the thermistor Rg1 is connected with the cathode of the diode D1, the anode of the diode D1 is connected with the trench gate 5 in the cell in a contact way, the gate turn-off speed is controlled, when the IGBT is turned off, if the turn-off speed is too high, di/dt is too high, the resistance value of the thermistor Rg1 is increased along with the increase of the temperature, and di/dt is reduced when the thermistor Rg1 is turned off, so that the Vce spike voltage is reduced, dangerous points are avoided, each IGBT cell is protected, and the risk of thermal failure of the IGBT is reduced; and since the IGBT turn-off loss is not greatly affected by the gate resistance, the turn-off loss is not increased even if the gate resistance is increased.
The overall equivalent circuit of an embodiment of the present invention can be seen in fig. 9. According to the embodiment of the invention, the switching speed of a single cell can be automatically adjusted according to the self temperature, so that the cell with high temperature reduces loss, thereby achieving the purpose of reducing the junction temperature of the cell; and heat balance is realized for the whole IGBT chip, and failure risk caused by chip heat concentration is reduced.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (8)
1. The manufacturing process of the soaking trench gate IGBT is characterized by comprising the following steps of:
Step S10, an N-type substrate (4) is provided as an N-type base region; etching is carried out through a grid groove distribution mask plate, so that each cell is provided with an independent grid groove;
Step S20, an oxide layer is manufactured in a gate groove of the N-type substrate (4) and removed, and a gate oxide layer (6) in the gate groove and an insulating medium layer (7) on one side of the surface of the substrate are grown again; polysilicon is deposited on the front surface of the N-type substrate (4) and filled in a grid groove, the polysilicon is etched through a diode distribution mask, two polysilicon strips for manufacturing a diode are left on the insulating dielectric layer (7) of a cell, and a groove grid (5) is formed in the grid groove; one end of the polysilicon strip facing the trench gate (5) is connected with the trench gate (5);
Step S30, carrying out N-type doping on the polysilicon left in the previous step, carrying out P+ type anode injection doping on the polysilicon strips through a diode anode injection mask to form two diodes carried by each cell, wherein the anode of one diode D1 is contacted with the trench gate (5), and the cathode of the other diode D2 is contacted with the trench gate (5);
step S40, two thermistors are manufactured above an insulating medium layer (7) on one side of the front surface of an N-type substrate (4), wherein a thermistor Rg1 for connecting a diode D1 is a positive temperature coefficient, and a thermistor Rg2 for connecting a diode D2 is a negative temperature coefficient;
S50, performing boron implantation on the other side of the front surface of the N-type substrate (4) through a well region implantation mask plate to form a P-type well region (9); the P-type well region (9) of each cell is arranged independently and discontinuously;
Step S60, phosphorus injection is carried out on the other side of the front surface of the N-type substrate (4) by a gate oxide layer (6) at the other side of the trench gate (5) through a source region injection mask plate, so as to form an N+ type source region (11); the N+ type source region (11) of each cell is arranged independently and discontinuously;
Step S70, depositing an insulating layer on the front surface of the N-type substrate (4); carrying out first hole photoetching through a first contact hole mask, forming a grid contact hole (12) above one end of the thermistors Rg1 and Rg2, and forming an interconnection hole (13) above the other ends of the thermistors Rg1 and Rg2, above the cathode of the diode D1 and above the anode of the diode D2;
depositing metal, etching through a grid metal mask plate to form grid metal and first interconnection metal, wherein the grid metal connects one ends of the thermistors Rg1 and Rg2 in each cell, the first interconnection metal connects the other end of the thermistor Rg1 in a single cell with the cathode of the diode D1, and connects the other end of the thermistor Rg2 in the single cell with the anode of the diode D2;
Step S80, depositing an insulating layer on the front surface of the N-type substrate (4); performing second via hole lithography through a second contact hole mask, and forming a continuous emitter contact hole (14) above the edge of one side of the N+ type source region (11) deviating from the trench gate (5); injecting P-type ions through the continuous emitter contact holes (14) to form a deep P region (10) at the upper part of the P-type well region (9);
Depositing metal and etching through an emitter metal mask plate to form emitter metal; the emitter metal connects the N+ type source region (11) and the deep P region (10) through the metal in the emitter contact hole (14); the emitter metal connects N+ type source regions (11) in each cell;
and step S90, thinning the back surface of the N-type substrate (4), then carrying out N-type ion implantation to form an electric field stop layer (3), then carrying out P+ type ion implantation and thermal annealing activation to form a collector heavily doped P-type region (2), and then depositing metal to form collector metal (1).
2. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
A plurality of grid groove patterns (a 1) for grid groove etching are distributed on the grid groove distribution mask plate in an array mode; the grid groove distribution mask plate is a positive plate.
3. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
Polysilicon strip patterns (a 2) for etching to form polysilicon strips are distributed on the diode distribution mask; the diode distribution mask is a shadow mask.
4. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
Diode anode injection patterns (a 3) are distributed on the diode anode injection mask; the anode injection mask of the diode is a positive plate.
5. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
The well region injection mask plate is distributed with a well region injection pattern (a 4); the well region injection mask is a positive plate.
6. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
An N+ type source region injection pattern (a 5) is distributed on the source region injection mask plate; the source region injection mask is a positive plate.
7. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
Grid contact hole patterns (a 6) and first interconnection hole patterns (a 7) are distributed in the first contact hole mask plate; a grid metal pattern (a 8) and a first interconnection metal pattern (a 9) are distributed in the grid metal mask plate; the first contact hole mask plate is a positive plate, and the grid metal mask plate is a negative plate.
8. The process for fabricating a soaking trench gate IGBT of claim 1, wherein,
Emitter contact hole patterns (a 10) are distributed in the second contact hole mask plate, and emitter metal patterns (a 11) are distributed in the emitter metal mask plate.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994069A (en) * | 2017-12-29 | 2018-05-04 | 安徽赛腾微电子有限公司 | A kind of IGBT device and its manufacture method |
| CN110444586A (en) * | 2019-08-21 | 2019-11-12 | 江苏中科君芯科技有限公司 | Trench gate IGBT device and preparation method with shunting zone |
| CN110491936A (en) * | 2019-08-21 | 2019-11-22 | 江苏中科君芯科技有限公司 | The carrier storage-type IGBT device of dual poly gate |
| CN110854186A (en) * | 2019-12-09 | 2020-02-28 | 安徽瑞迪微电子有限公司 | IGBT device structure and preparation method thereof |
| CN113035950A (en) * | 2019-12-25 | 2021-06-25 | 株洲中车时代半导体有限公司 | IGBT chip and preparation method thereof |
| WO2021238675A1 (en) * | 2020-05-27 | 2021-12-02 | 华为技术有限公司 | Igbt chip integrated with temperature sensor |
-
2021
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994069A (en) * | 2017-12-29 | 2018-05-04 | 安徽赛腾微电子有限公司 | A kind of IGBT device and its manufacture method |
| CN110444586A (en) * | 2019-08-21 | 2019-11-12 | 江苏中科君芯科技有限公司 | Trench gate IGBT device and preparation method with shunting zone |
| CN110491936A (en) * | 2019-08-21 | 2019-11-22 | 江苏中科君芯科技有限公司 | The carrier storage-type IGBT device of dual poly gate |
| CN110854186A (en) * | 2019-12-09 | 2020-02-28 | 安徽瑞迪微电子有限公司 | IGBT device structure and preparation method thereof |
| CN113035950A (en) * | 2019-12-25 | 2021-06-25 | 株洲中车时代半导体有限公司 | IGBT chip and preparation method thereof |
| WO2021238675A1 (en) * | 2020-05-27 | 2021-12-02 | 华为技术有限公司 | Igbt chip integrated with temperature sensor |
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