CN111463270A - IGBT structure and preparation method thereof - Google Patents
IGBT structure and preparation method thereof Download PDFInfo
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- CN111463270A CN111463270A CN202010209456.4A CN202010209456A CN111463270A CN 111463270 A CN111463270 A CN 111463270A CN 202010209456 A CN202010209456 A CN 202010209456A CN 111463270 A CN111463270 A CN 111463270A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention provides an IGBT structure and a preparation method thereof, wherein the IGBT structure comprises the following components: the substrate is provided with a plurality of strip-shaped grooves and annular grooves which are filled with polycrystalline silicon, and front metal layers are arranged on the strip-shaped grooves and the annular grooves; a deposition isolation medium layer is arranged at the upper end of the strip-shaped groove, so that the strip-shaped groove covered with the deposition isolation medium layer is not contacted with the front metal layer, and the annular groove without the deposition isolation medium layer is connected with the front metal layer; the back of the substrate is provided with an N + doped layer opposite to the annular groove. The invention can increase the circuit recovery path of the parallel FRD, form a distributed RC-IGBT structure designed by a novel back electrode of the IGBT, effectively improve the conduction voltage drop of the RC-IGBT, lead the path of the recovery current to be shortest and effectively reduce the loss.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an IGBT structure and a preparation method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a Bipolar Junction Transistor (BJT) and an insulated Gate field effect transistor (MOS), the switching speed of the IGBT is lower than that of the power MOS but far higher than that of the BJT, and the IGBT is a voltage control device, so that the IGBT has the advantages of simple control circuit, good stability and high input impedance of the MOSFET and low conduction voltage drop of GTR.
Usually, in the application of an IGBT product, an FRD (fast recovery diode) product of a corresponding specification needs to be connected in parallel as a current leakage loop when turned off, so as to protect an IGBT chip. In order to reduce the manufacturing and packaging cost of the device, the IGBT and the FRD can be integrated in the same chip, namely the RC-IGBT. Most of the existing RC-IGBTs still have a fixed back N +/P + pattern array, and the distributed structure causes the current paths of the parallel diodes to be relatively discrete and disordered, so that the path formed by the recovery current is relatively long, the loss is relatively large, as shown in FIG. 1, 12 is an N + doped region), and 13 is a P-type doped region.
Because the back of the RC-IGBT in the prior art is an N +/P + graphic array, the distributed structure can lead the current paths of the parallel diodes to be relatively discrete and disordered, so that the technical problems of longer path formed by recovery current, larger loss and the like are solved, and the distributed RC-IGBT structure designed by the novel back electrode of the IGBT and the preparation method thereof are researched and designed.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects that the current path of the parallel diode is relatively discrete and disordered, the path formed by the recovery current is relatively long and the loss is relatively large due to the fact that the back of the RC-IGBT in the prior art is an N +/P + graphic array, so that a novel distributed RC-IGBT structure designed by the back electrode of the IGBT and a preparation method thereof are provided.
The present invention provides an IGBT structure, comprising:
the IGBT device comprises a substrate, wherein a plurality of strip-shaped grooves and a plurality of annular grooves are formed in the front surface of the substrate, the annular grooves are transition regions located between a cell region and a terminal region of the front surface of the IGBT, polycrystalline silicon is filled in the strip-shaped grooves and the annular grooves, and front metal layers are arranged on the strip-shaped grooves and the annular grooves; the cell area refers to an effective area through which current can pass in a working state; the terminal region is a protection isolation structure designed at the periphery of the cell to achieve the voltage resistance of the device, and a region connected with the terminal region is called a transition region;
a deposition isolation medium layer is arranged at the upper end of the strip-shaped groove, so that the strip-shaped groove covered with the deposition isolation medium layer is not contacted with the front metal layer, and the annular groove without the deposition isolation medium layer is connected with the front metal layer; and an annular N + doped layer opposite to the annular groove is also arranged on the back surface of the substrate.
Preferably, the first and second electrodes are formed of a metal,
the front metal layer comprises a front emitting electrode metal layer and an anode metal layer of the FRD.
Preferably, the first and second electrodes are formed of a metal,
the reverse conducting IGBT structure further comprises a grid metal layer arranged on the front surface of the base body.
Preferably, the first and second electrodes are formed of a metal,
the substrate is an N-type pressure-resistant layer.
Preferably, the first and second electrodes are formed of a metal,
an N-type field stop layer and a P-type collector doped layer are arranged below the N-type voltage-resisting layer, and the N-type cathode doped layer is arranged in the P-type collector doped layer.
Preferably, the first and second electrodes are formed of a metal,
the front surface of the substrate is further provided with a P-type doped FRD main junction and a P-well of the IGBT in a concave mode, and the annular groove is formed in the positions of the P-type doped FRD main junction and the P-well of the IGBT.
Preferably, the first and second electrodes are formed of a metal,
the front surface of the substrate is also provided with a P-type doped pressure ring P-N junction in an inward concave manner.
Preferably, the first and second electrodes are formed of a metal,
and a metal isolation medium layer is also arranged on the front surface of the substrate.
The invention also provides a preparation method of the reverse conducting IGBT structure, which comprises the following steps:
firstly, forming a high-voltage terminal ring structure of an RC-IGBT device on a monocrystalline silicon wafer material according to a standard semiconductor manufacturing process;
etching the trench gate, oxidizing the gate, filling and etching back polysilicon, and doping and diffusing a well of a PN junction of the IGBT and the FRD; doping and annealing an IGBT N + emitter;
thirdly, depositing an isolation dielectric layer and etching to form a contact hole window on the front side of the RC-IGBT; in an anode structure area of the FRD device, a contact hole is etched to completely etch the anode of the PN junction and a trench gate in the area;
fourthly, sputtering and depositing front metal of the RC-IGBT, and etching to form a grid lead terminal and an emitter lead terminal of the RC-IGBT;
fifthly, carrying out ion implantation of back surface thinning and N-type field cut-off;
sixthly, photoetching a back N + region, carrying out N-type ion implantation doping, and activating by adopting laser annealing to form a diode structure; and sputtering and depositing back metal to form a leading-out terminal.
Preferably, the first and second electrodes are formed of a metal,
the diffusion drive-in trap is used for diffusing doped ions to a required depth through high-temperature long-time reaction.
The IGBT structure and the preparation method thereof provided by the invention have the following beneficial effects:
according to the invention, the annular groove is arranged on the front surface of the substrate, and the annular N + doped layer (N-type cathode doped layer) is correspondingly arranged on the back surface of the substrate, namely the surrounding groove surrounding the primitive cell CE LL is effectively designed in the transition region of the periphery and the terminal of the IGBT cellular cell, so that the anode contact of a groove type PN junction diode can be increased, the circuit recovery path of the parallel FRD is increased, the area and the current path of the original IGBT primitive cell CE LL are not occupied and influenced, the RC-IGBT structure is formed, the path of the recovery current is shortest, and the loss is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art IGBT backside structure (N +/P + pattern distributed array);
FIG. 2 is a schematic diagram of the back side structure of the IGBT structure of the invention;
FIG. 3 is a schematic diagram of the front side structure of the IGBT structure of the invention;
FIG. 4 is a partially enlarged structural view of a portion A in FIG. 3;
fig. 5 is a sectional view of the IGBT structure of the invention in the B-B direction (the sectional view is taken only at the position of the left edge).
The reference numbers in the figures denote:
1. a P-type doped pressure ring P-N junction; 2. a P-type doped FRD main junction and a P-well of the IGBT; 3. a front metal layer; 31. a front emitter metal layer; 32. an anode metal layer of FRD; 33. a gate metal layer; 4. a strip-shaped groove; 5. an N-type field stop layer; 6. a P-type collector doped layer; 7. an N-type cathode doped layer; 8. a back metal layer; 9. a substrate; 10. a metal isolation dielectric layer; 11. depositing an isolation medium layer; 12. an N + doped layer (ring shaped); 13. a P-type doped region; 14. an annular groove.
Detailed Description
As shown in fig. 2 to 5, the present invention provides a reverse conducting IGBT structure, including:
a substrate 9, wherein a plurality of strip-shaped trenches 4 and a plurality of annular trenches 14 are formed on the front surface of the substrate 9, the plurality of annular trenches are located in a transition region where a cell region on the front surface of the IGBT and a termination region are connected (for a power device, a CE LL region refers to an effective region through which current can pass in an operating state; the termination region refers to a protection and isolation structure designed on the periphery of a CE LL to achieve the withstand voltage of the device, and the region where the two regions are connected is referred to as the transition region), the plurality of strip-shaped trenches 4 and the plurality of annular trenches 14 are filled with polysilicon, and front metal layers 100 are disposed on the strip-shaped trenches 4 and the annular trenches 14;
a deposition isolation medium layer 11 is arranged at the upper end of the strip-shaped groove 4, so that the strip-shaped groove 4 covered with the deposition isolation medium layer 11 is not contacted with the front metal layer 3, and the annular groove 14 without the deposition isolation medium layer 11 is connected with part of the front metal layer 100; an annular N + doped layer 7 is also provided on the back side of the substrate 9 opposite the annular trench 13.
According to the invention, the annular groove is arranged on the front surface of the substrate, the annular N + doped layer is correspondingly arranged on the back surface of the substrate, and the metal layer, the deposition isolation dielectric layer and the correspondingly arranged N-type cathode doped layer are combined, so that the surrounding groove surrounding the primitive cell CE LL is effectively designed in the transition region of the periphery and the terminal of the IGBT cellular cell, the anode contact of a groove type PN junction diode can be increased, the circuit recovery path of the parallel FRD is increased, and the RC-IGBT structure is formed, so that the path of the recovery current is shortest, and the loss is effectively reduced.
The plurality of annular grooves are located in a transition region where a cell region on the front side of the IGBT is connected with a terminal region, and can be used for 1) utilizing the transition region, not occupying the through-flow area of the cell and correspondingly reducing the device area, and 2) being arranged on the periphery of the cell region and not influencing the current path of the IGBT in the CE LL region.
Preferably, the first and second electrodes are formed of a metal,
the front side metal layer 3 includes a front side emitter metal layer 31 of the RC-IGBT and an anode metal layer 32 of the FRD. This is a further preferred structural form of the front metal layer of the present invention, and as shown in fig. 3, the two are combined into a front metal layer capable of covering the trench, and a parallel shortest recovery current path can be formed at a position opposite to the N-type cathode doped layer, thereby greatly reducing the loss.
Preferably, the first and second electrodes are formed of a metal,
the reverse conducting IGBT structure further includes a gate metal layer 33 of the RC-IGBT provided on the front surface of the base body 9. The gate metal layer is arranged to be the extraction metal of the IGBT polysilicon filled trench gate, and the gate is adjusted and controlled to be switched on and off by an electric field in the IGBT.
Preferably, the first and second electrodes are formed of a metal,
the substrate 9 is an N-type voltage-withstanding layer of the RC-IGBT. This is a preferred configuration of the substrate of the present invention, and the N-type voltage-resistant layer is selected to be able to withstand high voltage in the IGBT.
Preferably, the first and second electrodes are formed of a metal,
an N-type field stop layer 5 of the IGBT and a P-type collector doped layer 6 of the IGBT are arranged below the N-type voltage-withstanding layer of the RC-IGBT, and the N-type cathode doped layer 7 is arranged in the P-type collector doped layer 6 of the IGBT. The N-type cathode doping layer is in the preferred hierarchical structure close to the back surface and the preferred arrangement position of the N-type cathode doping layer, so that a closed parallel FRD current recovery path can be effectively formed between the N-type cathode doping layer and the front surface groove and between the N-type cathode doping layer and the metal layer connected with the groove, the path of the recovery current is the shortest, and the loss is effectively reduced.
Preferably, the first and second electrodes are formed of a metal,
the front surface of the substrate 9 is further provided with a P-type doped FRD main junction and a P-well2 of the IGBT in a concave manner, and the strip-shaped trench 4 is opened at the positions of the P-type doped FRD main junction and the P-well2 of the IGBT. This is the preferred location for the stripe trench of the present invention to interface with the P-type doped FRD main junction and the P-well of the IGBT, allowing a closed parallel FRD current recovery path to form there, and preventing the IGBT from forming a closed path partially (by depositing the isolation dielectric layer 11).
Preferably, the front surface of the substrate 9 is further provided with a P-type doped pressure ring P-N junction 1 in an inward concave manner. Preferably, a metal isolation medium layer 10 is further disposed on the front surface of the substrate 9.
The invention also provides a preparation method of the reverse conducting IGBT structure, wherein the preparation method comprises the following steps:
firstly, forming a high-voltage terminal ring structure of an RC-IGBT device on a monocrystalline silicon wafer material according to a standard semiconductor manufacturing process;
etching the trench gate, oxidizing the gate, filling and etching back polysilicon, and doping and diffusing a well of a PN junction of the IGBT and the FRD; doping and annealing an IGBT N + emitter;
thirdly, depositing an isolation dielectric layer (such as BPSG boron phosphorus silicon glass) and etching to form a contact hole window on the front side of the RC-IGBT; in an anode structure area of an FRD device, a contact hole is etched to completely etch an anode of a PN junction and a trench gate in the area, so that the anode of the PN junction and the trench gate can be in short circuit when subsequent metal is contacted, and the structure is a typical structure of a trench diode;
fourthly, sputtering and depositing front metal of the RC-IGBT, and etching to form a grid lead terminal and an emitter lead terminal of the RC-IGBT;
fifthly, carrying out ion implantation of back surface thinning and N-type field cut-off;
sixthly, photoetching a back N + region, carrying out N-type ion implantation doping, and activating by adopting laser annealing to form a diode structure; and sputtering and depositing back metal to form a leading-out terminal.
Preferably, the first and second electrodes are formed of a metal,
the diffusion drive-in trap is used for diffusing doped ions to a required depth through high-temperature long-time reaction.
The invention provides a novel reverse conducting IGBT structure, which is characterized in that an anode contact of a groove type PN junction diode (a groove type anode can reduce the forward conduction Vf of an FRD and can reduce the PN junction capacitance) is added in a transition region of the periphery and a terminal of an IGBT unit cell, and a circuit recovery path of a parallel FRD (an N + doped region on the back and a corresponding front P type structure form the FRD together) is added;
the groove designed in the transition region and surrounding the primitive cell CE LL adopts a surrounding design;
and simultaneously forming an N + annular doped region in a region corresponding to the back surface to form the RC-IGBT structure. The path of the recovery current is minimized, and the loss is reduced
The back structure adopted by the invention belongs to the large category of lumped type, and is combined with a transition region with the front surface at the periphery of main CE LL to increase a current path of a diode anode and a corresponding annular N + region (back N + doping and corresponding front P type doping to form an FRD connected in parallel with the IGBT) on the back surface, so that the circuit path of the FRD is separated from the current path of the IGBT, the recovery current forms the shortest path, and the loss is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention. The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. An IGBT structure, characterized in that: the method comprises the following steps:
the IGBT device comprises a base body (9), wherein a plurality of strip-shaped grooves (4) and a plurality of annular grooves (14) are formed in the front surface of the base body (9), the annular grooves (14) are transition regions located between an IGBT front cell region and a terminal region, the strip-shaped grooves (4) and the annular grooves (14) are filled with polycrystalline silicon, and front metal layers (3) are arranged on the strip-shaped grooves (4) and the annular grooves (14); the cell area refers to an effective area through which current can pass in a working state; the terminal region is a protection isolation structure designed at the periphery of the cell to achieve the voltage resistance of the device, and a region connected with the terminal region is called a transition region;
a deposition isolation medium layer (11) is arranged at the upper end of the strip-shaped groove (4), so that the strip-shaped groove (4) covered with the deposition isolation medium layer (11) is not contacted with the front metal layer (3), and the annular groove (14) without the deposition isolation medium layer (11) is connected with the front metal layer (3); an annular N + doped layer (7) is also arranged on the rear side of the base body (9) opposite to the annular groove (14) region.
2. The IGBT structure of claim 1, wherein:
the front side metal layer (3) comprises a front side emitter metal layer (31) and an anode metal layer (32) of the FRD.
3. The IGBT structure of claim 1, wherein:
the reverse conducting IGBT structure further comprises a gate metal layer (33) arranged on the front surface of the substrate (9).
4. The reverse conducting IGBT structure according to claim 1, characterized in that:
the substrate (9) is an N-type pressure-resistant layer.
5. The IGBT structure of claim 4, characterized in that:
an N-type field stop layer (5) and a P-type collector doping layer (6) are arranged below the N-type voltage-resisting layer, and the N-type cathode doping layer (7) is arranged in the P-type collector doping layer (6).
6. The IGBT structure of claim 1, wherein:
the front surface of the base body (9) is further provided with a P-type doped FRD main junction and a P-well (2) of the IGBT in an inward concave mode, and the annular groove (4) is formed in the positions of the P-type doped FRD main junction and the P-well (2) of the IGBT.
7. The IGBT structure of claim 1, wherein:
the front surface of the base body (9) is also provided with a P-type doped pressure ring P-N junction (1) in an inward concave manner.
8. The IGBT structure of claim 1, wherein:
and a metal isolation medium layer (10) is also arranged on the front surface of the base body (9).
9. A method of manufacturing an IGBT structure according to any one of claims 1 to 8, characterized in that:
firstly, forming a high-voltage terminal ring structure of an RC-IGBT device on a monocrystalline silicon wafer material according to a standard semiconductor manufacturing process;
etching the trench gate, oxidizing the gate, filling and etching back polysilicon, and doping and diffusing a well of a PN junction of the IGBT and the FRD; doping and annealing an IGBT N + emitter;
thirdly, depositing an isolation dielectric layer and etching to form a contact hole window on the front side of the RC-IGBT; in an anode structure area of the FRD device, a contact hole is etched to completely etch the anode of the PN junction and a trench gate in the area;
fourthly, sputtering and depositing front metal of the RC-IGBT, and etching to form a grid lead terminal and an emitter lead terminal of the RC-IGBT;
fifthly, carrying out ion implantation of back surface thinning and N-type field cut-off;
sixthly, photoetching a back N + region, carrying out N-type ion implantation doping, and activating by adopting laser annealing to form a diode cathode structure; and sputtering and depositing back metal to form a leading-out terminal.
10. The method of claim 9, wherein:
the diffusion drive-in trap is used for diffusing doped ions to a required depth through high-temperature long-time reaction.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Application publication date: 20200728 |