CN112768447A - Reverse conducting insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Reverse conducting insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN112768447A CN112768447A CN202110029852.3A CN202110029852A CN112768447A CN 112768447 A CN112768447 A CN 112768447A CN 202110029852 A CN202110029852 A CN 202110029852A CN 112768447 A CN112768447 A CN 112768447A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
Abstract
Disclosed are a reverse conducting insulated gate bipolar transistor and a method of manufacturing the same, the reverse conducting insulated gate bipolar transistor including: the fast recovery diode comprises an insulated gate bipolar transistor area and at least one fast recovery diode area, wherein the at least one fast recovery diode area is arranged in the insulated gate bipolar transistor area, and the insulated gate bipolar transistor area surrounds the at least one fast recovery diode area; the at least one buffer area is arranged corresponding to the at least one fast recovery diode area and is respectively positioned between the at least one fast recovery diode area and the insulated gate bipolar transistor area, and the at least one buffer area respectively surrounds the at least one fast recovery diode area. The reverse conducting type insulated gate bipolar transistor reduces the influence of a fast recovery diode region on the dynamic parameters of the adjacent insulated gate bipolar transistor region, reduces the gate resistance, reduces the switching loss of the device and improves the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a reverse conducting type insulated gate bipolar transistor and a manufacturing method thereof.
Background
In the related art, an Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET). In use, an insulated gate bipolar transistor is typically used with an anti-parallel Fast Recovery Diode (FRD) to provide the device with reverse freewheeling capability. The functions of the insulated gate bipolar transistor chip and the fast recovery diode chip are integrated on one chip to form the reverse conducting insulated gate bipolar transistor. In the reverse conducting type insulated gate bipolar transistor, a plurality of fast recovery diode areas are usually directly surrounded by insulated gate bipolar transistor areas, only the trench gate structures at the edges of two sides of the plurality of fast recovery diode areas are usually connected with the peripheral gate electrode to perform charge and discharge in the insulated gate bipolar transistor areas between the plurality of fast recovery diode areas, so that the local gate resistance of the trench gate structures between the plurality of fast recovery diode areas is increased, and the gate resistance of the reverse conducting type insulated gate bipolar transistor is increased. The increase of the gate resistance of the reverse conducting insulated gate bipolar transistor leads to the increase of the turn-on time delay and turn-off time delay of the device. Particularly in the turn-off stage, the turn-off of the reverse conducting type insulated gate bipolar transistor is delayed, and the trailing current is large, so that the turn-off loss of the device is increased. When the device is at a high operating frequency, excessive turn-off loss easily causes the device temperature to rise sharply to be damaged.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a reverse conducting type insulated gate bipolar transistor and a method for manufacturing the same, which reduces gate resistance, reduces turn-on delay and turn-off delay, reduces switching loss of the reverse conducting type insulated gate bipolar transistor, and improves reliability of the reverse conducting type insulated gate bipolar transistor.
According to a first aspect of embodiments of the present invention, there is provided a reverse conducting insulated gate bipolar transistor, including:
the fast recovery diode comprises an insulated gate bipolar transistor area and at least one fast recovery diode area, wherein the at least one fast recovery diode area is arranged in the insulated gate bipolar transistor area, and the insulated gate bipolar transistor area surrounds the at least one fast recovery diode area;
the at least one buffer area is arranged corresponding to the at least one fast recovery diode area and is respectively positioned between the at least one fast recovery diode area and the insulated gate bipolar transistor area, and the at least one buffer area respectively surrounds the at least one fast recovery diode area.
Optionally, the reverse conducting type insulated gate bipolar transistor further comprises:
a termination region surrounding the IGBT region, the at least one fast recovery diode region, and the at least one buffer region.
Optionally, the igbt region, the at least one fast recovery diode region, and the at least one buffer region include:
a substrate as a drift region;
a trench structure in the substrate;
the covering medium layer is positioned above the substrate, a through hole is formed in the covering medium layer, and the through hole and the groove structure are arranged at intervals;
an electric field cut-off layer located below the substrate;
the emitter electrode is positioned on the covering dielectric layer;
and a collector electrode positioned below the electric field cut-off layer.
Optionally, the igbt region further includes:
a body region in the substrate;
the contact region and the emitter region are positioned in the body region, the top of the groove structure is positioned in the contact region, the top of the groove structure is close to the emitter region, and the groove structure is electrically connected with the grid electrode;
the emitter electrode is electrically connected with the emitter region and the contact region through the through hole;
and the collector region is positioned between the electric field stop layer and the collector electrode.
Optionally, the fast recovery diode region further comprises:
a first electrode region between the electric field cut-off layer and the collector electrode;
a second electrode region in the substrate, a top of the trench structure being in the second electrode region, the trench structure being electrically connected to the emitter electrode;
the emitter electrode is electrically connected with the second electrode region through the through hole.
Optionally, the buffer comprises: the fast recovery diode comprises a first buffer area and a second buffer area, wherein the first buffer area surrounds the corresponding fast recovery diode area, the second buffer area surrounds the first buffer area, and the insulated gate bipolar transistor area surrounds the second buffer area.
Optionally, the first buffer further includes:
the top of the groove structure is positioned in the second electrode region, and the groove structure is electrically connected with the emitter electrode;
the emitter electrode is electrically connected with the second electrode area through the through hole;
the collector region.
Optionally, the second buffer further includes:
the body region;
the contact region is positioned at the top of the groove structure, and the groove structure is electrically connected with the grid electrode;
the emitter electrode is electrically connected with the contact region through the through hole;
the collector region.
Optionally, in the igbt region, the trench structure includes: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
Optionally, in the fast recovery diode region, the trench structure includes: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
Optionally, in the first buffer region, the trench structure includes: the trench structure comprises a first trench structure extending along a first direction and a second trench structure extending along a second direction, wherein the first trench structure and the second trench structure enclose at least one first annular trench structure, the through holes comprise a first through hole extending along the first direction and a second through hole extending along the second direction, the first through hole and the second through hole enclose at least one annular through hole, and the first annular trench structure and the annular through hole are arranged at intervals.
Optionally, in the second buffer region, the trench structure includes: the insulated gate bipolar transistor structure comprises a first groove structure extending along a first direction and a second groove structure extending along a second direction, wherein the first groove structure and the second groove structure enclose at least one second annular groove structure, the groove structures in the insulated gate bipolar transistor area between the adjacent buffer areas are connected with the at least one second annular groove structure, the through holes comprise first through holes extending along the first direction and second through holes extending along the second direction, the first groove structures and the first through holes are arranged at intervals, and the second groove structures and the second through holes are arranged at intervals.
Optionally, the trench structure in the second buffer region includes a plurality of second annular trench structures, the plurality of first trench structures and the plurality of second trench structures are connected between the plurality of second annular trench structures, and the plurality of second annular trench structures are connected in parallel.
Optionally, the trench structure comprises:
a trench in the substrate, the trench extending from a first surface of the substrate to a second surface of the substrate;
the gate dielectric layer is positioned in the groove and covers the side wall and the bottom of the groove;
and the polycrystal is positioned on the gate dielectric layer and fills the groove.
Optionally, the first direction and the second direction are perpendicular.
Optionally, the junction depth of the contact region is smaller than that of the body region, and the doping concentration of the contact region is greater than that of the body region.
Optionally, the junction depth of the second electrode region is smaller than the body region, and the doping concentration of the second electrode region is larger than the body region.
Optionally, the substrate, the first electrode region, the emitter region, and the electric field stop layer are of a first doping type, the body region, the contact region, the collector region, and the second electrode region are of a second doping type, and the first doping type is opposite to the second doping type.
Optionally, the width of the trench includes 0.4um to 2um, the depth of the trench includes 2um to 10um, the pitch of the trench includes 0.6um to 10 um.
Optionally, a ratio of an area of the at least one fast recovery diode region to a total area of the igbt region, the at least one fast recovery diode region, and the at least one buffer region is less than or equal to 40%.
Optionally, the doping concentration of the second electrode regionGreater than 1E18cm-3。
According to a second aspect of the embodiments of the present invention, there is provided a method for manufacturing a reverse conducting insulated gate bipolar transistor, including:
forming an insulated gate bipolar transistor area;
forming at least one fast recovery diode region, the at least one fast recovery diode region being disposed in the insulated gate bipolar transistor region, the insulated gate bipolar transistor region surrounding the at least one fast recovery diode region;
and forming at least one buffer area, wherein the at least one buffer area is arranged corresponding to the at least one fast recovery diode area and is respectively positioned between the at least one fast recovery diode area and the insulated gate bipolar transistor area, and the at least one buffer area respectively surrounds the at least one fast recovery diode area.
Optionally, the manufacturing method further comprises:
forming a termination region surrounding the IGBT region, the at least one fast recovery diode region, and the at least one buffer region.
Optionally, the forming the igbt region, the at least one fast recovery diode region, and the at least one buffer region includes:
forming a substrate as a drift region;
forming a trench structure in the substrate;
forming a covering medium layer above the substrate, wherein a through hole is formed in the covering medium layer, and the through hole and the groove structure are arranged at intervals;
forming an electric field cut-off layer under the substrate;
forming an emitter electrode on the covering dielectric layer;
and forming a collector electrode below the electric field cut-off layer.
Optionally, the forming the igbt region further includes:
forming a body region in the substrate;
forming a contact region and an emitter region in the body region, wherein the top of the trench structure is positioned in the contact region, the top of the trench structure is close to the emitter region, and the trench structure is electrically connected with the gate electrode;
the emitter electrode is electrically connected with the emitter region and the contact region through the through hole;
a collector region is formed between the electric field stop layer and the collector electrode.
Optionally, forming the fast recovery diode region further comprises:
forming a first electrode region between the electric field cut-off layer and the collector electrode;
forming a second electrode region in the substrate, a top of the trench structure being located in the second electrode region, the trench structure being electrically connected to the emitter electrode;
the emitter electrode is electrically connected with the second electrode region through the through hole.
Optionally, the buffer comprises: the fast recovery diode comprises a first buffer area and a second buffer area, wherein the first buffer area surrounds the corresponding fast recovery diode area, the second buffer area surrounds the first buffer area, and the insulated gate bipolar transistor area surrounds the second buffer area.
Optionally, forming the first buffer further comprises:
forming the second electrode region, wherein the top of the groove structure is positioned in the second electrode region, and the groove structure is electrically connected with the emitter electrode;
the emitter electrode is electrically connected with the second electrode area through the through hole;
and forming the collector region.
Optionally, forming the second buffer further comprises:
forming the body region;
forming the contact region, wherein the top of the trench structure is positioned in the contact region, and the trench structure is electrically connected with the grid electrode;
the emitter electrode is electrically connected with the contact region through the through hole;
and forming the collector region.
Optionally, in the igbt region, the trench structure includes: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
Optionally, in the fast recovery diode region, the trench structure includes: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
Optionally, in the first buffer region, the trench structure includes: the trench structure comprises a first trench structure extending along a first direction and a second trench structure extending along a second direction, wherein the first trench structure and the second trench structure enclose at least one first annular trench structure, the through holes comprise a first through hole extending along the first direction and a second through hole extending along the second direction, the first through hole and the second through hole enclose at least one annular through hole, and the first annular trench structure and the annular through hole are arranged at intervals.
Optionally, in the second buffer region, the trench structure includes: the insulated gate bipolar transistor structure comprises a first groove structure extending along a first direction and a second groove structure extending along a second direction, wherein the first groove structure and the second groove structure enclose at least one second annular groove structure, the groove structures in the insulated gate bipolar transistor area between the adjacent buffer areas are connected with the at least one second annular groove structure, the through holes comprise first through holes extending along the first direction and second through holes extending along the second direction, the first groove structures and the first through holes are arranged at intervals, and the second groove structures and the second through holes are arranged at intervals.
Optionally, the trench structure in the second buffer region includes a plurality of second annular trench structures, the plurality of first trench structures and the plurality of second trench structures are connected between the plurality of second annular trench structures, and the plurality of second annular trench structures are connected in parallel.
Optionally, the forming a trench structure in the substrate includes:
forming a trench in the substrate, the trench extending from a first surface of the substrate to a second surface of the substrate;
forming a gate dielectric layer in the groove, wherein the gate dielectric layer covers the side wall and the bottom of the groove;
and forming a polycrystal on the gate dielectric layer, wherein the polycrystal fills the groove.
Optionally, after forming a capping dielectric layer over the substrate, the manufacturing method further includes:
and forming a photoresist masking layer on the at least one buffer area and the insulated gate bipolar transistor area, wherein the photoresist masking layer exposes the at least one fast recovery diode area, and the dynamic parameters of the at least one fast recovery diode area are improved by adopting a local carrier lifetime control process.
Optionally, the first direction is perpendicular to the second direction.
Optionally, the junction depth of the contact region is smaller than that of the body region, and the doping concentration of the contact region is greater than that of the body region.
Optionally, the junction depth of the second electrode region is smaller than the body region, and the doping concentration of the second electrode region is larger than the body region.
Optionally, the substrate, the first electrode region, the emitter region, and the electric field stop layer are of a first doping type, the body region, the contact region, the collector region, and the second electrode region are of a second doping type, and the first doping type is opposite to the second doping type.
Optionally, the width of the trench includes 0.4um to 2um, the depth of the trench includes 2um to 10um, the pitch of the trench includes 0.6um to 10 um.
Optionally, a ratio of an area of the at least one fast recovery diode region to a total area of the igbt region, the at least one fast recovery diode region, and the at least one buffer region is less than or equal to 40%.
Optionally, the doping concentration of the second electrode region is greater than 1E18cm-3。
According to the reverse conducting type insulated gate bipolar transistor and the manufacturing method thereof provided by the embodiment of the invention, the reverse conducting type insulated gate bipolar transistor comprises: the fast recovery diode area is arranged in the insulated gate bipolar transistor area, and the insulated gate bipolar transistor area surrounds the fast recovery diode area; the buffer areas and the fast recovery diode areas are correspondingly arranged and respectively located between the fast recovery diode areas and the insulated gate bipolar transistor areas, and at least one buffer area respectively surrounds at least one fast recovery diode area. The fast recovery diode region is prevented from being directly surrounded by the insulated gate bipolar transistor region, the problem that the gate resistance of the reverse conducting insulated gate bipolar transistor is increased due to the increase of the local gate resistance of the trench gate structure between the fast recovery diode regions is solved, the opening time delay and the turn-off time delay of the device are reduced, and the reliability of the device is improved.
The buffer area includes: a first buffer and a second buffer. The first buffer area surrounds the corresponding fast recovery diode area, the second buffer area surrounds the first buffer area, and the insulated gate bipolar transistor area surrounds the second buffer area. The first buffer area comprises at least one first groove structure and at least one second groove structure, and the at least one first groove structure and the at least one second groove structure enclose at least one first annular groove structure. The first annular groove structure of the first buffer area forms an isolation area, the dynamic parameters of the insulated gate bipolar transistor area close to the fast recovery diode area are prevented from being influenced when the dynamic parameters of the fast recovery diode area are improved by adopting a local carrier service life control process, the carrier service life control process can be independently carried out on at least one fast recovery diode area and the insulated gate bipolar transistor area, and the saturation voltage drop of the adjacent insulated gate bipolar transistor area is prevented from increasing along with the reduction of the carrier service life.
In the second buffer region, the trench structure includes: the first groove structure and the second groove structure enclose at least one second annular groove structure, the groove structures in the insulated gate bipolar transistor area between the adjacent buffer areas are connected with the second annular groove structure, the through holes comprise first through holes extending along the first direction and second through holes extending along the second direction, the first groove structures and the first through holes are arranged at intervals, and the second groove structures and the second through holes are arranged at intervals. In some embodiments, the second buffer region includes a plurality of second annular trench structures, the plurality of second annular trench structures are connected with the plurality of first trench structures and the plurality of second trench structures, and the plurality of second annular trench structures are connected in parallel. The second ring-shaped groove structure of the second buffer area increases grid current between a plurality of fast recovery diode areas and between the plurality of fast recovery diode areas and the terminal area, reduces grid resistance between the plurality of fast recovery diode areas and the terminal area, reduces trailing current of a device in a turn-off stage, reduces switching loss of the device, and improves reliability and service life of the device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram showing a layout of a reverse conducting type insulated gate bipolar transistor in the related art;
fig. 2 is a graph showing a relationship between a fast recovery diode region area and a gate resistance in the reverse conducting type igbt shown in fig. 1;
fig. 3 shows a layout diagram of an inverse conducting-type insulated gate bipolar transistor according to an embodiment of the present invention;
fig. 4 is a partially enlarged view showing a layout diagram of the reverse conducting-type insulated gate bipolar transistor shown in fig. 3;
FIG. 5 is a resistance network diagram showing the equivalent resistance of the gate resistance of the reverse conducting IGBT shown in FIG. 4;
fig. 6 is a graph showing a relationship between the equivalent resistance of the gate resistance of the reverse conducting insulated gate bipolar transistor shown in fig. 5 and the number of second annular trench structures;
fig. 7 shows a schematic cross-sectional view of a reverse conducting insulated gate bipolar transistor according to an embodiment of the invention;
fig. 8 to 14 are schematic cross-sectional views of the reverse conducting type insulated gate bipolar transistor according to the embodiment of the present invention at different stages of the manufacturing method.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 shows a layout diagram of a reverse conducting insulated gate bipolar transistor in the related art. As shown in fig. 1, the reverse conducting insulated gate bipolar transistor 1000 includes: an igbt region 1100, a fast recovery diode region 1210, and a fast recovery diode region 1220. The igbt region 1100 includes: a plurality of first trench gate structures 1110 extending in the Y-axis direction and a plurality of second trench gate structures 1120 extending in the X-axis direction. The igbt region 1100 surrounds the fast recovery diode region 1210 and the fast recovery diode region 1220. In the igbt region 1100, the first trench gate structure 1110 and the second trench gate structure 1120 located between the fast recovery diode region 1210 and the fast recovery diode region 1220, and the first trench gate structure 1110 located at the left and right edges of the fast recovery diode region 1210 and the fast recovery diode region 1220 constitute a trench gate structure group 1130. In the trench gate structure group 1130, the first trench gate structures 1110 located between the fast recovery diode region 1210 and the fast recovery diode region 1220 are connected in parallel between the second trench gate structures 1120, and both ends of the second trench gate structures 1120 are connected to the first trench gate structures 1110 located at both left and right edges of the fast recovery diode region 1210 and the fast recovery diode region 1220, respectively. The trench gate structure group 1130 is usually charged and discharged by connecting only the first trench gate structures 1110 located at the left and right edges of the fast recovery diode region 1210 and the fast recovery diode region 1220 with the peripheral gate, so that the gate resistance Rg of the trench gate structure group 1130 located between the fast recovery diode region 1210 and the fast recovery diode region 1220 is increased, and the gate resistance Rg of the igbt 1000 is increased. If the fast recovery diode regions 1210 and 1220 have increased widths in the X-direction, the number of first trench gate structures 1110 located between the fast recovery diode regions 1210 and 1220 increases, resulting in an increase in the gate resistance Rg of the igbt region 1100.
Fig. 2 is a graph showing a relationship between a fast recovery diode region area and a gate resistance in the reverse conducting type igbt shown in fig. 1. Fig. 2 specifically shows actual test data of the relationship between the gate resistance Rg of the reverse conducting-type igbt 1000 and the total area of the fast recovery diode region 1210 and the fast recovery diode region 1220, in which the fast recovery diode region 1210 and the fast recovery diode region 1220 increase in width in the X direction and do not change in length in the Y direction. As shown in fig. 2, the abscissa is a normalized value of the total area of the fast recovery diode region 1210 and the fast recovery diode region 1220, and the ordinate is the gate resistance Rg of the igbt 1000, and the gate resistance Rg is significantly increased as the total area of the fast recovery diode region 1210 and the fast recovery diode region 1220 is increased. Therefore, the introduction of the snapback diode region 1210 and the snapback diode region 1220 in the igbt region 1100 causes the gate resistance Rg of the igbt 1000 to increase.
The increase of the gate resistance Rg leads to a large time delay in the turn-on and turn-off stages, particularly in the turn-off stage, the voltage Vce between the collector and the emitter of the reverse conducting type insulated gate bipolar transistor 1000 rises, and after most of the insulated gate bipolar transistor cells in the reverse conducting type insulated gate bipolar transistor 1000 are turned off, the turn-off of the insulated gate bipolar transistor cells between the fast recovery diode region 1210 and the fast recovery diode region 1220 is delayed due to the fact that the local gate resistance Rg is large, so that the trailing current is still at a high level, and the turn-off loss of the device is increased. Accordingly, embodiments of the present invention provide a reverse conducting insulated gate bipolar transistor and a method for manufacturing the same, which will be described in detail below with reference to the accompanying drawings.
Fig. 3 shows a layout diagram of the reverse conducting insulated gate bipolar transistor according to the embodiment of the present invention. As shown in fig. 3, the reverse conducting type insulated gate bipolar transistor 2000 includes: an igbt region 2100, a snap-back diode region 2210, a snap-back diode region 2220, a snap-back diode region 2230, a snap-back diode region 2240, a buffer region 2310, a buffer region 2320, a buffer region 2330, a buffer region 2340, and a termination region 2400. The fast recovery diode region 2210, the fast recovery diode region 2220, the fast recovery diode region 2230, and the fast recovery diode region 2240 are disposed in the igbt region 2100, and the igbt region 2100 surrounds the fast recovery diode region 2210, the fast recovery diode region 2220, the fast recovery diode region 2230, and the fast recovery diode region 2240. The buffer areas 2310 to 2340 are disposed corresponding to the fast recovery diode areas 2210 to 2240, and the buffer areas 2310 to 2340 are respectively disposed between the fast recovery diode areas 2210 to 2240 and the igbt area 2100. The buffer areas 2310 to 2340 surround the corresponding fast recovery diode areas 2210 to 2240, respectively. The termination region 2400 surrounds the igbt region 2100, the snap-back diode regions 2210 to 2240, and the buffer regions 2310 to 2340. The ratio of the area of the fast recovery diode region 2210 to the fast recovery diode region 2240 to the total area of the igbt region 2100, the fast recovery diode region 2210 to the fast recovery diode region 2240, and the buffer region 2310 to the buffer region 2340 is 40% or less. The termination region 2400 is designed to withstand high voltages and protect the igbt region 2100, snapback diode region 2210-snapback diode region 2240, and buffer region 2310-buffer region 2340 from premature breakdown.
Fig. 4 is a partial enlarged view of the layout diagram of the reverse conducting insulated gate bipolar transistor shown in fig. 3, and particularly shows a partial enlarged view of the layout diagram of the reverse conducting insulated gate bipolar transistor in the rectangular frame 2500 shown in fig. 3. As shown in fig. 4, the igbt area 2100 includes: a plurality of first trench structures 2001 and a plurality of first via holes 2002 extending in the Y-axis direction (first direction), and a plurality of second trench structures 2003 and a plurality of second via holes 2004 extending in the X-axis direction (second direction). It is to be noted that the plurality of first through holes 2002 and the plurality of second through holes 2004 in the embodiment of the present invention are the same type of through holes, and the through holes are divided into the plurality of first through holes 2002 extending in the Y-axis direction (first direction) and the plurality of second through holes 2004 extending in the X-axis direction (second direction) for convenience of description. The first direction may be perpendicular to the second direction, or may form other angles with the second direction. A plurality of trench structures (including a first trench structure 2001 and a second trench structure 2003) and a plurality of via holes (including a first via hole 2002 and a second via hole 2004) are provided at intervals. The fast recovery diode region 2210 includes: a plurality of first trench structures 2001 and a plurality of first vias 2002. The buffer area 2310 includes: a first buffer area 2311 and a second buffer area 2312. The first buffer area 2311 surrounds the fast recovery diode area 2210, the second buffer area 2312 surrounds the first buffer area 2311, and the igbt area 2100 surrounds the second buffer area 2312. The first buffer area 2311 includes: at least one first trench structure 2001, at least one first via 2002, at least one second trench structure 2003 and at least one second via 2004, wherein the at least one first trench structure 2001 and the at least one second trench structure 2003 form at least one first annular trench structure (only a partial structure of the first annular trench structure is shown in the figure), the at least one first via 2002 and the at least one second via 2004 form at least one annular via (only a partial structure of the annular via is shown in the figure), the first annular trench structure and the annular via are arranged at intervals, and the at least one first annular trench structure and the at least one annular via surround a fast recovery diode region 2210. The second buffer area 2312 includes: at least one first trench structure 2001 and at least one second trench structure 2003, the first trench structure 2001 being spaced apart from the first through hole 2002, the second trench structure 2003 being spaced apart from the second through hole 2004. The at least one first trench structure 2001 and the at least one second trench structure 2003 enclose at least one second annular trench structure (only a part of the second annular trench structure is shown in the figure), and the at least one second annular trench structure encloses the first buffer 2311. In some embodiments, the second buffer 2312 includes a plurality of second annular trench structures, between which the plurality of first trench structures 2001 and the plurality of second trench structures 2003 are connected, the plurality of second annular trench structures being connected in parallel. It should be noted that, in the second buffer 2312, the first via 2002 and the second via 2004 are separated into a plurality of segments of vias, which may be square vias or rectangular vias, by the plurality of first trench structures 2001 and the plurality of second trench structures 2003 connected between the plurality of second annular trench structures.
The plurality of first trench structures 2001 in the igbt area 2100 between the second buffer area 2312 and the second buffer area 2332 are connected with the second ring-shaped trench structure of the second buffer area 2312 and the second ring-shaped trench structure of the second buffer area 2332. The first and second trench structures 2001 and 2003 located in the fast recovery diode region 2210 and the first buffer region 2311 are electrically connected to the emitter electrode. The first trench structure 2001 and the second trench structure 2003 located in the second buffer area 2312 and the igbt area 2100 are electrically connected to the gate electrode. The plurality of first trench structures 2001 and the plurality of second trench structures 2003 are formed in the same process step and are formed of the same material. The plurality of first through holes 2002 and the plurality of second through holes 2004 are formed in the same process step.
The first annular trench structure in the first buffer area 2311 is used for isolating the igbt area 2100 from the fast recovery diode area 2210, and the first annular trench structure is at the lowest potential during operation, so that the influence of special processes in the manufacturing process of the igbt area 2100 and the fast recovery diode area 2210 on the dynamic parameters of each other is avoided, and the influence of a carrier life control process of the fast recovery diode area 2210 on the adjacent igbt area 2100 is avoided; the second ring-shaped trench structure in the second buffer 2312 and the second ring-shaped trench structure in the second buffer 2332 are connected to the first trench structure 2001 therebetween, increasing the gate current of the portion of the igbt area 2100 between the fast recovery diode area 2210 and the fast recovery diode area 2230, and decreasing the gate resistance of the portion of the igbt area 2100.
It should be noted that, in the reverse conducting type insulated gate bipolar transistor shown in fig. 4, the first buffer 2311 includes two first annular trench structures, and the second buffer 2312 includes two second annular trench structures, while the reverse conducting type insulated gate bipolar transistor shown in fig. 4 is only an example and should not limit any embodiment of the present invention. It is easily understood that in the reverse conducting insulated gate bipolar transistor in the embodiment of the present invention, the first buffer region includes at least one first annular trench structure, and the second buffer region includes at least one second annular trench structure.
Fig. 5 is a resistance network diagram showing the equivalent resistance of the gate resistance of the reverse conducting igbt shown in fig. 4. Fig. 5 is a diagram for qualitatively analyzing the relationship between the gate resistance Rg and the number N of the second annular trench structures connected in parallel in the second buffer area 2332 in the portion of the igbt area 2100 between the snapback diode area 2210 and the snapback diode area 2230 shown in fig. 4. In fig. 5, the resistor network 510 represents the equivalent resistance of the first trench structure 2001 in the partial igbt area 2100 between the fast recovery diode area 2210 and the fast recovery diode area 2230, the resistor network 520 represents the equivalent resistance of the second ring-shaped trench structure of the second buffer area 2312 and the second ring-shaped trench structure of the second buffer area 2332 connected to the plurality of first trench structures 2001 in the partial igbt area 2100, and the resistor network between the interface 501 and the interface 502 represents the equivalent resistance of the gate resistance Rg of the partial igbt area 2100. In this embodiment, it is assumed that the number K of the first trench structures 2001 in the partial igbt area 2100 is 30, and the number N of the parallel second ring-shaped trench structures in the second buffer area 2312 and the second buffer area 2332 located on the left or right side of the partial igbt area 2100. For the sake of analysis, it is assumed that the resistances of the resistors 503 shown in fig. 5 are the same and the resistance value is 1. Fig. 6 is a graph showing the relationship between the equivalent resistance of the gate resistance Rg of the igbt area 2100 in fig. 5 and the number N of the parallel second ring-shaped trench structures in the second buffer area 2312 and the second buffer area 2332 on the left or right side of the igbt area 2100. As shown in fig. 6, the abscissa represents the number N of the second ring-shaped trench structures connected in parallel in the second buffer 2312 and the second buffer 2332 on the left or right side of the partial igbt area 2100, and the ordinate represents the equivalent resistance of the gate resistance Rg of the partial igbt area 2100. As can be seen from fig. 6, as the number N of the second annular trench structures connected in parallel increases, the resistance of the equivalent resistor of the gate resistor Rg decreases, and when N is 2, the resistance of the equivalent resistor of the gate resistor Rg decreases greatly, therefore, the number of the second annular trench structures in the second buffer area is preferably greater than or equal to 2, and increasing the number of the second annular trench structures in the second buffer area can effectively decrease the gate resistance of the igbt area located between the fast recovery diode areas, thereby effectively decreasing the turn-on delay and turn-off delay of the device.
Fig. 7 shows a schematic cross-sectional view of a reverse conducting insulated gate bipolar transistor according to an embodiment of the present invention. The cross-sectional diagram shown in fig. 7 is a cross-sectional diagram obtained along the AA' cross-section of the layout diagram of the reverse conducting-type insulated gate bipolar transistor shown in fig. 4. As shown in fig. 7, the reverse conducting type insulated gate bipolar transistor 3000 includes: an igbt region 2100, a snap-back diode region 2210, and a buffer region 2310. The buffer area 2310 includes: a first buffer area 2311 and a second buffer area 2312. The first buffer area 2311 surrounds the fast recovery diode area 2210, the second buffer area 2312 surrounds the first buffer area 2311, and the igbt area 2100 surrounds the second buffer area 2312. The igbt area 2100, the snap recovery diode area 2210, and the buffer area 2310 include: a substrate 3100; the substrate 3100 serves as a drift region. A trench structure located in the substrate 3100; a covering medium layer 3400 positioned above the substrate 3100, wherein through holes are arranged in the covering medium layer 3400, and the through holes and the groove structures are arranged at intervals; an electric field cut-off layer 3600 located below the substrate 3100; an emitter electrode 3500 on the capping dielectric layer 3400; a collector electrode 3900 located below the electric field stop layer 3600.
The igbt area 2100 further includes: body region 3310 in substrate 3100; a contact region 3330 and an emitter region 3320 located in the body region 3310, the emitter electrode 3500 being electrically connected to the emitter region 3320 and the contact region 3330 through a via hole; and a collector region 3700 located between the electric field stop layer 3600 and the collector electrode 3900. In the igbt area 2100, the top of the trench structure is located in the contact area 3330, and the top of the trench structure is close to the emitter area 3320.
The fast recovery diode region 2210 further includes: a first electrode region 3800 located between the electric field cut-off layer 3600 and the collector electrode 3900; and a second electrode region 3340 in the substrate 3100, and the emitter electrode 3500 is electrically connected to the second electrode region 3340 through a via hole. The doping impurity concentration of the second electrode region 3340 is more than 1E18cm-3. The second electrode region 3340 has a higher doping concentration to reduce the forward voltage drop VF of the fast recovery diode region 2210. The trench structure is used to adjust the area of the second electrode regions 3340.
The first buffer area 2311 further includes: a second electrode region 3340 in the substrate 3100, the emitter electrode 3500 being electrically connected to the second electrode region 3340 through a via hole; and a collector region 3700 located between the electric field stop layer 3600 and the collector electrode 3900. In the fast recovery diode region 2100 and the first buffer region 2311, the top of the trench structure is located in the second electrode region 3340. The second buffer area 2312 further includes: body region 3310 in substrate 3100; a contact region 3330 in the body region 3310, the emitter electrode 3500 being electrically connected to the contact region 3330 through a via hole; and a collector region 3700 located between the electric field stop layer 3600 and the collector electrode 3900. In the second buffer area 2312, the top of the trench structure is located in the contact area 3330.
The trench structures in the igbt region 2100, the fast recovery diode region 2210, the first buffer region 2311 and the second buffer region 2312 are formed in the same process step, and have the same constituent materials. In the igbt area 2100, the fast recovery diode area 2210, and the buffer area 2310, the trench structure includes: a trench 3210 in the substrate 3310, the trench 3210 extending from a first surface of the substrate 3100 to a second surface of the substrate 3100; a gate dielectric layer 3220 located in the trench 3210, the gate dielectric layer 3220 covering the sidewall and the bottom of the trench 3210; and a poly 3230 positioned on the gate dielectric layer 3220, wherein the poly 3230 fills the trench 3210. The width of the trench 3210 includes: 0.4um to 2um, the depth includes: 2um to 10um, the interval of slot includes: 0.6um to 10 um.
Specifically, in the igbt area 2100, the trench structure includes: and a first trench structure 2001 extending in the first direction, the via hole including a first via hole 2002 extending in the first direction, the first trench structure 2001 being spaced apart from the first via hole 2002. In the fast recovery diode region 2210, the trench structure includes: and a first trench structure 2001 extending in the first direction, the via hole including a first via hole 2002 extending in the first direction, the first trench structure 2001 being spaced apart from the first via hole 2002. It should be noted that, in the embodiment of the present invention, the number of the first trench structures and the number of the first through holes in the igbt region and the snapback diode region should not limit the present invention.
In the first buffer area 2311, the trench structure includes: the through holes comprise at least one first through hole 2002 extending along the first direction and at least one second through hole 2004 extending along the second direction, the at least one first through hole 2002 and the at least one second through hole 2004 define at least one annular through hole, and the first annular groove structures and the annular through holes are arranged at intervals. It should be noted that, in the embodiment of the present invention, the number of the first annular trench structures and the number of the annular vias of the first buffer area may be one or more, and the number of the first annular trench structures and the number of the annular vias should not limit the present invention.
In the second buffer area 2312, the trench structure includes: at least one first trench structure 2001 extending in a first direction and at least one second trench structure 2003 extending in a second direction, the via holes including at least one first via hole 2002 extending in the first direction and at least one second via hole 2004 extending in the second direction, the first trench structure 2001 being spaced apart from the first via hole 2002, the second trench structure 2003 being spaced apart from the second via hole 2004. The at least one first trench structure 2001 and the at least one second trench structure 2003 enclose at least one second annular trench structure. The first trench structure 2001 in the igbt area 2100 between the second buffer area 2312 and the second buffer area 2332 is connected to the at least one second ring-shaped trench structure. In some embodiments, in the second buffer area 2312, a plurality of second annular trench structures are included, and a plurality of first trench structures 2001 and a plurality of second trench structures 2003 are connected between the plurality of second annular trench structures, and the plurality of second annular trench structures are connected in parallel. It should be noted that, in the second buffer 2312, the first via 2002 and the second via 2004 are separated into a plurality of segments of vias, which may be square vias or rectangular vias, by the plurality of first trench structures 2001 and the plurality of second trench structures 2003 connected between the plurality of second annular trench structures. It should be noted that, in the embodiment of the present invention, the number of the second annular trench structures of the second buffer area may be one or more, and the number of the second annular trench structures should not limit the present invention in any way. It should be noted that the first direction in the embodiment of the present invention is the Y-axis direction shown in fig. 4, and the second direction is the X-axis direction shown in fig. 4.
The first and second trench structures 2001 and 2003 located in the fast recovery diode region 2210 and the first buffer region 2311 are electrically connected to the emitter electrode. The first trench structure 2001 and the second trench structure 2003 located in the second buffer area 2312 and the igbt area 2100 are electrically connected to the gate electrode.
It is noted that the substrate 3100, the first electrode regions 3800, the emitter region 3320 and the field stop layer 3600 are of a first doping type, e.g. N-type, the body region 3310, the contact region 3330, the collector region 3700 and the second electrode region 3340 are of a second doping type, e.g. P-type, the first doping type and the second doping type being opposite.
It should be noted that the junction depth of the contact region 3330 is smaller than the body region 3310, and the doping concentration of the contact region 3330 is greater than the body region 3310. The junction depth of the second electrode region 3340 is smaller than the body region 3310, and the doping concentration of the second electrode region 3340 is greater than the body region 3310.
In the igbt area 2100, the body region 3310, the emitter region 3320, the trench structures (the first trench structure 2001 and the second trench structure 2003), the substrate 3100, the electric field stop layer 3600, and the collector region 3700 constitute an igbt cell, and the igbt function of the reverse conducting igbt 3000 is realized. Emitter region 3320, body region 3310 and substrate 3100 comprise the igbt portion of igbt 3000, and body region 3310, substrate 3100 and collector region 3700 comprise the bipolar transistor portion of igbt 3000. The fast recovery diode region 2210 implements the freewheeling diode function of the reverse conducting igbt 3000. The first electrode region 3800 and the second electrode region 3340 in the fast recovery diode region 2210 constitute a fast recovery diode. When the igbt area 2100 normally operates, the fast recovery diode of the fast recovery diode area 2210 is in an off state, and when the igbt area 2100 is off, the fast recovery diode of the fast recovery diode area 2210 is in a freewheeling state.
Fig. 8 to 14 are schematic cross-sectional views of the reverse conducting type insulated gate bipolar transistor according to the embodiment of the present invention at different stages of the manufacturing method. Referring to fig. 8 to 14, the method of manufacturing the reverse conducting insulated gate bipolar transistor 3000 includes the following steps.
As shown in fig. 8, a substrate 3100 is provided, the substrate 3100 being a semiconductor substrate of a first doping type. The substrate 3100 serves as a drift region. The first doping type is, for example, N-type and the substrate 3100 is, for example, a zone-melted silicon with a crystal orientation <100 >. A voltage division ring terminal structure and an active region of a device to be processed are formed on a first surface of a substrate 3100, the active region includes an igbt region 2100, a fast recovery diode region 2210 and a buffer region 2310, and the buffer region 2310 includes a first buffer region 2311 and a second buffer region 2312. A plurality of trenches 3210 are formed in the active area in the substrate 3100 by photolithography and etching processes. A plurality of trenches 3210 extend from the first surface of the substrate 3100 to the second surface of the substrate 3100. An oxide layer of material is deposited on a first surface of the substrate 3100 by conventional semiconductor processing techniques such as Low Pressure Chemical Vapor Deposition (LPCVD) or ion enhanced chemical vapor deposition (PECVD) to form a barrier dielectric layer. Specifically, a shielding dielectric layer 3220 is formed in the plurality of trenches 3210, and the shielding dielectric layer 3220 covers sidewalls and bottoms of the plurality of trenches 3210; polysilicon material is then deposited on the shielding dielectric layer 3220 to form a poly 3230 filling the plurality of trenches 3210. The width of the plurality of trenches 3210 includes: 0.4um to 2um, the depth includes: 2um to 10um, the slot interval includes: 0.6um to 10 um. The plurality of trenches 3210, the shielding dielectric layer 3220, and the poly 3230 extending in the Y-axis direction (first direction) form a plurality of first trench structures 2001, and the plurality of trenches 3210, the shielding dielectric layer 3220, and the poly 3230 extending in the X-axis direction (second direction) form a plurality of second trench structures 2003 (not shown). It should be noted that the first direction in the embodiment of the present invention is the Y-axis direction shown in fig. 4, and the second direction is the X-axis direction shown in fig. 4.
In the igbt area 2100, the trench structure includes: a first trench structure 2001 extending in a first direction. In the fast recovery diode region 2210, the trench structure includes: a first trench structure 2001 extending in a first direction. In the first buffer area 2311, the trench structure includes: a first trench structure 2001 extending in a first direction and a second trench structure 2003 extending in a second direction, the first trench structure 2001 and the second trench structure 2003 enclosing at least one first ring-shaped trench structure. In the second buffer area 2312, the trench structure includes: a first trench structure 2001 extending in a first direction and a second trench structure 2003 extending in a second direction, the first trench structure 2001 and the second trench structure 2003 enclosing at least one second annular trench structure. In some embodiments, the second buffer region includes a plurality of second annular trench structures, between which the plurality of first trench structures 2001 and the plurality of second trench structures 2003 are connected, the plurality of second annular trench structures being connected in parallel. The first trench structure 2001 in the igbt area 2100 between the second buffer area 2312 and the second buffer area 2332 is connected to the at least one second ring-shaped trench structure. Optionally, a plurality of trenches 3210 are equally spaced in the substrate 3100. It is understood that the spacing between the plurality of grooves 3210 may also vary.
As shown in fig. 9, the first trench structure 2001 and the second trench structure 2003 are masked with a mask, and a second doping type (for example, P-type) is ion-implanted into the substrate 3100 between the first trench structure 2001 and the second trench structure 2003 in the igbt area 2100 and the second buffer area 2312, thereby forming a body region 3310. The first trench structure 2001 and the second trench structure 2003 are masked with a mask, and ion implantation of a second doping type (for example, P-type) is performed on the fast recovery diode region 2210 and the substrate 3100 between the first trench structure 2001 and the second trench structure 2003 in the first buffer region 2311, thereby forming a second electrode region 3340. The doping concentration of the second electrode region 3340 is greater than 1E18cm-3. In the igbt area 2100 and the second buffer area 2312, the tops of the first trench structure 2001 and the second trench structure 2003 are located in the body region 3310, and the body region 3310 is located between the first trench structure 2001 and the second trench structure 2003. In the fast recovery diode region 2210 and the first buffer region 2311, the tops of the first and second trench structures 2001 and 2003 are located in the second electrode region 3340, and the second electrode region 3340 is located between the first and second trench structures 2001 and 2003. The junction depth of the second electrode region 3340 is smaller than the body region 3310, and the doping concentration of the second electrode region 3340 is greater than the body region 3310.
As shown in fig. 10, the fast recovery diode region 2210 and the first buffer region 2311 are masked by a mask, and a contact region 3330 is formed by performing ion implantation of a second doping type (e.g., P-type) in the body regions 3310 of the igbt region 2100 and the second buffer region 2312. The fast recovery diode region 2210, the first buffer region 2311 and the second buffer region 2312 are masked by a mask, and ion implantation of a first doping type (e.g., N-type) is performed in the body region 3310 in the igbt region 2100 to form an emitter region 3320. The contact region 3330 has a junction depth less than that of body region 3310 and the contact region 3330 has a doping concentration greater than that of body region 3310.
As shown in fig. 11, a layer of capping dielectric layer material is formed on the first surface of the substrate 3100 by a semiconductor conventional process technique such as Low Pressure Chemical Vapor Deposition (LPCVD) or ion enhanced chemical vapor deposition (PECVD), the capping dielectric layer material is patterned by photolithography, etching, and the like to form a capping dielectric layer 3400, and a portion of the capping dielectric layer 3400 that is removed by etching forms a via hole, and the via hole and the trench structure are spaced apart from each other. In the igbt area 2100, the via hole includes a first via hole 2002 extending in the first direction, and the first trench structure 2001 is provided spaced apart from the first via hole 2002. In the fast recovery diode region 2210, the through hole includes a first through hole 2002 extending in the first direction, and the first trench structure 2001 is disposed spaced apart from the first through hole 2002. In the first buffer area 2311, the through holes include a first through hole 2002 extending along a first direction and a second through hole 2004 extending along a second direction (not shown in the figure), the first through hole 2002 and the second through hole 2004 enclose at least one annular through hole, and the first annular groove structure and the annular through hole are arranged at intervals. In the second buffer 2312, the via holes include a first via hole 2002 extending in the first direction and a second via hole 2004 extending in the second direction, the first trench structure 2001 is disposed spaced apart from the first via hole 2002, and the second trench structure 2003 is disposed spaced apart from the second via hole 2004. It should be noted that, in the second buffer 2312, the first via 2002 and the second via 2004 are separated into a plurality of segments of vias, which may be square vias or rectangular vias, by the plurality of first trench structures 2001 and the plurality of second trench structures 2003 connected between the plurality of second annular trench structures.
As shown in fig. 12, a photoresist mask layer 3420 is formed on the shielding dielectric layer 3400, and the photoresist mask layer 3420 covers the igbt area 2100, the first buffer area 2311 and the second buffer area 2312 to expose the fast recovery diode area 2210. The local carrier lifetime control process is used to adjust the carrier lifetime of the fast recovery diode region 2210 and improve the dynamic parameters of the fast recovery diode region 2210, for example, the doping concentration of the second electrode region 3340. The local carrier lifetime control process comprises light ion doping such as H and He and annealing. After that, the photoresist mask layer 3420 is removed.
As shown in fig. 13, an emitter electrode 3500 is formed by depositing a layer of metal material on the blanket dielectric layer 3400 by conventional semiconductor processing techniques such as sputtering or evaporation. In the fast recovery diode region 2210, the emitter electrode 3500 is electrically connected to the second electrode region 3340 through a via hole. At the first buffer region 2311, the emitter electrode 3500 is electrically connected to the second electrode region 3340 through a via hole. At the second buffer area 2312, the emitter electrode 3500 is electrically connected to the contact area 3330 through a via hole. In the igbt area 2100, the emitter electrode 3500 is electrically connected to the emitter region 3320 and the contact region 3330 through a via hole.
As shown in fig. 14, the second surface of the substrate 3100 is thinned to a predetermined thickness by a thinning process, ion implantation of a first doping type (for example, N type) is performed on the thinned second surface of the substrate 3100, an electric field stop layer 3600 is formed on the second surface of the substrate 3100, and annealing is performed. The fast recovery diode region 2210 is masked with a mask, and a second doping type (for example, P-type) ion implantation is performed on the second surface of the substrate 3100 in the igbt region 2100, the first buffer region 2311, and the second buffer region 2312, thereby forming a collector region 3700 below the electric field stop layer 3600. The igbt area 2100, the second buffer area 2312, and the first buffer area 2311 are masked with a mask, ion implantation of a first doping type (for example, N type) is performed on the second surface of the substrate 3100 in the fast recovery diode area 3002, a first electrode area 3800 is formed below the electric field stop layer 3600, and annealing is performed. A layer of metal material is deposited below the first electrode region 3800 and the collector region 3700 through a semiconductor conventional process technology such as sputtering or evaporation, so as to form a collector electrode 3900, wherein the collector electrode 3900 is electrically connected with the first electrode region 3800 and the collector region 3700 respectively.
According to the reverse conducting type insulated gate bipolar transistor and the manufacturing method thereof provided by the embodiment of the invention, the reverse conducting type insulated gate bipolar transistor comprises: the fast recovery diode area is arranged in the insulated gate bipolar transistor area, and the insulated gate bipolar transistor area surrounds the fast recovery diode area; the buffer areas and the fast recovery diode areas are correspondingly arranged and respectively located between the fast recovery diode areas and the insulated gate bipolar transistor areas, and at least one buffer area respectively surrounds at least one fast recovery diode area. The fast recovery diode region is prevented from being directly surrounded by the insulated gate bipolar transistor region, the problem that the gate resistance of the reverse conducting insulated gate bipolar transistor is increased due to the increase of the local gate resistance of the trench gate structure between the fast recovery diode regions is solved, the opening time delay and the turn-off time delay of the device are reduced, and the reliability of the device is improved.
The buffer area includes: a first buffer and a second buffer. The first buffer area surrounds the corresponding fast recovery diode area, the second buffer area surrounds the first buffer area, and the insulated gate bipolar transistor area surrounds the second buffer area. The first buffer area comprises at least one first groove structure and at least one second groove structure, and the at least one first groove structure and the at least one second groove structure enclose at least one first annular groove structure. The first annular groove structure of the first buffer area forms an isolation area, the dynamic parameters of the insulated gate bipolar transistor area close to the fast recovery diode area are prevented from being influenced when the dynamic parameters of the fast recovery diode area are improved by adopting a local carrier service life control process, the carrier service life control process can be independently carried out on at least one fast recovery diode area and the insulated gate bipolar transistor area, and the saturation voltage drop of the adjacent insulated gate bipolar transistor area is prevented from increasing along with the reduction of the carrier service life.
In the second buffer region, the trench structure includes: the first groove structure and the second groove structure enclose at least one second annular groove structure, the groove structure in the insulated gate bipolar transistor area between the adjacent buffer areas is connected with the at least one second annular groove structure, the through holes comprise a first through hole extending along the first direction and a second through hole extending along the second direction, the first groove structure and the first through hole are arranged at intervals, and the second groove structure and the second through hole are arranged at intervals. In some embodiments, the second buffer region includes a plurality of second annular trench structures, the plurality of second annular trench structures are connected with the plurality of first trench structures and the plurality of second trench structures therebetween, and the plurality of second annular trench structures are connected in parallel. The second ring-shaped groove structure of the second buffer area increases grid current between a plurality of fast recovery diode areas and between the plurality of fast recovery diode areas and the terminal area, reduces grid resistance between the plurality of fast recovery diode areas and the terminal area, reduces trailing current of a device in a turn-off stage, reduces switching loss of the device, and improves reliability and service life of the device.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (43)
1. A reverse conducting insulated gate bipolar transistor comprising:
the fast recovery diode comprises an insulated gate bipolar transistor area and at least one fast recovery diode area, wherein the at least one fast recovery diode area is arranged in the insulated gate bipolar transistor area, and the insulated gate bipolar transistor area surrounds the at least one fast recovery diode area;
the at least one buffer area is arranged corresponding to the at least one fast recovery diode area and is respectively positioned between the at least one fast recovery diode area and the insulated gate bipolar transistor area, and the at least one buffer area respectively surrounds the at least one fast recovery diode area.
2. The reverse conducting insulated gate bipolar transistor according to claim 1, further comprising:
a termination region surrounding the IGBT region, the at least one fast recovery diode region, and the at least one buffer region.
3. The igbt of claim 1 wherein the igbt region, the at least one fast recovery diode region, and the at least one buffer region comprise:
a substrate as a drift region;
a trench structure in the substrate;
the covering medium layer is positioned above the substrate, a through hole is formed in the covering medium layer, and the through hole and the groove structure are arranged at intervals;
an electric field cut-off layer located below the substrate;
the emitter electrode is positioned on the covering dielectric layer;
and a collector electrode positioned below the electric field cut-off layer.
4. The reverse conducting insulated gate bipolar transistor according to claim 3, wherein the insulated gate bipolar transistor region further comprises:
a body region in the substrate;
the contact region and the emitter region are positioned in the body region, the top of the groove structure is positioned in the contact region, the top of the groove structure is close to the emitter region, and the groove structure is electrically connected with the grid electrode;
the emitter electrode is electrically connected with the emitter region and the contact region through the through hole;
and the collector region is positioned between the electric field stop layer and the collector electrode.
5. The reverse conducting insulated gate bipolar transistor of claim 4, wherein said fast recovery diode region further comprises:
a first electrode region between the electric field cut-off layer and the collector electrode;
a second electrode region in the substrate, a top of the trench structure being in the second electrode region, the trench structure being electrically connected to the emitter electrode;
the emitter electrode is electrically connected with the second electrode region through the through hole.
6. The reverse conducting insulated gate bipolar transistor according to claim 5, wherein said buffer region comprises: the fast recovery diode comprises a first buffer area and a second buffer area, wherein the first buffer area surrounds the corresponding fast recovery diode area, the second buffer area surrounds the first buffer area, and the insulated gate bipolar transistor area surrounds the second buffer area.
7. The reverse conducting insulated gate bipolar transistor according to claim 6, wherein said first buffer region further comprises:
the top of the groove structure is positioned in the second electrode region, and the groove structure is electrically connected with the emitter electrode;
the emitter electrode is electrically connected with the second electrode area through the through hole;
the collector region.
8. The reverse conducting insulated gate bipolar transistor according to claim 7, wherein said second buffer region further comprises:
the body region;
the contact region is positioned at the top of the groove structure, and the groove structure is electrically connected with the grid electrode;
the emitter electrode is electrically connected with the contact region through the through hole;
the collector region.
9. The reverse conducting insulated gate bipolar transistor according to claim 4, wherein in the insulated gate bipolar transistor region, the trench structure comprises: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
10. The reverse conducting insulated gate bipolar transistor of claim 5, wherein in the fast recovery diode region, the trench structure comprises: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
11. The reverse conducting insulated gate bipolar transistor according to claim 7, wherein in the first buffer region, the trench structure comprises: the trench structure comprises a first trench structure extending along a first direction and a second trench structure extending along a second direction, wherein the first trench structure and the second trench structure enclose at least one first annular trench structure, the through holes comprise a first through hole extending along the first direction and a second through hole extending along the second direction, the first through hole and the second through hole enclose at least one annular through hole, and the first annular trench structure and the annular through hole are arranged at intervals.
12. The reverse conducting insulated gate bipolar transistor according to claim 8, wherein in the second buffer region, the trench structure comprises: the insulated gate bipolar transistor structure comprises a first groove structure extending along a first direction and a second groove structure extending along a second direction, wherein the first groove structure and the second groove structure enclose at least one second annular groove structure, the groove structures in the insulated gate bipolar transistor area between the adjacent buffer areas are connected with the at least one second annular groove structure, the through holes comprise first through holes extending along the first direction and second through holes extending along the second direction, the first groove structures and the first through holes are arranged at intervals, and the second groove structures and the second through holes are arranged at intervals.
13. The igbt of claim 12 wherein the trench structures in the second buffer region comprise a plurality of the second annular trench structures with the plurality of first trench structures and the plurality of second trench structures connected therebetween, the plurality of second annular trench structures being connected in parallel.
14. The reverse conducting insulated gate bipolar transistor according to claim 3, wherein said trench structure comprises:
a trench in the substrate, the trench extending from a first surface of the substrate to a second surface of the substrate;
the gate dielectric layer is positioned in the groove and covers the side wall and the bottom of the groove;
and the polycrystal is positioned on the gate dielectric layer and fills the groove.
15. The reverse conducting insulated gate bipolar transistor according to claim 11 or 12, wherein the first direction and the second direction are perpendicular.
16. The reverse conducting insulated gate bipolar transistor according to claim 4, wherein said contact region has a junction depth less than said body region and a doping concentration greater than said body region.
17. The reverse conducting insulated gate bipolar transistor of claim 5, wherein said second electrode region has a junction depth less than said body region and a doping concentration greater than said body region.
18. The reverse conducting igbt of claim 8 wherein the substrate, the first electrode region, the emitter region, and the field stop layer are of a first doping type, the body region, the contact region, the collector region, and the second electrode region are of a second doping type, and the first doping type and the second doping type are opposite.
19. The reverse conducting insulated gate bipolar transistor of claim 14, wherein the width of the trench comprises 0.4um to 2um, the depth of the trench comprises 2um to 10um, and the pitch of the trench comprises 0.6um to 10 um.
20. The igbt of claim 1 wherein the at least one fast recovery diode region has an area that accounts for less than or equal to 40% of the total area of the igbt region, the at least one fast recovery diode region, and the at least one buffer region.
21. The reverse conducting insulated gate bipolar transistor of claim 5, wherein the doping concentration of the second electrode region is greater than 1E18cm-3。
22. A method for manufacturing a reverse conducting insulated gate bipolar transistor comprises the following steps:
forming an insulated gate bipolar transistor area;
forming at least one fast recovery diode region, the at least one fast recovery diode region being disposed in the insulated gate bipolar transistor region, the insulated gate bipolar transistor region surrounding the at least one fast recovery diode region;
and forming at least one buffer area, wherein the at least one buffer area is arranged corresponding to the at least one fast recovery diode area and is respectively positioned between the at least one fast recovery diode area and the insulated gate bipolar transistor area, and the at least one buffer area respectively surrounds the at least one fast recovery diode area.
23. The manufacturing method of claim 22, wherein the manufacturing method further comprises:
forming a termination region surrounding the IGBT region, the at least one fast recovery diode region, and the at least one buffer region.
24. The method of manufacturing of claim 22, wherein forming the insulated gate bipolar transistor region, the at least one fast recovery diode region, and the at least one buffer region comprises:
forming a substrate as a drift region;
forming a trench structure in the substrate;
forming a covering medium layer above the substrate, wherein a through hole is formed in the covering medium layer, and the through hole and the groove structure are arranged at intervals;
forming an electric field cut-off layer under the substrate;
forming an emitter electrode on the covering dielectric layer;
and forming a collector electrode below the electric field cut-off layer.
25. The manufacturing method according to claim 24, wherein forming the igbt region further comprises:
forming a body region in the substrate;
forming a contact region and an emitter region in the body region, wherein the top of the trench structure is positioned in the contact region, the top of the trench structure is close to the emitter region, and the trench structure is electrically connected with the gate electrode;
the emitter electrode is electrically connected with the emitter region and the contact region through the through hole;
a collector region is formed between the electric field stop layer and the collector electrode.
26. The method of manufacturing of claim 25, wherein forming the fast recovery diode region further comprises:
forming a first electrode region between the electric field cut-off layer and the collector electrode;
forming a second electrode region in the substrate, a top of the trench structure being located in the second electrode region, the trench structure being electrically connected to the emitter electrode;
the emitter electrode is electrically connected with the second electrode region through the through hole.
27. The method of manufacturing of claim 26, wherein the buffer zone comprises: the fast recovery diode comprises a first buffer area and a second buffer area, wherein the first buffer area surrounds the corresponding fast recovery diode area, the second buffer area surrounds the first buffer area, and the insulated gate bipolar transistor area surrounds the second buffer area.
28. The method of manufacturing of claim 27, wherein forming the first buffer region further comprises:
forming the second electrode region, wherein the top of the groove structure is positioned in the second electrode region, and the groove structure is electrically connected with the emitter electrode;
the emitter electrode is electrically connected with the second electrode area through the through hole;
and forming the collector region.
29. The method of manufacturing of claim 28, wherein forming the second buffer region further comprises:
forming the body region;
forming the contact region, wherein the top of the trench structure is positioned in the contact region, and the trench structure is electrically connected with the grid electrode;
the emitter electrode is electrically connected with the contact region through the through hole;
and forming the collector region.
30. The manufacturing method according to claim 25, wherein in the igbt region, the trench structure includes: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
31. The method of manufacturing of claim 26, wherein in the fast recovery diode region, the trench structure comprises: the through holes comprise first through holes extending along the first direction, and the first groove structures and the first through holes are arranged at intervals.
32. The manufacturing method of claim 28, wherein in the first buffer region, the trench structure comprises: the trench structure comprises a first trench structure extending along a first direction and a second trench structure extending along a second direction, wherein the first trench structure and the second trench structure enclose at least one first annular trench structure, the through holes comprise a first through hole extending along the first direction and a second through hole extending along the second direction, the first through hole and the second through hole enclose at least one annular through hole, and the first annular trench structure and the annular through hole are arranged at intervals.
33. The manufacturing method according to claim 29, wherein in the second buffer region, the trench structure includes: the insulated gate bipolar transistor structure comprises a first groove structure extending along a first direction and a second groove structure extending along a second direction, wherein the first groove structure and the second groove structure enclose at least one second annular groove structure, the groove structures in the insulated gate bipolar transistor area between the adjacent buffer areas are connected with the at least one second annular groove structure, the through holes comprise first through holes extending along the first direction and second through holes extending along the second direction, the first groove structures and the first through holes are arranged at intervals, and the second groove structures and the second through holes are arranged at intervals.
34. The manufacturing method according to claim 33, wherein the trench structure in the second buffer region includes a plurality of the second annular trench structures, the plurality of first trench structures and the plurality of second trench structures being connected between the plurality of second annular trench structures, the plurality of second annular trench structures being connected in parallel.
35. The method of manufacturing of claim 24, wherein the forming a trench structure in the substrate comprises:
forming a trench in the substrate, the trench extending from a first surface of the substrate to a second surface of the substrate;
forming a gate dielectric layer in the groove, wherein the gate dielectric layer covers the side wall and the bottom of the groove;
and forming a polycrystal on the gate dielectric layer, wherein the polycrystal fills the groove.
36. The method of manufacturing of claim 24, wherein after forming a capping dielectric layer over the substrate, the method of manufacturing further comprises:
and forming a photoresist masking layer on the at least one buffer area and the insulated gate bipolar transistor area, wherein the photoresist masking layer exposes the at least one fast recovery diode area, and the dynamic parameters of the at least one fast recovery diode area are improved by adopting a local carrier lifetime control process.
37. The manufacturing method according to claim 32 or 33, wherein the first direction is perpendicular to the second direction.
38. The method of manufacturing of claim 25, wherein the contact region has a junction depth less than the body region and a doping concentration greater than the body region.
39. The method of manufacturing of claim 26, wherein the second electrode region has a junction depth less than the body region and a doping concentration greater than the body region.
40. The method of manufacturing of claim 29, wherein the substrate, the first electrode region, the emitter region, and the electric field stop layer are of a first doping type, the body region, the contact region, the collector region, and the second electrode region are of a second doping type, the first doping type and the second doping type being opposite.
41. The method of manufacturing of claim 35, wherein the width of the trenches comprises 0.4um to 2um, the depth of the trenches comprises 2um to 10um, and the pitch of the trenches comprises 0.6um to 10 um.
42. The method of manufacturing of claim 22, wherein a proportion of an area of the at least one fast recovery diode region to a total area of the igbt region, the at least one fast recovery diode region, and the at least one buffer region is 40% or less.
43. The method of manufacturing of claim 26, wherein the second electrode region has a doping concentration greater than 1E18cm-3。
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