CN117594592A - Semiconductor integrated chip and manufacturing method thereof - Google Patents

Semiconductor integrated chip and manufacturing method thereof Download PDF

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Publication number
CN117594592A
CN117594592A CN202311760751.9A CN202311760751A CN117594592A CN 117594592 A CN117594592 A CN 117594592A CN 202311760751 A CN202311760751 A CN 202311760751A CN 117594592 A CN117594592 A CN 117594592A
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Prior art keywords
oxide layer
tube
region
field oxide
detected
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Inventor
赵二坤
陈一
尚松川
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Xinlian Pioneer Integrated Circuit Manufacturing Shaoxing Co ltd
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Xinlian Pioneer Integrated Circuit Manufacturing Shaoxing Co ltd
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Priority to CN202311760751.9A priority Critical patent/CN117594592A/en
Publication of CN117594592A publication Critical patent/CN117594592A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor integrated chip and a manufacturing method thereof, wherein the semiconductor integrated chip comprises a substrate, the substrate is provided with a cell area and a terminal area, the cell area is provided with an IGBT tube to be detected and an IGBT tube to be detected, and the terminal area is provided with a diode, a resistor and an MOS tube; according to the invention, the diode and the resistor are arranged in the terminal area, so that the overcurrent protection circuit is monolithically integrated on the semiconductor integrated chip, the chip integration level can be improved, the occupied area of the PCB is reduced, the short-circuit protection function (namely, the overcurrent protection function) is realized, the saturated current of the IGBT tube to be detected in the short circuit process is reduced, the heat damage of the IGBT tube to be detected due to the excessively high current is avoided, namely, the risk of breakdown of the IGBT tube to be detected is reduced, and the delay is also reduced.

Description

Semiconductor integrated chip and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor integrated chip and a manufacturing method thereof.
Background
In conventional IGBT (insulated gate bipolar transistor) application circuits, sensors embedded in the power electronics system are typically used to monitor the operation of the circuit. When the current of the IGBT chip in the IGBT application circuit exceeds several times of rated on-state current, the IGBT chip needs to be turned off to avoid the maximum bearable junction temperature. The current of IGBT chip is monitored to current monitoring module that adopts to set up integrated board level on the PCB board in current mainstream scheme usually, and it has increased the area occupied of PCB board, and current mainstream scheme still has the risk of breakdown IGBT chip and delay higher scheduling problem.
Disclosure of Invention
The invention aims to provide a semiconductor integrated chip and a manufacturing method thereof, which can improve the integration level to reduce the occupied area of a PCB (printed circuit board), reduce the risk of breakdown of an IGBT (insulated Gate Bipolar transistor) chip and reduce the time delay.
In order to solve the above problems, the present invention provides a semiconductor integrated chip, comprising a substrate having a cell region provided with an IGBT tube to be detected and a detection IGBT tube and a terminal region provided with a diode, a resistor and a MOS tube;
the collector of the IGBT tube to be detected is electrically connected with the collector of the IGBT tube to be detected, the grid of the IGBT tube to be detected is electrically connected with the grid of the IGBT tube to be detected and the anode of the diode at the same time, the emitter of the IGBT tube to be detected is electrically connected with one end of the resistor and the grid of the MOS tube at the same time, the drain of the MOS tube is electrically connected with the cathode of the diode, and the other end of the resistor is electrically connected with the source of the MOS tube and the emitter of the IGBT tube to be detected at the same time.
Optionally, in the termination region, a first field oxide layer and a second field oxide layer are disposed on the substrate at intervals, the first field oxide layer is disposed near the cellular region, a diode is disposed on the first field oxide layer, a resistor is disposed on the second field oxide layer, and the MOS transistor is disposed between the first field oxide layer and the second field oxide layer.
Further, the terminal area is further provided with a TVS tube, one end of the TVS tube is electrically connected with the grid electrode of the detection IGBT tube, and the other end of the TVS tube is electrically connected with the grid electrode of the MOS tube.
Further, the voltage withstand of the TVS tube is lower than the voltage withstand requirement between the grid electrode and the emitter electrode of the IGBT tube to be detected, and the voltage withstand requirement between the grid electrode and the emitter electrode of the IGBT tube to be detected is lower than the voltage withstand of the MOS tube.
Further, the terminal area sequentially comprises a first terminal area, a second terminal area and a third terminal area from the cell area to a direction far away from the cell area, the diode and the resistor are both located in the first terminal area, the TVS tube is arranged in the second terminal area through isolation groove structures in an isolated mode, and the MOS tube is arranged in the third terminal area through isolation groove structures in an isolated mode.
Further, the MOS tube is an LDMOS tube.
Further, in the second terminal region, a third field oxide layer and an isolation trench structure are formed on the substrate, the TVS tube is disposed on the third field oxide layer, and the third field oxide layer is disposed inside the isolation trench structure of the second terminal region; the TVS tube comprises a plurality of first subregions and a plurality of second subregions, wherein the first subregions and the second subregions are periodically arranged along the extending direction of the TVS tube, and in the extending direction of the TVS tube, the regions at two ends are both the first subregions or the second subregions, and the conductivity types of the first subregions and the second subregions are opposite.
On the other hand, the invention also provides a manufacturing method of the semiconductor integrated chip, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a cell area and a terminal area;
forming an IGBT tube to be detected and an IGBT tube to be detected in the cell region, and forming a diode, a resistor and an MOS tube in the terminal region;
the detector comprises a detector, a diode, a resistor, a diode, a resistor, a MOS tube, a collector electrode of the IGBT tube to be detected, a gate electrode of the diode, a source electrode of the MOS tube and an emitting electrode of the IGBT tube to be detected.
Optionally, the terminal area is provided with a first field oxide layer and a second field oxide layer which are arranged at intervals.
Further, the steps of forming the IGBT tube to be detected and the detection IGBT tube in the cell region, and forming the diode, the resistor and the MOS tube in the terminal region at the same time are specifically as follows:
forming a semiconductor material layer on the substrate, wherein the semiconductor material layer covers the first field oxide layer, the second field oxide layer and the cell region, and has an n-type conductivity;
Forming a patterned first photoresist layer on the semiconductor material layer, etching the semiconductor material layer by taking the patterned first photoresist layer as a mask, forming a grid electrode of the IGBT tube to be detected and a grid electrode of the IGBT tube to be detected in the cell area, forming an initial diode on the first field oxide layer, forming a resistor on the second field oxide layer, forming a grid electrode of the MOS tube between the first field oxide layer and the second field oxide layer, and removing the first photoresist layer;
and carrying out p-type conductivity type ion implantation on a partial region of the initial diode to form the diode.
Further, the MOS transistor is an LDMOS transistor, the termination region sequentially includes a first termination region, a second termination region and a third termination region from the cell region to a direction far away from the cell region, a first field oxide layer and a second field oxide layer are disposed on a substrate of the first termination region at intervals, a third field oxide layer is disposed on a substrate of the second termination region, a gate oxide layer and a fourth field oxide layer which are disposed adjacently are disposed on a substrate of the third termination region, isolation trenches are disposed in the substrates of the second termination region and the third termination region, isolation trenches of the second termination region are disposed around the outside of the third field oxide layer, and isolation trenches of the third termination region are disposed around the outside of the gate oxide layer and the fourth field oxide layer.
Further, the steps of forming the IGBT tube to be detected and the detection IGBT tube in the cell region, and forming the diode, the resistor and the MOS tube in the terminal region at the same time are specifically as follows:
forming a semiconductor material layer on the upper surface of the substrate, wherein the semiconductor material layer fills the isolation groove and also covers the cell region, the first field oxide layer, the second field oxide layer, the third field oxide layer, the fourth field oxide layer and the gate oxide layer, and the semiconductor material layer has an n-type conductivity type;
forming a patterned first photoresist layer on the semiconductor material layer, etching the semiconductor material layer by taking the patterned first photoresist layer as a mask, forming a grid electrode of the IGBT tube to be detected and a grid electrode of the IGBT tube to be detected by taking the cell area, forming an initial diode on the first field oxide layer, forming a resistor on the second field oxide layer, forming an initial TVS tube on the third field oxide layer, forming a field plate of an LDMOS tube on the fourth field oxide layer, forming a grid electrode of the LDMOS tube on the gate oxide layer, and removing the first photoresist layer;
and carrying out p-type conductivity type ion implantation on the partial region of the initial diode and the partial region of the initial TVS tube to form the diode and the TVS tube.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a semiconductor integrated chip and a manufacturing method thereof, wherein the semiconductor integrated chip comprises a substrate, the substrate is provided with a cell area and a terminal area, the cell area is provided with an IGBT tube to be detected and an IGBT tube to be detected, and the terminal area is provided with a diode, a resistor and an MOS tube; the collector of the IGBT tube to be detected is electrically connected with the collector of the IGBT tube to be detected, the grid of the IGBT tube to be detected is electrically connected with the grid of the IGBT tube to be detected and the anode of the diode at the same time, the emitter of the IGBT tube to be detected is electrically connected with one end of the resistor and the grid of the MOS tube at the same time, the drain of the MOS tube is electrically connected with the cathode of the diode, and the other end of the resistor is electrically connected with the source of the MOS tube and the emitter of the IGBT tube to be detected at the same time. According to the invention, the diode and the resistor are arranged in the terminal area, so that the overcurrent protection circuit is monolithically integrated on the semiconductor integrated chip, the chip integration level can be improved, the occupied area of the PCB is reduced, the short-circuit protection function (namely, the overcurrent protection function) is realized, the saturated current of the IGBT tube to be detected in the short circuit process is reduced, the heat damage of the IGBT tube to be detected due to the excessively high current is avoided, namely, the risk of breakdown of the IGBT tube to be detected is reduced, and the delay is also reduced.
Further, the terminal area II of the semiconductor integrated chip is further provided with a TVS tube, so that the terminal area is provided with a diode, a resistor, a MOS tube and a TVS tube, the integration level can be improved, the occupied area of a PCB (printed circuit board) is reduced, meanwhile, overcurrent protection and overvoltage protection are realized, the risk of breakdown of an IGBT (insulated gate bipolar transistor) chip is reduced, the time delay is reduced, and the reliability of the device is improved.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor integrated chip according to a first embodiment of the present invention;
fig. 2 is a circuit diagram of a semiconductor integrated chip according to a first embodiment of the present invention;
fig. 3 to fig. 5 are schematic structural diagrams of a semiconductor integrated chip according to a first embodiment of the present invention in a manufacturing process;
fig. 6 is a schematic structural diagram of a semiconductor integrated chip according to a second embodiment of the present invention;
FIG. 7 is an enlarged schematic view at P in FIG. 6;
fig. 8 is a circuit diagram of a semiconductor integrated chip according to a second embodiment of the present invention;
fig. 9 to 11 are schematic structural diagrams of a semiconductor integrated chip according to a second embodiment of the present invention in a manufacturing process.
Reference numerals illustrate:
100-a substrate; a 101-CS layer; 102-a first well region; 103-an extraction zone; 104-an emitter region; 105-conductive regions; 106-a second well region; 107-source region; 108-a drain region; 109-a second doped region; 110-a first doped region; 111-a third doped region; 112-body region; 113-a drift region;
200-a layer of semiconductor material; 201-a first field oxide layer; 202-a second field oxide layer; 203-a third field oxide layer; 204-a fourth field oxide layer; 211-a first gate; 2121-first region; 2122-second region; 213-a second gate; 214-resistance; 215-field plates; 216-TVS tube; 2161-first sub-region; 2162-second subregion; 217-isolation trench structure;
311. 312, 313-first conductive pillars; 321. 322-second conductive pillars; 330-a third conductive post; 341. 342-fourth conductive pillars; 351. 352, 353-fifth conductive column; 361. 362-sixth conductive pillars; 371. 372-seventh conductive pillars;
400-a first photoresist layer.
Detailed Description
A semiconductor integrated chip and a method of manufacturing the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
The invention provides a semiconductor integrated chip, which comprises a substrate, wherein the substrate is provided with a cell area I and a terminal area II, the cell area is provided with an IGBT tube Q1 to be detected and an IGBT tube Q2 to be detected, and the terminal area is provided with a diode D, a resistor Rs and a MOS tube Q3.
According to the invention, the diode D and the resistor Rs are arranged in the terminal area, so that an overcurrent protection circuit is monolithically integrated on the semiconductor integrated chip, the chip integration level can be improved, the occupied area of a PCB (printed circuit board) is reduced, the short-circuit protection function (namely, the overcurrent protection function) is realized, the saturated current of the IGBT tube Q1 to be detected in the short circuit is reduced, the heat damage of the IGBT tube Q1 to be detected due to the excessively high current is avoided, namely, the risk of breakdown of the IGBT tube Q1 to be detected is reduced, and the delay is also reduced.
Example 1
The embodiment provides a semiconductor integrated chip, which comprises a substrate, wherein the substrate is provided with a cell area I and a terminal area II, the cell area is provided with an IGBT tube Q1 to be detected and an IGBT tube Q2 to be detected, and the terminal area is provided with a diode D, a resistor Rs and a MOS tube Q3.
As shown in fig. 2, the collector C of the IGBT tube Q1 to be detected is connected to the collector of the IGBT tube Q2 to be detected, the gate G of the IGBT tube Q1 to be detected is simultaneously connected to the gate of the IGBT tube Q2 to be detected and the anode of the diode D, the emitter of the IGBT tube Q2 to be detected is simultaneously connected to one end of the resistor Rs and the gate of the MOS tube Q3, the drain of the MOS tube Q3 is connected to the cathode of the diode D, and the other end of the resistor Rs is simultaneously connected to the source of the MOS tube Q3 and the emitter E of the IGBT tube Q1 to be detected. The MOS tube Q3 is a transverse MOSFET tube, the IGBT tube Q1 to be detected is used as a main IGBT tube, namely a to-be-detected IGBT tube, and the IGBT tube Q2 to be detected is used as a detection IGBT tube.
When the circuit is in short circuit, the on-state current IC of the detection IGBT tube Q2 is larger than the preset threshold value of the detection IGBT tube Q2, so that the voltage (namely the voltage drop) at two ends of the resistor Rs is larger than the threshold voltage of the MOS tube Q3, the MOS tube Q3 is turned on, the grid voltage of the IGBT tube Q1 to be detected is pulled down, the grid voltage of the IGBT tube Q1 to be detected is smaller than the normal grid driving voltage when the grid voltage is in an on state, the IGBT tube Q1 to be detected is turned off, the turn-off and turn-on of the IGBT tube Q1 to be detected are controlled, the damage of the IGBT tube Q1 to be detected caused by the over-high current is protected, namely the fact that the IGBT tube Q1 to be detected reaches the maximum bearable junction temperature is avoided, and the over-current protection of the IGBT tube Q1 to be detected is realized.
As shown in fig. 1, a CS layer (carrier storage layer) 101 and a first well region 102 are sequentially disposed in the substrate 100 of the cellular region I from bottom to top, the first well region 102 extends from the upper surface toward the lower surface into the substrate 100, and the CS layer 101 is adjacently disposed below the first well region 102. Wherein the first well region 102 has a first conductivity type, e.g., p-type, and the CS layer 101 has a second conductivity type, e.g., n-type.
A plurality of cell grooves are formed in the substrate 100 of the cell region I, the cell grooves penetrate through the upper surface and the bottom of the cell grooves is exposed out of the substrate 100 below the CS layer 101, a gate oxide layer is disposed on the inner wall of the cell grooves, a first gate 211 is disposed in the cell grooves, the cell grooves are filled with the first gate 211, a leading-out region 103 and a transmitting region 104 are disposed in the first well region 102 outside most of the cell grooves from bottom to top adjacently in sequence, a collector region (not shown in the figure) is disposed on the lower surface, and the first gate 211, the transmitting region 104 and the collector region form an IGBT tube Q1 to be detected and an IGBT tube Q2 to be detected. Wherein the first gate 211 has a second conductivity type, such as n-type; the extraction region 103 has a first conductivity type, for example p-type; the emitter region 104 and collector region each have a second conductivity type, such as n-type.
In this embodiment, the extraction region 103 and the emission region 104 are not disposed in the first well region 102 between the two first gates 211 near the terminal region II.
A conductive region 105 is disposed in the substrate 100 of the terminal region II, the conductive region 105 is disposed adjacent to the cell region I and is disposed adjacent to the first gate 211 of the cell region I adjacent to the terminal region II, the conductive region 105 extends from the upper surface to the lower surface into the substrate 100, and a second well region 106 is disposed in the conductive region 105. The substrate 100 in the terminal region II is provided with a first field oxide layer 201 and a second field oxide layer 202 that are disposed at intervals, the first field oxide layer 201 and the second field oxide layer 202 are located at two sides of the second well region 106 and each have an overlapping region with the second well region 106, the first field oxide layer 201 is located on the conductive region 105 and is disposed near the first well region 102, the second field oxide layer 202 is located at a boundary of the conductive region 105, and a conductive ring, such as a P-type conductive ring P-ring, is disposed in the substrate of the second field oxide layer 202 far from the first field oxide layer 201. Wherein the second well region 106 and the conductive region 105 each have a first conductivity type, e.g., p-type.
A diode, such as a polysilicon diode, is disposed on the first field oxide layer 201. The diode is provided with a first region 2121 and a second region 2122 adjacent in its extension direction, the first region 2121 having a first conductivity type, e.g. p-type; the second region 2122 has a second conductivity type, e.g., n-type. A resistor 214 is formed on the second field oxide layer 202, and the resistor 214 is, for example, a polysilicon resistor having a second conductivity type, for example, n-type. A gate structure is formed on the substrate 100 of the second well region 106, the gate structure sequentially includes a gate oxide layer and a second gate layer 213 from bottom to top, a source region 107 and a drain region 108 are formed in the substrate on two sides of the gate structure, and the source region 107 and the drain region 108 each have a second conductivity type, such as n-type. The gate structure, source region 107 and drain region 108 constitute a lateral MOS transistor.
A first interlayer dielectric layer (ILD) (not shown) is formed on the substrate 100, the first interlayer dielectric layer covers the first gate 211 and the emitter region 104 of the cell region I and also covers the diode, the gate structure and the resistor 214 of the terminal region II, a plurality of conductive pillars are disposed in the first interlayer dielectric layer, and one end of all the conductive pillars leads out the first gate 213 and the emitter region 104 of the cell region I and also leads out the diode, the gate structure and the resistor 214 of the terminal region II. And a metal layer is arranged on the first interlayer dielectric layer, and the metal layer is positioned on the first interlayer dielectric layer and is connected with the other ends of all the conductive posts so as to electrically connect the semiconductor integrated chip. The materials of the first gate electrode 211 and the second gate electrode 213 are all semiconductor materials, such as polysilicon, monocrystalline silicon, etc., and in this embodiment, the materials of the first gate electrode 211 and the second gate electrode 213 are all polysilicon.
In this embodiment, the conductive pillars include three first conductive pillars 311, 312, 313, two second conductive pillars 321, 322, one third conductive pillar, two fourth conductive pillars, three fifth conductive pillars, and two sixth conductive pillars, one end of one first conductive pillar 311 extends into an emission region constituting the IGBT tube Q1 to be detected and stops in the extraction region to extract the emitter end of the IGBT tube Q1 to be detected, one end of two first conductive pillars 312, 313 extends into the first well region 102 and the conductive region 105 outside the first gate 211 near the terminal region II and stops in the extraction region; the two second conductive columns extend into a first grid electrode 211 forming an IGBT tube Q1 to be detected and a first grid electrode 211 forming an IGBT tube Q2 to be detected so as to lead out the grid electrodes of the IGBT tube Q1 to be detected and the IGBT tube Q2 to be detected; one end of the third conductive column extends into an emission region forming the detection IGBT tube Q2 and stops in the extraction region so as to extract an emitter of the detection IGBT tube Q2; the fourth conductive pillar 341 extends into the first region 2121 of the diode, and the fourth conductive pillar 342 extends into the second region 2122 of the diode to draw out the two poles of the diode D; three of the fifth conductive pillars 351, 352, 353 respectively lead out the second gate 213, the source region 107, and the drain region 108; two of the sixth conductive pillars 361, 362 extend into both ends of the resistor to draw out both ends of the resistor Rs.
The embodiment also provides a method for manufacturing the semiconductor integrated chip, which comprises the following steps:
step S11: providing a substrate 100, wherein the substrate 100 is provided with a cell area I and a terminal area II;
step S12: forming an IGBT tube Q1 to be detected and an IGBT tube Q2 to be detected in the cell region I, and forming a diode D, a resistor Rs and an MOS tube Q3 in the terminal region II;
step S13: the detector is characterized in that the detector is electrically connected with a collector of the IGBT tube Q1 to be detected and a collector of the IGBT tube Q2 to be detected, the detector is electrically connected with a grid of the IGBT tube Q1 to be detected, a grid of the IGBT tube Q2 to be detected and a positive electrode of the diode D, the detector is electrically connected with an emitter of the IGBT tube Q2 to be detected, one end of the resistor Rs and a grid of the MOS tube Q3, the drain of the MOS tube Q3 is electrically connected with a negative electrode of the diode D, and the other end of the resistor Rs, a source of the MOS tube Q3 and the emitter of the IGBT tube Q1 to be detected are electrically connected.
The following describes in detail a method for manufacturing a semiconductor integrated chip according to this embodiment with reference to fig. 1 to 5.
As shown in fig. 3, step S11 is first performed, and a substrate 100 is provided, where the substrate 100 has a cell area I and a terminal area II.
A CS layer (carrier storage layer) 101 is provided in the substrate 100 of the cell region I, the CS layer extending downward from the upper surface in the substrate 100. Wherein the CS layer 101 has a second conductivity type, e.g., n-type. A plurality of cell grooves are formed in the substrate 100 of the cell area I, the cell grooves penetrate through the upper surface, the bottom of the cell grooves exposes the substrate 100 below the CS layer 101, and a gate oxide layer is disposed on the inner wall of the cell grooves.
A conductive region 105 is disposed in the substrate 100 of the terminal region II, the conductive region 105 being disposed adjacent to the cell region I and adjacent to the first gate 211 of the cell region I adjacent to the terminal region II, the conductive region 105 extending from the upper surface to the lower surface into the substrate 100. A first field oxide layer 201 and a second field oxide layer 202 are disposed on the substrate 100 in the terminal region II at intervals, the first field oxide layer 201 is located on the conductive region 105 and is disposed close to the cell region I, the second field oxide layer 202 is located at a boundary of the conductive region 105, and a conductive ring, such as a P-type conductive ring P-ring, is disposed in the substrate of the second field oxide layer 202 far from the first field oxide layer 201. A gate oxide layer is formed on the substrate between the first field oxide layer 201 and the second field oxide layer 202, and the gate oxide layer connects the first field oxide layer 201 and the second field oxide layer 202.
Next, step S12 is performed, where the IGBT tube Q1 to be detected and the IGBT tube Q2 to be detected are formed in the cell region, and the diode D, the resistor Rs, and the MOS tube Q3 are formed in the terminal region.
The method specifically comprises the following steps:
as shown in fig. 4, first, a semiconductor material layer 200 is formed, which fills the cell trench, covering the upper surface of the substrate 100, the first field oxide layer 201, the second field oxide layer 202, and the gate oxide layer between the first field oxide layer 201 and the second field oxide layer 202. The semiconductor material layer 200 may be a polysilicon material layer, and the polysilicon material layer has a second conductivity type, such as n-type.
Next, a patterned first photoresist layer 400 is formed on the semiconductor material layer 200, wherein the patterned first photoresist layer 400 covers a portion of the first field oxide layer 201, a portion of the second field oxide layer 202, and a portion of the gate oxide layer between the first field oxide layer 201 and the second field oxide layer 202.
As shown in fig. 5, the patterned first photoresist layer 400 is used as a mask to etch the semiconductor material layer 200, so as to expose the first field oxide layer 201, the second field oxide layer 201, the gate oxide layer and the upper surface of the substrate outside the first photoresist layer 400.
Next, the exposed gate oxide layer between the first field oxide layer 201 and the second field oxide layer 202 is etched to remove the gate oxide layer outside the patterned first photoresist layer 400, and then the first photoresist layer 400 is removed. Of course, the first photoresist layer 400 may be removed first, and the gate oxide layer is etched, so as to form a first gate, a resistor, a gate structure and a diode in the cell trench.
As shown in fig. 1, a patterned second photoresist layer is then formed, the patterned second photoresist layer exposes the first region 2121 of the diode, and the first region 2121 is subjected to ion implantation of a first conductivity type with the patterned second photoresist layer as a mask to form the diode. And finally, removing the second photoresist layer.
Next, a first well region 102 is formed outside the cell trench, the first well region 102 extending from the upper surface towards the lower surface into the substrate 100, the CS layer 101 being adjacently disposed under the first well region 102. Meanwhile, a second well region 106 is formed in the conductive region between the first field oxide layer 201 and the second field oxide layer 202, the gate structure is located on the substrate of the second well region 106, and the first field oxide layer 201 and the second field oxide layer 202 uniformly overlap the first well region 102.
Next, a lead-out region 103 and an emitter region 104 are formed in the first well region 102 outside a part of the cell trench in order from bottom to top, and a source region 107 and a drain region 108 are formed on both sides of the second gate 213. An extraction region 103 is formed in the first well region 102 and the conductive region 105 on both sides of the cell trench near the termination region.
Wherein the emitter region 104, the source region 107 and the drain region 108 each have the second conductivity type, and the extraction region 103 and the first well region 102 each have the first conductivity type.
Step S13 is then executed, where the collector of the IGBT tube Q1 to be detected and the collector of the IGBT tube Q2 to be detected are electrically connected, the gate of the IGBT tube Q1 to be detected, the gate of the IGBT tube Q2 to be detected and the positive electrode of the diode D are electrically connected, the emitter of the IGBT tube Q2 to be detected, one end of the resistor Rs and the gate of the MOS tube Q3 are electrically connected, the drain of the MOS tube Q3 and the negative electrode of the diode D are electrically connected, and the other end of the resistor Rs, the source of the MOS tube Q3 and the emitter of the IGBT tube Q1 to be detected are electrically connected. The method specifically comprises the following steps:
First, a first interlayer dielectric layer is formed on the upper surface, and the first interlayer dielectric layer covers the first grid electrode, the resistor, the grid electrode structure and the diode.
And then, forming a plurality of conductive posts in the first interlayer dielectric layer, and forming a metal layer on the first interlayer dielectric layer. One end of all the conductive pillars leads out the first gate 213 and the emitter region 104 of the cellular region I, and also leads out the diode, the gate structure and the resistor 214 of the terminal region II. The metal layer is positioned on the first interlayer dielectric layer and connected with the other ends of all the conductive posts so as to electrically connect the semiconductor integrated chips.
Example two
As shown in fig. 6 to fig. 7, compared with the first embodiment, the difference of the present embodiment is that the terminal area II of the semiconductor integrated chip is further provided with a TVS (transient voltage suppressor) diode, so that the terminal area II is provided with a diode D, a resistor Rs, a MOS transistor and a TVS transistor, which can improve the integration level, reduce the occupied area of the PCB board, realize the overvoltage protection while realizing the overcurrent protection, reduce the risk of breakdown of the IGBT chip, reduce the delay, and improve the device reliability.
As shown in fig. 8, one end of the TVS tube is connected to the gate of the detection IGBT tube Q2, and the other end of the TVS tube is connected to the gate of the MOS tube Q3. The MOS transistor Q3 is, for example, a lateral LDMOS transistor, the withstand voltage of the TVS transistor is lower than the withstand voltage requirement between the gate G and the emitter E of the IGBT transistor Q1 to be detected, and the withstand voltage requirement between the gate G and the emitter E of the IGBT transistor Q1 to be detected is lower than the withstand voltage of the MOS transistor Q3.
When the detection IGBT tube Q2 is shunted to form a detection current Icd, voltage drop is formed at two ends of the resistor Rs, and when the voltage drop is larger than the threshold voltage of the MOS tube Q3, the grid G and the emitter E of the IGBT tube Q1 to be detected are in short circuit, so that the turn-off and turn-on of the IGBT tube Q1 to be detected are controlled, the damage of the IGBT tube Q1 to be detected caused by exceeding expected current is protected, namely, the situation that the IGBT tube Q1 to be detected reaches the maximum bearable junction temperature is avoided, and the overcurrent protection of the IGBT tube Q1 to be detected is realized.
When the withstand voltage of the TVS tube is smaller than the voltage between the grid G and the emitter E of the IGBT tube Q1 to be detected, the TVS tube breaks down, so that the resistor Rs generates voltage drop due to over-current, when the voltage drop at the two ends of the resistor Rs is larger than the threshold voltage of the MOS tube Q3, the MOS tube Q3 is started to clamp the voltages at the two ends of the grid G and the emitter E of the IGBT tube Q1 to be detected, and accordingly the grid G of the IGBT tube Q1 to be detected is prevented from being broken down due to the over-high voltages at the two ends of the grid G and the emitter E of the IGBT tube Q1 to be detected, namely the over-voltage protection of the IGBT tube Q1 to be detected is realized, and the reliability of a device is improved.
In this embodiment, the terminal region II includes a first terminal region a for forming the diode D and the resistor Rs, a second terminal region B for forming the TVS tube, and a third terminal region C for forming the MOS tube Q3. Wherein, TVS tube and MOS pipe Q3 all keep apart through isolation groove structure 217.
In detail, the substrate 100 of the first terminal area a is provided with a conductive area 105, the conductive area 105 is disposed near the cell area I and is disposed adjacent to the first gate 211 of the cell area I near the terminal area II, and the conductive area 105 extends from the upper surface to the lower surface into the substrate 100. A first field oxide layer 201 and a second field oxide layer 202 are disposed on the substrate 100 of the first termination region a at intervals, the first field oxide layer 201 is located on the conductive region 105 and is disposed close to the first well region 102, the second field oxide layer 202 is located at a boundary of the conductive region 105, and a conductive ring, such as a P-type conductive ring P-ring, is disposed in the substrate of the second field oxide layer 202 far from the first field oxide layer 201. Wherein the conductive region 105 has a first conductivity type, such as p-type. The diode is disposed on the first field oxide layer 201 and the resistor 214 is disposed on the second field oxide layer 202.
The substrate 100 of the second termination region B has a second doped region 109 and a first doped region 110 disposed adjacent to each other, a third field oxide layer 203 is disposed on the substrate 100 of the first doped region 110, the TVS tube is disposed on the third field oxide layer 203, the TVS tube includes a plurality of first sub-regions 2161 and a plurality of second sub-regions 2162, the first sub-regions 2161 and the second sub-regions 2162 are periodically disposed along the extending direction of the TVS tube, and the first region and the last region of the TVS tube in the extending direction of the third field oxide layer 203 are both the first sub-regions 2161 or both the second sub-regions 2162, that is, the conductivity types of the first region and the last region of the TVS tube in the extending direction of the TVS tube are the same. In this embodiment, the number of the first sub-region 2161 and the second sub-region 2162 depends on the voltage withstanding requirement between the gate G and the emitter E of the IGBT tube Q1 to be detected.
Wherein the first sub-region has a second conductivity type, i.e., n-type, and the second sub-region has a first conductivity type, i.e., p-type; the second doped region 109 has a first conductivity type, i.e., p-type, and the first doped region 110 has a second conductivity type, i.e., n-type. A third doped region 111 is provided in the substrate 100 of both the second doped region 109 and the first doped region 110, the third doped region 111 being of the second conductivity type, i.e. n-type.
Isolation trench structures 217 are provided in the substrate outside of the second doped region 109 and the first doped region 110 to isolate the region device from adjacent region devices.
The substrate 100 in the third terminal area C has a body area 112 and a drift area 113 that are adjacently disposed, a gate oxide layer is disposed at a junction between the body area 112 and the drift area 113, a fourth field oxide layer 204 is disposed on the substrate 100 on one side of the gate oxide layer, which is close to the drift area 113, a second gate 213 is disposed on the gate oxide layer, a field plate 215 is disposed on the fourth field oxide layer 204, an extraction area and a source area 107 are sequentially disposed in the body area 112 outside the second gate 213 from bottom to top, and an extraction area and a drain area 108 are sequentially disposed in the drift area 113 outside the second gate 213 from bottom to top.
Wherein, the body region 112 and the extraction region are of a first conductivity type, i.e. p-type, and the source region 107, the drain region 108 and the drift region 113 are of a second conductivity type, i.e. n-type.
Isolation trench structures 217 are provided in the substrate outside of the body region 112 and drift region 113 to isolate the region device from neighboring region devices. The isolation trench structure 217 includes an isolation trench disposed on the upper surface, a gate oxide layer is formed on an inner wall of the isolation trench, and the isolation trench is filled with a polysilicon material.
Referring to fig. 6-11, the method for manufacturing a semiconductor integrated chip according to the present embodiment includes the following steps:
step S21: providing a substrate 100, wherein the substrate 100 is provided with a cell area I and a terminal area II;
step S22: forming an IGBT tube Q1 to be detected and an IGBT tube Q2 to be detected in the cell region I, and forming a diode D, a resistor Rs, a MOS tube Q3 and a TVS tube in the terminal region II;
step S23: the detector is characterized in that the detector is electrically connected with a collector of the IGBT tube Q1 to be detected and a collector of the IGBT tube Q2 to be detected, the detector is electrically connected with a grid of the IGBT tube Q1 to be detected, a grid of the IGBT tube Q2 to be detected and a positive electrode of the diode D, the detector is electrically connected with an emitter of the IGBT tube Q2 to be detected, one end of the resistor Rs and a grid of the MOS tube Q3, the drain of the MOS tube Q3 is electrically connected with a negative electrode of the diode D, and the other end of the resistor Rs, a source of the MOS tube Q3 and the emitter of the IGBT tube Q1 to be detected are electrically connected.
As shown in fig. 9, in step S21, a CS layer (carrier storage layer) 101 is provided in the substrate 100 of the cell region I, a plurality of cell grooves disposed at intervals are formed in the substrate 100 of the cell region I, the cell grooves penetrate the upper surface and the bottom of the groove exposes the substrate 100 under the CS layer 101, and a gate oxide layer is provided on the inner wall of the cell groove. Wherein the CS layer 101 has a second conductivity type, e.g., n-type.
The terminal region II includes a first terminal region a for forming the diode D and the resistor Rs, a second terminal region B for forming the TVS tube, and a third terminal region C for forming the MOS tube Q3.
A conductive region 105 is disposed in the substrate 100 of the first terminal region a, the conductive region 105 being disposed adjacent to the cell region I and adjacent to the cell trench of the cell region I adjacent to the terminal region II, the conductive region 105 extending from the upper surface to the lower surface into the substrate 100. A first field oxide layer 201 and a second field oxide layer 202 are disposed on the substrate 100 of the first termination region a at intervals, the first field oxide layer 201 is located on the conductive region 105, the second field oxide layer 202 is located at a boundary of the conductive region 105, and a conductive ring, such as a P-type conductive ring P-ring, is disposed in the substrate of the second field oxide layer 202 away from the first field oxide layer 201. The diode is disposed on the first field oxide layer 201 and the resistor 214 is disposed on the second field oxide layer 202.
A first doped region 110 is disposed in the substrate 100 of the second terminal region B, a third field oxide layer 203 is disposed on the substrate 100 of the first doped region 110, and an isolation trench is disposed in the substrate 100 outside the first doped region 110. A drift region 113 is disposed in the substrate 100 of the third terminal region C, a gate oxide layer is disposed at a junction of one side of the drift region 113, an isolation trench is disposed in the substrate 100 outside the drift region 113, a fourth field oxide layer 204 is disposed on the substrate 100 of the drift region 113, and the fourth field oxide layer 204 is disposed adjacent to the gate oxide layer.
The step S22 specifically includes the following steps:
as shown in fig. 9, first, a semiconductor material layer 200 is formed on the upper surface of the substrate 100, and the semiconductor material layer 200 fills the cell trench and the isolation trench to cover the first field oxide layer 201, the second field oxide layer 202, the third field oxide layer 203, the fourth field oxide layer 204 and the gate oxide layer.
Next, a patterned first photoresist layer 400 is formed on the semiconductor material layer 200, wherein the patterned first photoresist layer 400 covers a portion of the first field oxide layer 201, a portion of the second field oxide layer 202, a portion of the gate oxide layer, a portion of the third field oxide layer 203, and a portion of the fourth field oxide layer 204.
As shown in fig. 10, the semiconductor material layer 200 is etched with the patterned first photoresist layer 400 as a mask to expose the first field oxide layer 201, the second field oxide layer 202, the third field oxide layer 203, the fourth field oxide layer 204 and the gate oxide layer outside the first photoresist layer 400, and form a first gate 211 in the cell trench, a resistor is formed on the second field oxide layer 202, an initial diode is formed on the first field oxide layer 201, a second gate 213 and a field plate 215 of the LDMOS tube are formed, an initial TVS tube and an isolation trench structure 217 are also formed, and finally the first photoresist layer 400 is removed.
Forming a patterned second photoresist layer, wherein the patterned second photoresist layer exposes a part of the first region of the initial polysilicon diode and a second subregion of the initial TVS tube, and performing ion implantation of a first conductivity type by taking the patterned second photoresist layer as a mask so as to form the polysilicon diode and the TVS tube; and finally, removing the second photoresist layer.
Wherein the first region 2121 and the second sub-region 2162 each have a second conductivity type.
As shown in fig. 11, next, a first well region 102 is formed in the substrate at both sides of the first gate electrode 211 through ion implantation, the first well region 102 extends into the substrate 100 from the upper surface toward the lower surface, and the CS layer 101 is adjacently disposed under the first well region 102. Meanwhile, a body region 112 is formed in the substrate 100 outside the drift region 113, the drift region 113 and the body region 112 are both disposed inside the isolation trench of the third termination region C, and a second doped region 109 is also formed in the substrate 100 outside the first doped region 110, and the first doped region 110 and the second doped region 109 are both disposed inside the isolation trench of the second termination region B.
Then, forming a lead-out area and an emission area in the first well areas 102 on two sides of the first grid electrode 211 of the IGBT tube Q1 to be detected sequentially from bottom to top through ion implantation, wherein only the lead-out area is formed in the first well areas 102 on two sides of the remaining first grid electrode 211 and the conductive area close to the cell area; a source region 107 is also formed in the body region 112 in order from bottom to top, a drain region 108 is formed in the drift region 113 in order from bottom to top, and a third doped region 111 is formed in the first doped region 110 and the second doped region 109.
Step S23: the detector is characterized in that the detector is electrically connected with a collector of the IGBT tube Q1 to be detected and a collector of the IGBT tube Q2 to be detected, the detector is electrically connected with a grid of the IGBT tube Q1 to be detected, a grid of the IGBT tube Q2 to be detected and a positive electrode of the diode D, the detector is electrically connected with an emitter of the IGBT tube Q2 to be detected, one end of the resistor Rs and a grid of the MOS tube Q3, the drain of the MOS tube Q3 is electrically connected with a negative electrode of the diode D, and the other end of the resistor Rs, a source of the MOS tube Q3 and the emitter of the IGBT tube Q1 to be detected are electrically connected. The method specifically comprises the following steps:
first, a first interlayer dielectric layer is formed on the upper surface, and covers the first grid electrode, the second grid electrode, the resistor, the TVS tube and the diode.
Next, a plurality of conductive pillars are formed in the first interlayer dielectric layer to draw out the source region, the drain region and the field plate, the first region and the second region of the diode, both ends of the resistor, the first gate and the emitter region, and both ends of the TVS tube.
Wherein the conductive pillars include three first conductive pillars 311, 312, 313, two second conductive pillars 321, 322, one third conductive pillar, two fourth conductive pillars, three fifth conductive pillars, two sixth conductive pillars, and two seventh conductive pillars 371, 372, one end of one first conductive pillar 311 extends into an emission region constituting an IGBT tube Q1 to be detected and stops in the extraction region to extract an emitter end of the IGBT tube Q1 to be detected, one end of two first conductive pillars 312, 313 extends into the first well region 102 and the conductive region 105 outside the first gate 211 near the terminal region II and stops in the extraction region; the two second conductive columns extend into a first grid electrode 211 forming the IGBT tube to be detected Q1 and a first grid electrode 211 forming the IGBT tube to be detected Q2 so as to lead out the grid electrodes of the IGBT tube to be detected Q1 and the IGBT tube to be detected Q2; one end of the third conductive pillar 330 extends into an emission region forming the detection IGBT tube Q2 and stops in the extraction region to extract the emitter of the detection IGBT tube Q2; the fourth conductive pillar 341 extends into the first region 2121 of the diode, and the fourth conductive pillar 342 extends into the second region 2122 of the diode to draw out the two poles of the diode D; three of the fifth conductive pillars 351, 352, 353 respectively lead out the second gate 213, the source region 107, and the drain region 108; the two sixth conductive pillars 361, 362 extend into the two ends of the resistor 214 to draw out the two ends of the resistor Rs, and the two seventh conductive pillars 371, 372 extend into the first sub-regions of the TVS pipe at the two ends to draw out the two ends of the TVS pipe.
In summary, the present invention provides a semiconductor integrated chip and a method for manufacturing the same, the semiconductor integrated chip includes a substrate, the substrate has a cell region and a termination region, the cell region is provided with an IGBT tube to be detected and a detection IGBT tube, and the termination region is provided with a diode, a resistor and a MOS tube; the collector of the IGBT tube to be detected is electrically connected with the collector of the IGBT tube to be detected, the grid of the IGBT tube to be detected is electrically connected with the grid of the IGBT tube to be detected and the anode of the diode at the same time, the emitter of the IGBT tube to be detected is electrically connected with one end of the resistor and the grid of the MOS tube at the same time, the drain of the MOS tube is electrically connected with the cathode of the diode, and the other end of the resistor is electrically connected with the source of the MOS tube and the emitter of the IGBT tube to be detected at the same time. According to the invention, the diode and the resistor are arranged in the terminal area, so that the overcurrent protection circuit is monolithically integrated on the semiconductor integrated chip, the chip integration level can be improved, the occupied area of the PCB is reduced, the short-circuit protection function (namely, the overcurrent protection function) is realized, the saturated current of the IGBT tube to be detected in the short circuit process is reduced, the heat damage of the IGBT tube to be detected due to the excessively high current is avoided, namely, the risk of breakdown of the IGBT tube to be detected is reduced, and the delay is also reduced.
Further, the terminal area II of the semiconductor integrated chip is further provided with a TVS tube, so that the terminal area is provided with a diode, a resistor, a MOS tube and a TVS tube, the integration level can be improved, the occupied area of a PCB (printed circuit board) is reduced, meanwhile, overcurrent protection and overvoltage protection are realized, the risk of breakdown of an IGBT (insulated gate bipolar transistor) chip is reduced, the time delay is reduced, and the reliability of the device is improved.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (12)

1. The semiconductor integrated chip is characterized by comprising a substrate, wherein the substrate is provided with a cell area and a terminal area, the cell area is provided with an IGBT tube to be detected and an IGBT tube to be detected, and the terminal area is provided with a diode, a resistor and a MOS tube;
the collector of the IGBT tube to be detected is electrically connected with the collector of the IGBT tube to be detected, the grid of the IGBT tube to be detected is electrically connected with the grid of the IGBT tube to be detected and the anode of the diode at the same time, the emitter of the IGBT tube to be detected is electrically connected with one end of the resistor and the grid of the MOS tube at the same time, the drain of the MOS tube is electrically connected with the cathode of the diode, and the other end of the resistor is electrically connected with the source of the MOS tube and the emitter of the IGBT tube to be detected at the same time.
2. The semiconductor integrated chip according to claim 1, wherein a first field oxide layer and a second field oxide layer are provided on the substrate at an interval in the termination region, the first field oxide layer is provided near the cell region, a diode is provided on the first field oxide layer, a resistor is provided on the second field oxide layer, and the MOS transistor is provided between the first field oxide layer and the second field oxide layer.
3. The semiconductor integrated chip according to claim 2, wherein the termination region is further provided with a TVS tube, one end of the TVS tube is electrically connected to the gate of the detection IGBT tube, and the other end of the TVS tube is electrically connected to the gate of the MOS tube.
4. The semiconductor integrated chip according to claim 3, wherein a withstand voltage of the TVS tube is lower than a withstand voltage requirement between a gate and an emitter of the IGBT tube to be detected, which is lower than a withstand voltage of the MOS tube.
5. The semiconductor integrated chip according to claim 4, wherein the terminal region includes a first terminal region, a second terminal region, and a third terminal region in this order from the cell region toward a direction away from the cell region, the diode and the resistor are both located in the first terminal region, the TVS transistor is disposed in the second terminal region by isolation trench structure isolation, and the MOS transistor is disposed in the third terminal region by isolation trench structure isolation.
6. The semiconductor integrated chip according to claim 5, wherein the MOS transistor is an LDMOS transistor.
7. The semiconductor integrated chip according to claim 6, wherein in the second termination region, a third field oxide layer and an isolation trench structure are formed on the substrate, the TVS tube is disposed on the third field oxide layer, the third field oxide layer is disposed inside the isolation trench structure of the second termination region; the TVS tube comprises a plurality of first subregions and a plurality of second subregions, wherein the first subregions and the second subregions are periodically arranged along the extending direction of the TVS tube, and in the extending direction of the TVS tube, the regions at two ends are both the first subregions or the second subregions, and the conductivity types of the first subregions and the second subregions are opposite.
8. A method of manufacturing a semiconductor integrated chip, comprising the steps of:
providing a substrate, wherein the substrate is provided with a cell area and a terminal area;
forming an IGBT tube to be detected and an IGBT tube to be detected in the cell region, and forming a diode, a resistor and an MOS tube in the terminal region;
the detector comprises a detector, a diode, a resistor, a diode, a resistor, a MOS tube, a collector electrode of the IGBT tube to be detected, a gate electrode of the diode, a source electrode of the MOS tube and an emitting electrode of the IGBT tube to be detected.
9. The method of manufacturing a semiconductor integrated chip according to claim 8, wherein the termination region has a first field oxide layer and a second field oxide layer disposed at intervals.
10. The method for manufacturing a semiconductor integrated chip as recited in claim 9, wherein,
the steps of forming the IGBT tube to be detected and the IGBT tube to be detected in the cell area and forming the diode, the resistor and the MOS tube in the terminal area are specifically as follows:
Forming a semiconductor material layer on the substrate, wherein the semiconductor material layer covers the first field oxide layer, the second field oxide layer and the cell region, and has an n-type conductivity;
forming a patterned first photoresist layer on the semiconductor material layer, etching the semiconductor material layer by taking the patterned first photoresist layer as a mask, forming a grid electrode of the IGBT tube to be detected and a grid electrode of the IGBT tube to be detected in the cell area, forming an initial diode on the first field oxide layer, forming a resistor on the second field oxide layer, forming a grid electrode of the MOS tube between the first field oxide layer and the second field oxide layer, and removing the first photoresist layer;
and carrying out p-type conductivity type ion implantation on a partial region of the initial diode to form the diode.
11. The method of manufacturing a semiconductor integrated chip according to claim 10, wherein the MOS transistor is an LDMOS transistor, the termination region includes a first termination region, a second termination region, and a third termination region in order from the cell region toward a direction away from the cell region, a first field oxide layer and a second field oxide layer are provided on a substrate of the first termination region at intervals, a third field oxide layer is provided on a substrate of the second termination region, a gate oxide layer and a fourth field oxide layer are provided on a substrate of the third termination region adjacently disposed, isolation trenches are provided in the substrates of the second termination region and the third termination region, the isolation trenches of the second termination region are provided around the outside of the third field oxide layer, and the isolation trenches of the third termination region are provided around the outside of the gate oxide layer and the fourth field oxide layer.
12. The method of manufacturing a semiconductor integrated chip according to claim 11, wherein the steps of forming the IGBT tube to be detected and the detection IGBT tube in the cell region, and forming the diode, the resistor, and the MOS tube in the terminal region are specifically:
forming a semiconductor material layer on the upper surface of the substrate, wherein the semiconductor material layer fills the isolation groove and also covers the cell region, the first field oxide layer, the second field oxide layer, the third field oxide layer, the fourth field oxide layer and the gate oxide layer, and the semiconductor material layer has an n-type conductivity type;
forming a patterned first photoresist layer on the semiconductor material layer, etching the semiconductor material layer by taking the patterned first photoresist layer as a mask, forming a grid electrode of the IGBT tube to be detected and a grid electrode of the IGBT tube to be detected by taking the cell area, forming an initial diode on the first field oxide layer, forming a resistor on the second field oxide layer, forming an initial TVS tube on the third field oxide layer, forming a field plate of an LDMOS tube on the fourth field oxide layer, forming a grid electrode of the LDMOS tube on the gate oxide layer, and removing the first photoresist layer;
and carrying out p-type conductivity type ion implantation on the partial region of the initial diode and the partial region of the initial TVS tube to form the diode and the TVS tube.
CN202311760751.9A 2023-12-20 2023-12-20 Semiconductor integrated chip and manufacturing method thereof Pending CN117594592A (en)

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