CN106057866A - Semiconductor device and manufacturing method of semiconductor device - Google Patents
Semiconductor device and manufacturing method of semiconductor device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A first parallel pn layer 5 having a first n-type region 3 and a first p-type region 4 junctioned alternately and repeatedly is disposed in an element active portion 10a. The first parallel pn layer 5 has a striped planar layout. A second parallel pn layer 15 having a second n-type region 13 and a second p-type region 14 junctioned alternately and repeatedly is disposed in a high voltage structure 10c. The second parallel pn layer 15 has a striped planar layout in a direction identical to that of the first parallel pn layer 5. An intermediate region 6 having a third parallel pn layer and a fourth parallel pn layer is disposed between the first 5 and second 15 parallel pn layers, and formed by diffusing impurity implanting regions becoming the first 5 and the second 15 parallel pn layers formed separated from each other to a region in which no impurity is ion-implanted.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device and semiconductor device.
Background technology
In the past, the semiconductor device being known to possess superjunction (SJ:Super Junction) structure is (following
It is referred to as super junction semiconductor device), this super-junction structure is to be set to drift layer in the side with chip main surface parallel
The pn layer arranged side by side of n-type region and the p-type area that improve impurity concentration alternately it is configured with to (laterally)
Form.In super junction semiconductor device, the n-type region of current flowing pn arranged side by side layer during conducting state, cut
Only during state, depletion layer also extends from the pn-junction between n-type region and the p-type area of pn layer arranged side by side and makes
N-type region and p-type area exhaust, and load is pressure.It addition, in super junction semiconductor device, due to
The impurity concentration of drift layer can be improved, it is possible to reduce conducting resistance when maintaining height pressure.
As such super junction semiconductor device, it is proposed that possess from element active portion to pressure-resistance structure portion
In the range of the plane figure of striated that is configured to n-type area with p-type area to extend with identical width form
The device (for example, referring to following patent documentation 1 (the 0020th section, Fig. 1, Fig. 2)) of pn layer arranged side by side.
In following patent documentation 1, lived than element by the impurity concentration making the pn layer arranged side by side in pressure-resistance structure portion
The impurity concentration of the pn layer arranged side by side in property portion is low, so that the element active of the resistance to pressure ratio portion in pressure-resistance structure portion
Pressure height.There is the region of current flowing in element active portion when being conducting state.Component periphery portion embracing element
Around active portion.Pressure-resistance structure portion is configured at component periphery portion, be relax chip front side side electric field and
Keep pressure region.
It addition, as another super junction semiconductor device, it is proposed that side by side pn layer n-type region and
The repetition pitch of p-type area arranges than device (example narrow in element active portion in pressure-resistance structure portion
As, with reference to following patent documentation 2 (the 0023rd section, Fig. 6) and following patent documentation 3 the (the 0032nd
Section, Fig. 1, Fig. 2)).In following patent documentation 2, it is all provided with in element active portion and pressure-resistance structure portion
Put the pn layer arranged side by side of the plane figure that n-type region and p-type area are configured to striated.Following
In patent documentation 3, arrange in element active portion and n-type region and p-type area are configured to the flat of strip
The pn layer arranged side by side of face layout, is arranged p-type area in pressure-resistance structure portion with rectangular plane figure configuration
Pn layer arranged side by side in n-type region.
It addition, as another super junction semiconductor device, it is proposed that by n-type region and the p of pn layer arranged side by side
Type region is configured to the plane figure of striated, make the n-type region of pn layer arranged side by side in pressure-resistance structure portion with
And the horizontal width (hereinafter simply referred to as width) orthogonal with striped of p-type area partly change and
The device (for example, referring to following patent documentation 4) obtained.It addition, as another superjunction quasiconductor
Device, it is proposed that the n-type region of pn layer arranged side by side and p-type area are configured to the plane figure of striated,
With the border in pressure-resistance structure portion near, by the width of the p-type area of the pn layer arranged side by side in element active portion
The device that becomes narrow gradually towards outside (for example, referring to following patent documentation 5 (the 0051st section, Figure 18,
Figure 19)).
In following patent documentation 2～5, by element active portion and pressure-resistance structure portion, change side by side
The width of the p-type area of the n-type region of pn layer and the repetition pitch of p-type area and/or pn layer arranged side by side,
So that the impurity concentration of the pn layer arranged side by side in pressure-resistance structure portion is than the pn layer arranged side by side in element active portion
Impurity concentration is low.Therefore, in the same manner as following patent documentation 1, the element of resistance to pressure ratio in pressure-resistance structure portion is lived
The pressure height in property portion.
As the forming method of pn layer arranged side by side, propose to have below scheme: at the layer by epitaxial growth every time
During folded undoped layer, all whole face is carried out the ion implanting of p-type impurity, use photoresistive mask to select
Property ground carried out n-type impurity ion implanting after, make impurity spread (such as, ginseng by heat treatment
According to the reference of following patent documentation 6 (the 0025th section, Fig. 1～Fig. 4)).In following patent documentation 6,
In view of follow-up thermal diffusion step, for the A/F of photoresistive mask of the ion implanting of n-type impurity
For remaining about the 1/4 of width, correspondingly, the injection rate of n-type impurity is set to p-type impurity
About 4 times of injection rate, so that the n-type region of pn layer arranged side by side and the total impurities amount phase of p-type area
Deng.
As another forming method of pn layer arranged side by side, propose to have below scheme: every time raw by extension
During long and stacking N-shaped resistive formation, different photoresistive mask is all used respectively selectively to carry out N-shaped
After the ion implanting of impurity and n-type impurity, made by heat treatment impurity diffusion (for example, referring to
Following patent documentation 7 (the 0032nd～0035 section, Fig. 4) reference).In following patent documentation 7, make
The p-type impurity injection zone becoming the n-type region of pn layer arranged side by side and the n-type impurity becoming p-type area note
Enter region to be formed selectively in the way of transversely opposed and to carry out thermal diffusion.Therefore, it is possible to make N-shaped
Region and the equal high impurity concentration of p-type area, and the pn between the region being laterally abutted can be suppressed
The deviation of the impurity concentration near knot.
Prior art literature
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Publication 2008-294214 publication
Patent documentation 2: Japanese Unexamined Patent Publication 2002-280555 publication
Patent documentation 3: Japan internationality discloses No. 2013/008543
Patent documentation 4: Japanese Unexamined Patent Publication 2010-056154 publication
Patent documentation 5: Japanese Unexamined Patent Publication 2012-160752 publication
Patent documentation 6: Japanese Unexamined Patent Publication 2011-192824 publication
Patent documentation 7: Japanese Unexamined Patent Publication 2000-040822 publication
Summary of the invention
Technical problem
But, the inventors of the present invention have carried out the result new discovery studied with keen determination, such as above-mentioned patent literary composition
Offer 7 like that, respectively selectively carry out p-type impurity and the ion implanting of n-type impurity and at element
In the case of active portion and pressure-resistance structure portion form pn layer arranged side by side, produce following problem.Figure 27,
Figure 28 is the top view of the plane figure of the pn layer arranged side by side representing conventional super junction semiconductor device.Figure 27
A (), Figure 28 (a) show plane figure when completing of pn layer arranged side by side.Figure 27 (a), Figure 28
A () shows conventional super junction semiconductor device 1/4 part.Figure 27 (b), Figure 28 (b)
In show in the borderline region 100b between element active portion 100a and pressure-resistance structure portion 100c arranged side by side
State in the forming process of pn layer.Component periphery portion 100d is by borderline region 100b and pressure-resistance structure
Portion 100c is constituted.At Figure 27, Tu28Zhong, the extension of the striped of pn layer arranged side by side is laterally set to y,
Orthogonal with striped is laterally set to x.Symbol 101 is to form pn layer arranged side by side and epitaxially grown n-
Type semiconductor layer.
As shown in Figure 27 (a), Figure 28 (a), in conventional super junction semiconductor device, element active
The pn layer arranged side by side (hereinafter referred to as the first pn layer arranged side by side) 104 and pressure-resistance structure portion 100c of portion 100a
Pn layer arranged side by side (hereinafter referred to as the second pn layer arranged side by side) 114 each extend to element active portion 100a with
Borderline region 100b between pressure-resistance structure portion 100c and adjoin each other.Such as Figure 27 (b), Figure 28 (b)
Shown in, when forming this first pn layer 104, second pn layer 114 arranged side by side arranged side by side, the first pn layer arranged side by side
The p-type impurity injection zone 121 becoming the first n-type region 102 of 104 and become the first p-type area
To extend to the inner side of borderline region 100b (live respectively by element for the n-type impurity injection zone 122 in territory 103
Property 100a side, portion) the mode of first area 100e formed.Second pn layer 114 arranged side by side become second
The p-type impurity injection zone 131,141 of n-type region 112,115, and become the second p-type area 113,
The n-type impurity injection zone 132,142 of 116 is (resistance to extend to the outside of borderline region 100b respectively
100c side, laminated structure portion) the mode of second area 100f formed.These each impurity injection zones are respectively
Till extending to the border (vertical dotted line) of first area 100e and second area 100f.
As shown in figure 27, by the first n-type region 102 and repetition pitch of the first p-type area 103
P11 and the second n-type region 112 and the second p-type area 113 repeat pitch P12 and are set to identical feelings
Under condition (P11=P12), in borderline region 100b, the first pn layer 104, second pn arranged side by side arranged side by side
The same conductive area of layer 114 is the state completely attached to each other.That is, become the first n-type region 102,
The p-type impurity injection zone 121,131 of the second n-type region 112 each other and becomes the first p-type area
103, the n-type impurity injection zone 122,132 of the second p-type area 113 is configured at separately from each other from unit
Part active portion 100a extends to pressure-resistance structure portion 100c and the plane figure of continuous print striated.Therefore,
In borderline region 100b, the charge balance of the first pn layer 104, second pn layer 114 arranged side by side arranged side by side does not has
Have destroyed, and the mean impurity concentration of the first pn layer 104, second pn layer 114 arranged side by side arranged side by side is homogeneous
With, thus element active portion 100a and pressure-resistance structure portion 100c does not produce resistance to pressure reduction.Accordingly, there exist as
Under problem, in pressure-resistance structure portion, 100c is prone to concentration of local electric field, resistance to by pressure-resistance structure portion 100c
Pressure determines the pressure of element entirety.
On the other hand, as shown in figure 28, by the second n-type region 115 and the second p-type area 116
Repetition pitch P12 be set to than the first n-type region 102 and repetition pitch of the first p-type area 103
In the case of P11 is narrow (P11 ＞ P12), the first pn layer 104, second pn layer 114 arranged side by side arranged side by side same
The cycle that conductive area contacts with each other determines based on mutual repetition pitch P11, the ratio of P12.That is,
In borderline region 100b, become the p-type impurity of first n-type region the 102, second n-type region 115
Injection zone 121,141 each other and becomes first p-type area the 103, second p-type area 116
N-type impurity injection zone 122,142 is in position and the state of discontiguous position that there is contact each other.
Therefore, uprise in borderline region 100b p-type impurity concentration and n-type impurity Concentration portion.Such as,
Near contacting with each other continuous print position 143 at n-type impurity injection zone 122,142, with adjacent
Distance between p-type impurity injection zone 121,141 is different, thus n-type impurity concentration compares p-type impurity
Concentration is high.Accordingly, there exist and be difficult to ensure that the first pn layer 104 arranged side by side and limit of the second pn layer 114 arranged side by side
Charge balance in boundary, the problem of the pressure part ground step-down of borderline region 100b.For this problem, logical
Cross the mean impurity concentration relative reduction making the first pn layer 104, second pn layer 114 arranged side by side arranged side by side, energy
Enough suppression pressure part ground step-downs, but pressure also reduction of element entirety.
The present invention is to solve above-mentioned problem of the prior art, its object is to provide one to reduce
Conducting resistance, and the semiconductor device of pressure reduction and the manufacture method of semiconductor device can be suppressed.
Technical scheme
In order to solve above-mentioned problem, it is achieved the purpose of the present invention, so the semiconductor device of the present invention has
Following feature.First interarea side is provided with surface element structure.Second interarea side is provided with low electricity
Resistance layer.The first pn layer arranged side by side it is provided with, with bag between above-mentioned surface element structure and above-mentioned conductive formation
The mode placing the surrounding stating the first pn layer arranged side by side is provided with the second pn layer arranged side by side.Above-mentioned first pn arranged side by side
Layer is that first the first conductive area and first the second conductive area are alternately configured and formed.
Above-mentioned second pn layer arranged side by side is by second the first conductive area and second the second conductive area
With than above-mentioned first the first conductive area and the repetition pitch of above-mentioned first the second conductive area
Narrow pitch alternately configures and forms.Between the above-mentioned first pn layer arranged side by side and the above-mentioned second pn layer arranged side by side,
It is provided with zone line in the way of contacting with the above-mentioned first pn layer arranged side by side and the above-mentioned second pn layer arranged side by side.
At above-mentioned zone line, there is the 3rd the second conductive area and the 4th the second conductive area.On
State above-mentioned first second conductivity type district of the 3rd the second conductive area and the above-mentioned first pn floor arranged side by side
Territory contacts, and mean impurity concentration is lower than above-mentioned first the second conductive area.Above-mentioned 4th
Two conductive areas contact with above-mentioned second second conductive area of the above-mentioned second pn layer arranged side by side, and
Mean impurity concentration is lower than above-mentioned second the second conductive area.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, above-mentioned mesozone
Territory has the 3rd the first conductive area and the 4th the first conductive area.Lead for above-mentioned 3rd first
Electricity type region contacts with above-mentioned first first conductive area of the above-mentioned first pn layer arranged side by side, and averagely
Impurity concentration is lower than above-mentioned first the first conductive area.Above-mentioned 4th the first conductive area is with upper
State above-mentioned second first conductive area contact of the second pn layer arranged side by side, and mean impurity concentration ratio is upper
State second the first conductive area low.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, in above-mentioned centre
Region is configured with above-mentioned 3rd the first conductive area and above-mentioned 3rd the second conductive area replaces
3rd pn layer arranged side by side of ground configuration.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, in above-mentioned centre
Region is configured with above-mentioned 4th the first conductive area and above-mentioned 4th the second conductive area replaces
4th pn layer arranged side by side of ground configuration.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, have further
Following characteristics.Above-mentioned first the first conductive area and above-mentioned first the second conductive area configuration
Plane figure for striated.Above-mentioned second the first conductive area and above-mentioned second second conduction
Type region be configured to towards with above-mentioned first the first conductive area and above-mentioned first the second conductivity type
The plane figure of the striated that region is identical.Above-mentioned 3rd the second conductive area and above-mentioned 4th
Second conductive area be configured to towards with above-mentioned first the second conductive area and above-mentioned second
The plane figure of the striated that two conductive areas are identical.
It addition, the semiconductor device of the present invention is characterised by, in above-mentioned invention, center is opposed
Above-mentioned 3rd the second conductive area and above-mentioned 4th the second conductive area are adjacent across drift region.
It addition, the semiconductor device of the present invention has following characteristics in above-mentioned invention further.Above-mentioned
First the first conductive area and above-mentioned first the second conductive area are configured to the plane of striated
Layout.Above-mentioned second the first conductive area and above-mentioned second the second conductive area are configured to court
To the striped orthogonal with above-mentioned first the first conductive area and above-mentioned first the second conductive area
The plane figure of shape.Above-mentioned 3rd the second conductive area is configured to lead towards with above-mentioned first second
The plane figure of the striated that electricity type region is identical.Above-mentioned 4th the second conductive area be configured to towards
The plane figure of the striated identical with above-mentioned second the second conductive area.
It addition, the semiconductor device of the present invention is in above-mentioned invention, there is following characteristics further.On
State surface element structure and the above-mentioned first pn layer arranged side by side and when being configured at conducting state, have the unit of current flowing
Part active portion.Above-mentioned second pn layer arranged side by side is configured at the component periphery portion surrounding said elements active portion.?
The opposite side relative to said elements active portion side of said elements periphery, above-mentioned first interarea with
Between above-mentioned conductive formation, it is provided with terminal area.In the above-mentioned second pn layer arranged side by side and above-mentioned terminal area
Between, it is provided with five first lower than above-mentioned second the first conductive area of mean impurity concentration and leads
Electricity type region.Conductive layer electrically connects with above-mentioned terminal area.
It addition, in order to solve above-mentioned problem, it is achieved the purpose of the present invention, the semiconductor device of the present invention
Manufacture method there is following characteristics.First, carry out first operation, the formation of second operation are repeated
Operation.In above-mentioned first operation, pile up the first conductive-type semiconductor layer.In above-mentioned second operation,
At the surface layer of above-mentioned first conductive-type semiconductor layer, formed first the first conductive-type impurity injection zone,
First the second conductive-type impurity injection zone, second the first conductive-type impurity injection zone and second
Individual second conductive-type impurity injection zone.Above-mentioned first the first conductive-type impurity injection zone and above-mentioned
First the second conductive-type impurity injection zone alternately configures.Above-mentioned second the first conductive-type impurity note
Enter region and above-mentioned second the second conductive-type impurity injection zone than above-mentioned first the first conductivity type
Impurity injection zone and the more outward position of above-mentioned first the second conductive-type impurity injection zone are with upper
State first the first conductive-type impurity injection zone and above-mentioned first the second conductive-type impurity injection zone
Separate with preset width.Above-mentioned second the first conductive-type impurity injection zone and above-mentioned second second
Conductive-type impurity injection zone is with than above-mentioned first the first conductive-type impurity injection zone and above-mentioned first
The pitch that the repetition pitch of individual second conductive-type impurity injection zone is narrow alternately configures.Then, heat is carried out
Treatment process.In above-mentioned heat treatment step, make above-mentioned first the first conductive-type impurity injection zone with
And above-mentioned first second conductive-type impurity injection zone diffusion and formed first the first conductive area with
And the first pn layer arranged side by side that first the second conductive area alternately configures.Make above-mentioned second
One conductive-type impurity injection zone and above-mentioned second the second conductive-type impurity injection zone spread and are formed
Second the first conductive area and second the second conductive area alternately configure second also
Row pn layer.Further, in above-mentioned heat treatment step, at the above-mentioned first pn layer arranged side by side with above-mentioned second also
Between row pn layer, make above-mentioned first the first conductive-type impurity injection zone, above-mentioned first second conduction
Type impurity injection zone, above-mentioned second the first conductive-type impurity injection zone and above-mentioned second second
Conductive-type impurity injection zone spreads, and is formed and has mean impurity concentration than above-mentioned first the first conductivity type
Low the 3rd the first conductive area, the mean impurity concentration in region is than above-mentioned first the second conductivity type district
Low the 3rd the second conductive area, the mean impurity concentration in territory is than above-mentioned second the first conductive area
The 4th low the first conductive area and upper mean impurity concentration ratio state second the second conductive area
The zone line of the 4th low the second conductive area.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned heat treatment step, formed and have above-mentioned 3rd the first conductive area and the above-mentioned 3rd
The 3rd pn layer arranged side by side that individual second conductive area alternately configures and above-mentioned 4th first is led
The 4th pn layer arranged side by side that electricity type region and above-mentioned 4th the second conductive area alternately configure
Above-mentioned zone line.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned second operation, by above-mentioned first the first conductive-type impurity injection zone and above-mentioned first
Second conductive-type impurity injection zone is formed as the plane figure of striated, and by above-mentioned second first
Conductive-type impurity injection zone and above-mentioned second the second conductive-type impurity injection zone are formed as with above-mentioned
First the first conductive-type impurity injection zone and above-mentioned first the second conductive-type impurity injection zone phase
With towards the plane figure of striated.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned second operation, by above-mentioned first the first conductive-type impurity injection zone and above-mentioned first
Two conductive-type impurity injection zones are formed as the plane figure of striated, and lead above-mentioned second first
Electricity type impurity injection zone and above-mentioned second the second conductive-type impurity injection zone are formed towards with upper
State first the first conductive-type impurity injection zone and above-mentioned first the second conductive-type impurity injection zone
The plane figure of orthogonal striated.
It addition, in order to solve above-mentioned problem, it is achieved the purpose of the present invention, the semiconductor device of the present invention
Manufacture method there is following characteristics.First, carry out repeating the first operation, the formation of the second operation
Operation.In above-mentioned first operation, pile up the first conductive-type semiconductor layer.In above-mentioned second operation,
At the surface layer of above-mentioned first conductive-type semiconductor layer, in the way of alternately configuring, form first second
Conductive-type impurity injection zone, and than above-mentioned first the second conductive-type impurity injection zone more outward
The position that side separates with preset width, with the repetition than above-mentioned first the second conductive-type impurity injection zone
Pitch second the second conductive-type impurity injection zone of formation that pitch is narrow.It follows that carry out following heat
Treatment process, by heat treatment, makes above-mentioned first the second conductive-type impurity injection zone diffusion be formed
First the second conductive area and above-mentioned first conductive-type semiconductor layer alternately configure first also
Row pn layer, and make above-mentioned second the second conductive-type impurity injection zone diffusion form second second
The second pn layer arranged side by side that conductive area and above-mentioned first conductive-type semiconductor layer alternately configure.?
In above-mentioned heat treatment step, between the above-mentioned first pn layer arranged side by side and the above-mentioned second pn layer arranged side by side, make
State first the second conductive-type impurity injection zone and above-mentioned second the second conductive-type impurity injection zone
Diffusion and form have that mean impurity concentration is lower than above-mentioned first the second conductive area the 3rd second
Conductive area and four lower than above-mentioned second the second conductive area of mean impurity concentration
The zone line of two conductive areas.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned second operation, above-mentioned first the second conductive-type impurity injection zone is formed as striated
Plane figure, and above-mentioned second the second conductive-type impurity injection zone is formed towards and above-mentioned
The plane figure of the striated that one the second conductive-type impurity injection zone is identical.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
In above-mentioned second operation, above-mentioned first the second conductive-type impurity injection zone is formed as striated
Plane figure, and above-mentioned second the second conductive-type impurity injection zone is formed towards and above-mentioned
The plane figure of the striated that one the second conductive-type impurity injection zone is orthogonal.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
Above-mentioned preset width is the thickness of above-mentioned first conductive-type semiconductor layer piled up in the most above-mentioned first operation
Less than the 1/2 of degree.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
The conductive formation that above-mentioned first conductive-type semiconductor layer of resistance ratio is low is formed the above-mentioned first pn layer arranged side by side
And the above-mentioned second pn layer arranged side by side.After above-mentioned heat treatment step, in the phase of the above-mentioned first pn layer arranged side by side
Opposite side for above-mentioned conductive formation side forms surface element structure.
It addition, the manufacture method of the semiconductor device of the present invention is characterised by, in above-mentioned invention,
The element active portion of current flowing is had, by above-mentioned when above-mentioned first pn layer arranged side by side is formed at conducting state
Two pn layers arranged side by side are formed at the component periphery portion surrounding said elements active portion.
According to above-mentioned invention, by becoming the impurity injection zone of the first pn layer arranged side by side and becoming second
Form, between the impurity injection zone of pn layer, the region not carrying out ion implanted impurity side by side, make each impurity note
Enter region thermal diffusion to this region, it is possible at the first pn layer arranged side by side and the second pn interlayer arranged side by side, form tool
The 3rd pn layer arranged side by side that standby mean impurity concentration is lower than the first pn layer arranged side by side, and mean impurity concentration ratio the
The zone line of the 4th pn layer arranged side by side that two pn layers arranged side by side are low.Further, since the impurity level of zone line
Lower than the impurity level of the first pn layer arranged side by side, so being prone to exhaust compared with the first pn layer arranged side by side, electric field is not
Easily concentrate.Therefore, at pressure-resistance structure portion (terminal side part in component periphery portion) configuration and element active
Portion compares the second pn layer arranged side by side that the repetition pitch of n-type region and p-type area is narrower, even if by pressure
It is pressure high, between element active portion and pressure-resistance structure portion that structural portion pressure is set to than element active portion
Borderline region in the most there is not pressure reduction.Therefore, it is possible to respectively adjust the first pn layer arranged side by side, second
The side by side charge balance of pn layer, thus resistance to by component periphery portion (pressure-resistance structure portion and borderline region)
It is pressure high that pressure is set to than element active portion, makes element entirety be prone to high pressureization.Even if it addition, increasing
The mean impurity concentration of the first pn layer arranged side by side and realize low on-resistance, it is also possible to maintain component periphery portion
Resistance to pressure reduction with element active portion.
Invention effect
Semiconductor device according to the present invention and the manufacture method of semiconductor device, play to reduce and lead
Energising resistance, and the effect of pressure reduction can be suppressed.
Accompanying drawing explanation
Fig. 1 is the top view of the plane figure of the semiconductor device representing embodiment 1.
Fig. 2 is the top view being amplified in the X1 portion of Fig. 1 and illustrating.
Fig. 3 is the sectional view of the cross section structure of the line of cut A-A' representing Fig. 1.
Fig. 4 is the sectional view of the cross section structure of the line of cut B-B' representing Fig. 1.
Fig. 5 is the sectional view of the cross section structure of the line of cut C-C' representing Fig. 1.
Fig. 6 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 7 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 8 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Fig. 9 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Figure 10 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Figure 11 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Figure 12 is the top view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Figure 13 is the top view of the state in the manufacture process of the semiconductor device representing embodiment 1.
Figure 14 is the cross section of an example in the element active portion of the semiconductor device representing embodiment 1
Figure.
Figure 15 is the cross section of another example in the element active portion of the semiconductor device representing embodiment 1
Figure.
Figure 16 is the top view being amplified in the X1 portion of Fig. 1 and illustrating.
Figure 17 is the sectional view of the cross section structure of the line of cut A-A' representing Fig. 1.
Figure 18 is the sectional view of the cross section structure of the line of cut B-B' representing Fig. 1.
Figure 19 is the sectional view of the cross section structure of the line of cut C-C' representing Fig. 1.
Figure 20 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 21 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 22 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 23 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 24 is the sectional view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 25 is the top view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 26 is the top view of the state in the manufacture process of the semiconductor device representing embodiment 2.
Figure 27 is the top view of the plane figure of the pn layer arranged side by side representing conventional super junction semiconductor device.
Figure 28 is the top view of the plane figure of the pn layer arranged side by side representing conventional super junction semiconductor device.
Figure 29 is the top view of the plane figure of the semiconductor device representing embodiment 3.
Figure 30 is the top view being amplified in the X2 portion of Figure 29 and illustrating.
Figure 31 is the top view being amplified in the X3 portion of Figure 29 and illustrating.
Figure 32 is the sectional view of the cross section structure of the line of cut D-D' representing Figure 29.
Figure 33 is the sectional view of the cross section structure of the line of cut E-E' representing Figure 29.
Symbol description
1 n+Type drop ply
2 N-type buffer layer
3,83 first n-type region
4,84 first p-type area
5,85 first pn layer arranged side by side
6 first pn layers arranged side by side and the zone line of the second pn interlayer arranged side by side
7 p-type bases
8 source electrodes
9 drain electrodes
10a element active portion
10b borderline region
10c pressure-resistance structure portion
10d component periphery portion
10e first area
10f second area
10g the 3rd region
12 n-Type region
13 second n-type region
14 second p-type area
15 second pn layers arranged side by side
16 n-type channel stop zones
17 p-type most peripheral regions
18 channel stop electrodes
19 interlayer dielectrics
21a～21f n-Type semiconductor layer
22a～22e, 42a n-type impurity injection zone
23a～23e, 43a p-type impurity injection zone
24 epitaxial layers
31,33 photoresistive mask
32,34 ion implanting
41 the 3rd n-type region
42 the 3rd p-type area
43 the 3rd pn layers arranged side by side
44 the 4th n-type region
45 the 4th p-type area
46 the 4th pn layers arranged side by side
47 transition regions
51,61 n+Type source region
52,62 p+Type contact area
53,64 gate insulating films
54,65 gate electrodes
63 grooves
70 n-type region
71a～71f n-type semiconductor layer
The repetition pitch of P1 first pn layer arranged side by side
The repetition pitch of P2 second pn layer arranged side by side
Y is clipped in the interval between the position that the first p-type area is opposed with the center of the second p-type area
A1, b1 are clipped in the district between the position that the first p-type area is opposed with the center of the second p-type area
Between the region of the first pn layer arranged side by side
A2, b2 are clipped in the district between the position that the first p-type area is opposed with the center of the second p-type area
Between zone line
A3, b3 are clipped in the district between the position that the first p-type area is opposed with the center of the second p-type area
Between the region of the second pn layer arranged side by side
A1', a2', a3', b1', b2', b3' midpoint
D1 is formed at p-type impurity injection zone and the interval of n-type impurity injection zone in element active portion
D2 is formed at p-type impurity injection zone and the interval of n-type impurity injection zone in pressure-resistance structure portion
w1 n-The width in type region
The width in w2 pressure-resistance structure portion
The width of the part being configured at pressure-resistance structure portion of w3 second pn layer arranged side by side
The width of the zone line between w4 first pn layer arranged side by side and the second pn layer arranged side by side
t n-The thickness of type semiconductor layer
Horizontal (second direction) that x is orthogonal with the striped of pn layer arranged side by side
Horizontal (first direction) of the extension of the striped of y pn arranged side by side layer
Z depth direction
Detailed description of the invention
Hereinafter, referring to the drawings, to the manufacture method of the semiconductor device of the present invention and semiconductor device
Preferred implementation is described in detail.In this specification and accompanying drawing, it is embroidered with n's or p front
In layer and region, represent that electronics or hole are majority carrier respectively.It addition, be marked on n, p
+ and-expression and unlabelled layer and region are in a ratio of impurity concentration height and impurity concentration is low respectively.Should
Give explanation, in the explanation and accompanying drawing of following embodiment, identical constituted the symbol that mark is identical,
And the repetitive description thereof will be omitted.
(embodiment 1)
For the structure of the semiconductor device of embodiment 1, to possess the n-channel type of super-junction structure
MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated-gate type field effect
Transistor) as a example by illustrate.Fig. 1 is the plane figure of the semiconductor device representing embodiment 1
Top view.Fig. 2 is the top view being amplified in the X1 portion of Fig. 1 and illustrating.Fig. 3 is to represent cutting of Fig. 1
The sectional view of the cross section structure of secant A-A'.Fig. 4 is the cross section structure of the line of cut B-B' representing Fig. 1
Sectional view.Fig. 5 is the sectional view of the cross section structure of the line of cut C-C' representing Fig. 1.
Fig. 1 shows the first pn layer arranged side by side of transversal element active portion 10a and component periphery portion 10d
5, the plane of the second pn layer 15 arranged side by side, such as, be positioned at the first pn layer 5 arranged side by side of element active portion 10a
The degree of depth 1/2 at the shape of plane.Element active portion 10a has current flowing when being conducting state
Region.Around component periphery portion 10d embracing element active portion 10a.It addition, for a clear and definite n
Type region (first the first conductive area) 3 and first p-type area (first the second conductivity type
Region) 4 repetition pitch P1 and the second n-type region (second the first conductive area) 13 and
Repetition pitch P2 of two p-type area (second the second conductive area) 14 is different, makes to show in Fig. 1
The number in these regions gone out is fewer than Fig. 3.
As shown in Fig. 1～5, the semiconductor device of embodiment 1 possesses element active portion 10a and surrounds unit
The component periphery portion 10d of the surrounding of part active portion 10a.The first interarea (chip at element active portion 10a
Front) side, as the Facad structure of element be provided with mos gate that diagram omits (by metal-oxide film-
The insulated gate that quasiconductor is constituted) structure.In unit, the second interarea side of part active portion 10a is provided with n+Type
Drop ply (conductive formation) 1, with n+Type drop ply 1 compares the position that distance the second interarea (chip back) is deep
Install and be equipped with N-type buffer layer 2.At second interarea of element active portion 10a, it is provided with and n+Type drop ply 1
The drain electrode 9 of contact.N-type buffer layer 2, n+Type drop ply 1 and drain electrode 9 are set to from element active
Portion 10a extends to component periphery portion 10d.
In element active portion 10a, between mos gate structure and N-type buffer layer 2, it is provided with first
Pn layer 5 side by side.First pn layer 5 arranged side by side is that the first n-type region 3 and the first p-type area 4 are with
The direction (laterally) of one main surface parallel is alternately repeated joint and is formed.First n-type region 3 and a p
The plane figure in type region 4 is striated.First n-type region 3 and a p of the first pn layer 5 arranged side by side
Outermost (side, chip end) e.g. first n-type region 3 of the part that type region 4 is repeated, should
Outermost first n-type region 3 in the direction orthogonal with the striped of the first pn layer 5 arranged side by side across described later
Zone line 6 is opposed with the such as second p-type area 14 of the second pn layer 15 arranged side by side.First pn arranged side by side
Layer 5 the first pn layer 5 arranged side by side striped extension direction and the direction orthogonal with striped, be set to from
Element active portion 10a extends to the borderline region 10b between element active portion 10a and pressure-resistance structure portion 10c.
By borderline region 10b and pressure-resistance structure portion 10c composed component periphery 10d.Component periphery portion 10d
E.g. more outward than the outboard end of the gate electrode being configured at outermost mos gate structure region,
Or it is configured with n in the outside of this gate electrode+Than this n in the case of type source region+The outboard end of type source region
More outward region.Pressure-resistance structure portion 10c is embracing element active portion 10a across borderline region 10b
Around, it is to relax the electric field of chip front side side and keep pressure region.Pressure-resistance structure portion 10c is such as
It is than be arranged in the region that the outboard end of outermost p-type base 7 is more outward.In pressure-resistance structure portion
10c, is provided with the second pn layer 15 arranged side by side on N-type buffer layer 2.Second pn layer 15 arranged side by side is second
N-type region 13 and the second p-type area 14 form laterally alternately repeating joint.
The plane figure of the second n-type region 13 and the second p-type area 14 is striated.Second is arranged side by side
The striped of pn layer 15 towards with the striped of the first pn layer 5 arranged side by side towards identical.Hereinafter, by first
What the striped of pn layer 5, second pn layer 15 arranged side by side extended side by side is laterally set to first direction y, will be with bar
Orthogonal horizontal (i.e. orthogonal with first direction y is horizontal) of stricture of vagina is set to second direction x.Second n-type area
Repetition pitch P2 of territory 13 and the second p-type area 14 is than the first n-type region 3 and the first p-type area
Repetition pitch P1 in territory 4 is narrow.Thus, the second n-type area 13 and the second p-type area 14 is the most miscellaneous
Matter concentration is lower than the mean impurity concentration of the first n-type region 3 and the first p-type area 4 respectively.Due to
Second n-type region 13 and the second p-type area 14 respectively with the first n-type region 3 and the first p-type
Region 4 concurrently forms, so by envoy away from narrower, thus mean impurity concentration step-down, second also
Row pn layer 15 depletion layer is prone to extend to peripheral direction, it is easy to make the most pressure height pressureization.Second
P-type area 14 is until exhausting and playing the effect identical with protection ring.Thus, the second n-type region 13
Electric field be alleviated, be thus susceptible to make high pressureization of pressure-resistance structure portion 10c.
The direction and with striped just that second pn layer 15 arranged side by side extends at the striped of the second pn layer 15 arranged side by side
The direction handed over is arranged in the way of extending to borderline region 10b from pressure-resistance structure portion 10c.It addition, second
Pn layer 15 surrounds the first pn layer 5 arranged side by side around across zone line 6 side by side, and via mesozone
Territory 6 is adjacent with the first pn layer 5 arranged side by side.That is, the first pn layer 5 arranged side by side and the second pn layer 15 arranged side by side are altogether
Contact with zone line 6, be via zone line 6 continuous print region.Second pn layer 15 arranged side by side
It is configured at the part of pressure-resistance structure portion 10c and can be arranged to start at from N-type buffer layer 2 that not arrive first main
The thickness in face.That is, at ion implanting described later and the heat treatment for forming the second pn layer 15 arranged side by side
In, the impurity being typically ion implanted into extension matrix can not expand to the first interarea.In the case of Gai, resistance to
In laminated structure portion 10c, between the second pn layer 15 arranged side by side and the first interarea, forming the second pn layer 15 arranged side by side
The n of Shi Chengwei epitaxial growth-Type semiconductor layer.
It is arranged side by side that zone line 6 between the first pn layer 5, second pn layer 15 arranged side by side arranged side by side is configured with the 3rd
Pn layer 43 and the 4th pn layer 46 arranged side by side, the described 3rd pn layer 43 arranged side by side and the 4th pn layer arranged side by side
46 is to make to become first by what the first ion implanting described later, the second ion implanting were separated from each other and were formed
Each impurity injection zone of pn layer 5, second pn layer 15 arranged side by side is diffused into this each impurity injection zone side by side
Between the region (the 3rd region described later) of the ion implanting not carrying out impurity form.Specifically,
Inner side (chip center side) part of zone line 6 possesses the 3rd pn layer 43 arranged side by side, and the described 3rd also
Row pn layer 43 has with repetition pitch P1 with the first n-type region 3 and the first p-type area 4 substantially
3rd n-type region that equal repetition pitch alternately configures, that impurity concentration is the lowest the most laterally (the
Three the first conductive areas) 41 and the 3rd p-type area (the 3rd the second conductive area) 42.
The Outboard Sections of zone line 6 possesses the 4th pn layer 46 arranged side by side, and the described 4th pn layer 46 arranged side by side has
Joint is repeated with roughly equal with repetition pitch P2 of the second n-type region 13 and the second p-type area 14
Away from alternately configure more to the 4th n-type region (the 4th the first conductivity type that inner side impurity concentration is the lowest
Region) 44 and the 4th p-type area (the 4th the second conductive area) 45.That is, zone line 6
Threeth n-type region 41 lower than the first n-type region 3 by mean impurity concentration and mean impurity concentration ratio
The 4th n-type region 44, mean impurity concentration that second n-type region 13 is low are lower than the first p-type area 4
The 3rd p-type area 42 and mean impurity concentration fourth p-type area lower than the second p-type area 14
45 are constituted.
It addition, the position that width is opposed with the center being clipped in the first p-type area 4 and the second p-type area 14
Between interval Y zone line a2 identical for width w4 first side by side pn layer 5 region a1 and
The n-type impurity amount of the region a3 of the second pn layer 15 arranged side by side and p-type impurity amount are relative in interval Y
Between region a2 meet Ca2 ＜ (Ca1+Ca3)/2.Ca1～Ca3 is respectively the impurity of region a1～a3
Amount.The center of the first p-type area 4 and the second p-type area 14 is opposed refers to the of the first p-type area 4
The center y in a first direction of the center of two direction x and second direction x of the second p-type area 14 is positioned at phase
With on straight line.Therefore, zone line 6 is to be easier to exhaust than the first pn layer 5 arranged side by side when cut-off state
Region.Further, in the position that the center of the first p-type area 4 and the second p-type area 14 is opposed, district
Between the impurity concentration of midpoint a2' of zone line a2 of the Y midpoint than the region a1 of the first pn layer arranged side by side
The impurity concentration of the midpoint a3' of the region a3 of the impurity concentration of a1' and the second pn layer arranged side by side is low.
The 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side that are configured at zone line 6 are opposed.?
Between three pn layers 43 arranged side by side and the 4th pn layer 46 arranged side by side, will have the first of different repetition pitches also
The transition region that the impurity of each impurity injection zone of row pn layer 5, second pn layer 15 arranged side by side spreads and obtains
47.Should illustrate, the 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side can also be to become first
Side by side impurity between each impurity injection zone of pn layer 5, second pn layer 15 arranged side by side spreads and overlap
Mode contacts.
In pressure-resistance structure portion 10c, in the position more more outward than the second pn layer 15 arranged side by side, at N-shaped
It is provided with n on cushion 2-Type region (the 5th the first conductive area) 12.n-Type region 12 is arranged
Become the thickness reaching the first interarea from N-type buffer layer 2.n-Type region 12 surrounds the second pn layer 15 arranged side by side
Around, the depletion layer that when having cut-off state, rejection ratio second pn layer 15 arranged side by side extends more laterally
The function extended.n-The mean impurity concentration in type region 12 is denseer than the average impurity of the second n-type region 13
Spend low.n-The width w1 in type region 12 is such as preferably the 1/20 of the width w2 of pressure-resistance structure portion 10c
Above and less than 1/3 degree.Its reason is by the second pn layer 15 arranged side by side is configured at pressure-resistance structure
The width w3 of the part of portion 10c is set to more than the 2/3 of the width w2 of pressure-resistance structure portion 10c, so that
Vague and generalization of the second pn layer 15 arranged side by side becomes easier to, so being prone to guarantee to make a reservation for pressure.
In the terminal area of pressure-resistance structure portion 10c, N-type buffer layer 2 is provided with n-type channel and stops
District 16.N-type channel stop zone 16 is arranged to arrive the thickness of the first interarea from N-type buffer layer 2.Replace
N-type channel stop zone 16, it is also possible to p-type channel stop zone is set.In n-type channel stop zone 16
One interarea side, is provided with p-type most peripheral region 17.Channel stop electrode 18 and p-type most peripheral region
17 connect, and component periphery portion 10d by cover the interlayer dielectric 19 of the first interarea and and MOS
Source electrode 8 electric insulation of grid structure.It addition, channel stop electrode 18 extends on interlayer dielectric 19,
Highlight than more inside side, p-type most peripheral region 17.Channel stop electrode 18 can also be unlike n-type channel
More inside side, stop zone 16 highlights.
Although being not particularly limited, but such as semiconductor device at embodiment 1 is longitudinal type MOSFET,
Pressure for 600V level in the case of, size and the impurity concentration in each portion are set to following value.Drift
The thickness (thickness of the first pn floor 5 arranged side by side) moving district is 35 μm, the first n-type area 3 and a p
The width in type district 4 is 6.0 μm (repeating pitch P1 is 12.0 μm).(described later being equivalent to drift region
Epitaxial layer 24 (Figure 10 reference)) 1/2 the n of the degree of depth-Oneth n of type semiconductor layer 21c surface configuration
The peak impurity concentration of the width of type region 3 and the first p-type area 4 is 4.0 × 1015/cm3。
The width of the second n-type region 13 and the second p-type area 14 is 4.0 μm (repeating pitch P2 is 8.0 μm).
N in the degree of depth of be equivalent to drift region (epitaxial layer 24 described later) 1/2-Type semiconductor layer 21c surface
The peak impurity concentration of the second n-type region 13 of configuration and the width of the second p-type area 14 is
2.0×1015/cm3.The width w4 of zone line 6 is 2 μm.Be equivalent to drift region (extension described later
Layer 24) 1/2 the n of the degree of depth-The n of type semiconductor layer 21c surface configuration-The width in type region 12
Peak impurity concentration be preferably 1.0 × 1015/cm3Below.n-The width w1 in type region 12 is 8 μm.
The width w2 of pressure-resistance structure portion 10c is 150 μm.Fig. 3～5 (in Figure 17～19,32,33 also phase
With) in, although make the simplified partial of the pressure-resistance structure portion that the is configured at 10c of the second pn layer 15 arranged side by side scheme
Show, but the width w3 of the part of the pressure-resistance structure portion that the is configured at 10c of the second pn layer 15 arranged side by side is 110 μm.
It addition, pressure for 300V level in the case of, n-The peak impurity concentration of the width in type region 12
It is preferably 1.0 × 1016/cm3Below.
Should illustrate, preferably though it is shown that at element active portion 10a in 1, at mos gate
The first pn layer 5 arranged side by side it is provided with, at pressure-resistance structure portion 10c, at n between structure and N-type buffer layer 2
Be provided with the structure of the second pn layer 15 arranged side by side on type cushion 2 but it also may mos gate structure with
n+First pn layer 5 arranged side by side is set between type drop ply 1, at n+Second pn layer arranged side by side is set on type drop ply 1
15。
It follows that the manufacture method of the semiconductor device of embodiment 1 is illustrated.Fig. 6～11 is
The sectional view of the state in the manufacture process of the semiconductor device of expression embodiment 1.Figure 12,13 it is table
Show embodiment 1 semiconductor device manufacture process in the top view of state.Figure 12 shows
State in the forming process of one pn layer 5, second pn layer 15 arranged side by side arranged side by side.Specifically, Figure 12
In show for formed the first pn layer 5, second pn layer 15 arranged side by side arranged side by side the first ion implanting 32,
The plane figure of the impurity injection zone after the second ion implanting 34 and before heat treatment.Figure 13 shows
The state of the zone line 6 after heat treatment.Fig. 6～11 shows the first of element active portion 10a also
State in the manufacture process of row pn layer 5, although diagram eliminates the second arranged side by side of pressure-resistance structure portion 10c
State in the manufacture process of pn layer 15, but the second pn layer 15 arranged side by side by with the first pn layer 5 arranged side by side
Identical method concurrently forms with the first pn layer 5 arranged side by side.That is, in Fig. 6～11, repetition pitch is made
P2 narrow obtained by state be the second pn layer 15 arranged side by side manufacture process in state.
First, as shown in Figure 6, as n+The n of type drop ply 1+On the front of type initial substrate, pass through
Epitaxial growth and form N-type buffer layer 2.It follows that as it is shown in fig. 7, on N-type buffer layer 2,
(formation) first paragraph n is piled up with predetermined thickness t by epitaxial growth-Type semiconductor layer 21a.It follows that
As shown in Figure 8, at n-In type semiconductor layer 21a, form the first p-type area with the first pn layer 5 arranged side by side
Second p-type area 14 of territory 4 and the second pn layer 15 arranged side by side form the corresponding outs open in region
Photoresistive mask 31.The width of second direction x of the peristome of photoresistive mask 31 is at element active portion 10a
The narrow width of middle second direction x than the first p-type area 4, ratio the 2nd p in pressure-resistance structure portion 10c
The narrow width of second direction x in type region 14.It addition, the second direction of the peristome of photoresistive mask 31
The width of x is narrower than in element active portion 10a in pressure-resistance structure portion 10c.It follows that by photoresistive mask
31 carry out the first ion implanting 32 as mask to n-type impurity.By this first ion implanting 32,
At n-The surface layer of type semiconductor layer 21a, is formed selectively n-type impurity in element active portion 10a
Injection zone 22a, is formed selectively n-type impurity injection zone 42a (ginseng in pressure-resistance structure portion 10c
According to Figure 12).The degree of depth of n-type impurity injection zone 22a, 42a is such as than n-The thickness of type semiconductor layer 21a
T is shallow for degree.
It follows that as it is shown in figure 9, after eliminating photoresistive mask 31, at n-In type semiconductor layer 21a,
Form the first n-type region 3 and the second N-shaped of the second pn layer 15 arranged side by side with the first pn layer 5 arranged side by side
The forming the corresponding outs open in region of region 13 and the photoresistive mask 33 that obtains.Photoresistive mask 33
The width of second direction x of peristome is the second party of ratio the first n-type region 3 in element active portion 10a
To the narrow width of x, the width of second direction x of ratio the second n-type region 13 in pressure-resistance structure portion 10c
Narrow.It addition, the width of second direction x of the peristome of photoresistive mask 33 compares in pressure-resistance structure portion 10c
In element active portion 10a narrow.It follows that photoresistive mask 33 is carried out as mask to p-type impurity
Two ion implantings 34.By this second ion implanting 34, at n-The surface layer of type semiconductor layer 21a,
Selectively formed p-type impurity injection zone 23a in element active portion 10a, in pressure-resistance structure portion 10c
n-The surface layer selectively formed p-type impurity injection zone 43a (with reference to Figure 12) of type semiconductor layer 21a.n
The degree of depth of type impurity injection zone 23a, 43a is such as than n-The thickness t of type semiconductor layer 21a is shallow.Also may be used
With by the formation process of p-type impurity injection zone 23a, 43a and n-type impurity injection zone 22a, 42a
Formation process exchange.
In first above-mentioned ion implanting the 32, second ion implanting 34, as shown in figure 12, at element
Active portion 10a d1 at predetermined intervals configures p-type impurity injection zone 23a and n-type impurity note discretely
Enter region 22a.At pressure-resistance structure portion 10c, d2 configures p-type impurity injection discretely at predetermined intervals
Region 43a and n-type impurity injection zone 42a.It addition, element active portion 10a and pressure-resistance structure portion
Each impurity injection zone 22a, 23a, 42a, 43a of 10c be configured to extend to element active portion 10a with
Borderline region 10b between pressure-resistance structure portion 10c.Specifically, in a first direction in y, element active
The p-type impurity injection zone 23a and n-type impurity injection zone 22a of portion 10a are configured in frontier district
The first area 10e of the inner side (10a side, element active portion) of territory 10b extends.Pressure-resistance structure portion 10c
P-type impurity injection zone 43a and n-type impurity injection zone 42a be configured at borderline region 10b
Outside (10c side, pressure-resistance structure portion) second area 10f extend.Further, by with photoresistive mask
31,33 the 3rd region 10g between first area 10e and second area 10f is covered, to the 3rd region
10g does not carry out the ion implanting of impurity, thus by each impurity injection zone 22a of element active portion 10a,
Each impurity injection zone 42a, 43a y in a first direction of 23a and pressure-resistance structure portion 10c configures discretely.
3rd region 10g is to become the first pn layer 5, second pn layer arranged side by side arranged side by side by heat treatment described later
The part of the zone line 6 between 15.The width of the first direction y of the 3rd region 10g (zone line 6)
Degree w4 can be n-Less than 1/2 (w4≤t/2) of the thickness t of type semiconductor layer 21a.Its reason is not
Be vulnerable to the repetition pitch due to n-type region and p-type area difference and the first pn layer 5 arranged side by side,
The harmful effect mutually produced between the second pn layer 15 arranged side by side, is not likely to produce resistance to pressure drop at borderline region 10b
Low.Specifically, at n-The thickness t of type semiconductor layer 21a be about 7 μm in the case of, mesozone
The width w4 of the first direction y in territory 6 can be such as about 2 μm.
It follows that as shown in Figure 10, after eliminating photoresistive mask 33, at n-In type semiconductor layer 21a,
Multistage n is piled up further by epitaxial growth-Type semiconductor layer 21b～21f, formed by these multistage (examples
Such as 6 sections) n-The epitaxial layer 24 of the predetermined thickness that type semiconductor layer 21a～21f are constituted.Now, every time
Pile up n-Type semiconductor layer 21b～21e, with first paragraph n-Type semiconductor layer 21a similarly carries out first
Ion implanting the 32, second ion implanting 34, at element active portion 10a and pressure-resistance structure portion 10c respectively
Form n-type impurity injection zone and p-type impurity injection zone.At element active portion 10a and pressure
N-type impurity injection zone that structural portion 10c is formed respectively and the plane figure of p-type impurity injection zone
With at first paragraph n-N-type impurity injection zone and p-type impurity that type semiconductor layer 21a is formed inject
The plane figure in region is identical.Figure 10 shows in element active portion 10a at n-Type semiconductor layer
21b～21f forms n-type impurity injection zone 22b～22e respectively, and form respectively p-type impurity note
Enter the state of region 23b～23e.At the n becoming epitaxial layer 24-In type semiconductor layer 21a～21f
Epimere n-Type semiconductor layer 21f can not also carry out first ion implanting the 32, second ion implanting 34.Logical
Cross operation so far, as n+The n of type drop ply 1+It is formed successively on the front of type initial substrate
The extension matrix of stacking N-type buffer layer 2 and epitaxial layer 24.
It follows that as shown in figure 11, by heat treatment, make n-Each n in type semiconductor layer 21a～21e
Type impurity injection zone and the diffusion of each n-type impurity injection zone.Each p-type impurity injection zone and each
N-type impurity injection zone is respectively formed as the linearity that y extends in the first direction, so respectively with ion
The generally a cylindrical shape ground extension of axle centered by injection phase.Thus, in element active portion 10a, along deep
P-type impurity injection zone 23a～23e opposed for degree direction z links each other in the way of overlapping, shape
Become the first n-type region 3, and along n-type impurity injection zone 22a～22e opposed for depth direction z that
This is to link overlappingly, forms the first p-type area 4.And the first n-type region 3 and a p
Type region 4 links overlappingly, forms the first pn layer 5 arranged side by side.In pressure-resistance structure portion 10c also together
Sample ground, overlaps ground even each other along p-type impurity injection zone (not shown) opposed for depth direction z
Knot, forms the second n-type region 13, and along n-type impurity injection zone opposed for depth direction z (not
Diagram) overlap ground link each other, forms the second p-type area 14.And the second n-type region 13
Link overlappingly with the second p-type area 14, form the second pn layer 15 arranged side by side.Now, on border
The 3rd region 10g of region 10b, p-type impurity and n-type impurity respectively from element active portion 10a and
During the p-type impurity injection zone of pressure-resistance structure portion 10c and each n-type impurity injection zone spread and are formed
Between region 6.
Although being not particularly limited, but such as semiconductor device at embodiment 1 is longitudinal type MOSFET,
Pressure for 600V level, the width w4 of the first direction y of zone line 6 is the situation about 2 μm
Under, first ion implanting the 32, second ion implanting 34 with and subsequent for impurity diffusion heat treatment
Condition as described below.For the first ion implanting 32, by the first p-type area 4 and the 2nd p
The dosage in type region 14 is set to 0.2 × 1013/cm2Above and 2.0 × 1013/cm2Following degree.For
For second ion implanting 34, the dosage of the first n-type region 3 and the second n-type region 13 is set to
0.2×1013/cm2Above and 2.0 × 1013/cm2Following degree.Heat treatment temperature be more than 1000 DEG C and
The degree of less than 1200 DEG C.
The state of the zone line 6 after heat treatment is shown in Figure 13.By the first ion implanting 32,
What two ion implantings 34 were separated from each other and were formed becomes the first pn layer 5, second pn layer 15 arranged side by side arranged side by side
Each impurity injection zone between the 3rd region 10g of the ion implanting not carrying out impurity, in being formed
Between region 6, zone line 6 possess this each impurity injection zone diffusion the 3rd pn layer 43 arranged side by side
And the 4th pn layer 46 arranged side by side.Specifically, as the inner side of zone line 6 of the 3rd region 10g
(chip center side) is formed in part with the 3rd pn layer 43 arranged side by side, the 3rd pn layer 43 arranged side by side have with
The repetition pitch that repetition pitch P1 of the first n-type region 3 and the first p-type area 4 is almost equal replaces
3rd n-type region 41 and the 3rd p-type area 42 that ground configures, that impurity concentration is the lowest the most laterally.
The Outboard Sections of zone line 6 is formed with the 4th pn layer 46 arranged side by side, the 4th pn layer 46 arranged side by side have with
The repetition pitch roughly equal with repetition pitch P2 of the second n-type region 13 and the second p-type area 14
That alternately configure, more to the 4th n-type region 44 and the 4th p-type area that inner side impurity concentration is the lowest
45.That is, zone line 6 is formed with the 3rd n-type area that mean impurity concentration is lower than the first n-type region 3
Territory 41 and mean impurity concentration fourth n-type region 44 and the average impurity lower than the second n-type region 13
The 3rd p-type area 42 that concentration is lower than the first p-type area 4 and mean impurity concentration are than the second p-type area
The 4th p-type area 45 that territory 14 is low, than the first pn layer 5, second pn arranged side by side arranged side by side when being off state
Layer 15 is easier to the region exhausted.
The 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side that are configured at zone line 6 are opposed.?
Between three pn layers 43 arranged side by side and the 4th pn layer 46 arranged side by side, exist and will there is the first of different repetition pitch
The transition that the impurity of each impurity injection zone of pn layer 5, second pn layer 15 arranged side by side arranged side by side spreads and obtains
District 47.Should illustrate, the 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side can be to become first
The side that impurity between each impurity injection zone of pn layer 5, second pn layer 15 arranged side by side arranged side by side spreads and overlaps
Formula contacts.
The plane figure of the second n-type region 13 and the second p-type area 14 is preferably striated.Its reason
By being, it is easy to by multiple second n-type region 13 and multiple second p-type area 14 respective averagely
Impurity concentration is adjusted to roughly the same, it is easy to guarantee the charge balance of the second pn layer 15 arranged side by side.Assuming will
Second p-type area 14 is configured to rectangular plane figure, is formed as the second n-type region 13 surrounding
The cancellate plane figure of the second p-type area 14.In the case of Gai, the second p-type area 14 be substantially
Rectangular-shaped flat shape, in contrast, the second n-type region 13 is relative to the second p-type area 14
There is the cancellate flat shape of three times of surface areas.Therefore, there is following worry: in order at the 2nd n
Type region 13 entirety diffusion n-type impurity equably, studies the p-type impurity as the second n-type region 13
The difficulty of the plane figure of injection zone becomes big, and/or the machining accuracy of photoresistive mask have limitation etc. because of from
Difference that son injects and cause the respective mean impurity concentration of multiple second n-type region 13 uneven.By this
The harmful effect that the difference of ion implanting causes is in the second n-type region 13 and the second p-type area 14
Repeat the pressure-resistance structure portion 10c that pitch P2 is narrow produces particularly significant.To this, by the second n-type region
13 and second in the case of the plane figure of p-type area 14 is set to striated, the second n-type region 13
And second p-type area 14 be all the flat shape of the roughly equal linearity of surface area.Therefore, pass through
The width making second direction x of p-type impurity injection zone and n-type impurity injection zone is equal, thus
Can be by dense for the respective average impurity of multiple second n-type region 13 and multiple second p-type area 14
Degree is easily adapted to for roughly the same.
N-type channel stop zone 16 such as can form first p-type area the 4, second p-type area 14
Formed by the first ion implanting 32, it is also possible in the timing different from the first ion implanting 32 simultaneously
Property ground carry out the ion implanting of n-type impurity and formed.n-Type region 12 can the first ion implanting 32,
N is covered with photoresistive mask 31,33 during the second ion implanting 34-The formation region in type region 12 and formed,
Can also increase further and be selectively ion-implanted the operation of p-type impurity and formed.It follows that utilize
Usual way, carries out forming mos gate structure and/or p-type most peripheral region 17, layer insulation successively
Film 19, source electrode 8, channel stop electrode 18, the remaining operation such as operation of drain electrode 9.Thereafter,
It is shaped like chips by extension matrix is cut (cut-out), thus completes the superjunction quasiconductor shown in Fig. 1～5
Device.
Should illustrate, preferably in the manufacture method of the semiconductor device of 1, although becoming n+
The n of type drop ply 1+N-type buffer layer 2 is formed but it also may be formed without N-shaped on the front of type initial substrate
Cushion 2, and becoming n+The n of type drop ply 1+Epitaxial layer 24 is formed on the front of type initial substrate.
It follows that an example of the element active portion 10a of the semiconductor device of embodiment 1 is carried out
Explanation.Figure 14 is the cross section of an example in the element active portion of the semiconductor device representing embodiment 1
Figure.Figure 15 is the cross section of another example in the element active portion of the semiconductor device representing embodiment 1
Figure.As shown in figure 14, in the first interarea side of element active portion 10a, be provided with by p-type base 7,
n+Type source region 51, p+The common plane that type contact area 52, gate insulating film 53 and gate electrode 54 are constituted
The mos gate structure of grid structure.It addition, as shown in figure 15, at first interarea of element active portion 10a
Side, can be arranged by p-type base 7, n+Type source region 61, p+Type contact area 62, groove 63, gate insulation
The mos gate structure of the common trench gate structure that film 64 and gate electrode 65 are constituted.These mos gates
Structure is to configure in the way of depth direction z contacts by the first p-type area 4 with the first pn layer 5 arranged side by side
P-type base 7.Dotted line in first pn layer 5 arranged side by side is logical when forming the first pn layer 5 arranged side by side
Cross epitaxial growth and the multiple n of stacking-Border between type semiconductor layer.
(embodiment 2)
For the structure of the semiconductor device of embodiment 2, to possess the n-channel type of super-junction structure
Illustrate as a example by MOSFET.Represent the top view of the plane figure of the semiconductor device of embodiment 2
Identical with the top view of the plane figure of the semiconductor device representing embodiment 1.Figure 16 is by Fig. 1
The top view that X1 portion amplifies and illustrates.Figure 17 is cutting of the cross section structure of the line of cut A-A' representing Fig. 1
Face figure.Figure 18 is the sectional view of the cross section structure of the line of cut B-B' representing Fig. 1.Figure 19 is to represent figure
The sectional view of the cross section structure of the line of cut C-C' of 1.
The semiconductor device of embodiment 2 difference from the semiconductor device of embodiment 1 is, the
One n-type region the 3, second n-type region the 13, the 3rd n-type region 41 and the 4th n-type region 44 have
There is identical mean impurity concentration, and do not formed by the ion implanting of p-type impurity.Even if not
Carry out the ion implanting of p-type impurity for forming first n-type region the 3, second n-type region 13, no
Change the p-type impurity concentration of extension matrix (n-type semiconductor layer 71a described later～71f) and formed side by side
In the case of the n-type region of pn layer, it is also possible to obtain and embodiment 1 by possessing zone line 6
Identical effect.
Zone line 6 between the first pn layer 5, second pn layer 15 arranged side by side arranged side by side is configured with the 3rd pn arranged side by side
Layer 43 and the 4th pn layer 46 arranged side by side, the 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side are by making
What the first ion implanting was formed separated from each other becomes the first pn layer 5, second pn layer 15 arranged side by side arranged side by side
Each impurity injection zone is diffused into the ion implanting not carrying out impurity between this each impurity injection zone
Region (the 3rd region) forms.Specifically, inner side (chip center side) part of zone line 6
Possess the 3rd pn layer 43 arranged side by side, the 3rd pn layer 43 arranged side by side with the first n-type region 3 and a p
The roughly equal repetition pitch of repetition pitch P1 in type region 4 alternately configures and forms, and has more towards outward
The 3rd p-type area 42 that side impurity concentration is the lowest.The Outboard Sections of zone line 6 possesses the 4th pn arranged side by side
Layer 46, the 4th pn layer 46 arranged side by side with the second n-type region 13 and repetition of the second p-type area 14
The roughly equal repetition pitch of pitch P2 alternately configures and forms, and has more towards inner side impurity concentration
The 4th the lowest p-type area 45.That is, zone line 6 is by mean impurity concentration and the first n-type region 3
The 3rd identical n-type region 41 and the 4th n-type region 44 and mean impurity concentration are than the first p-type
The 3rd p-type area 42 that region 4 is low and mean impurity concentration lower than the second p-type area 14 the 4th
P-type area 45 is constituted.
It addition, the position that width is opposed with the center being clipped in the first p-type area 4 and the second p-type area 14
Between interval Y zone line b2 identical for width w4 first side by side pn layer 5 region b1 and
The n-type impurity amount of the region b3 of the second pn layer 15 arranged side by side is relative to the zone line b2 of interval Y, full
Foot Cb2 ＜ (Cb1+Cb3)/2.Cb1～Cb3 is respectively the n-type impurity amount of region b1～b3.Cause
This, be prone to the region exhausted compared with the first pn layer 5 arranged side by side when zone line 6 is off state.Further,
In the position that the center of the first p-type area 4 and the second p-type area 14 is opposed, the mesozone of interval Y
The impurity concentration of the midpoint b2' of the territory b2 impurity than the midpoint b1' of the region b1 of the first pn layer 5 arranged side by side is dense
The impurity concentration of the midpoint b3' of the region b3 of degree and the second pn layer 15 arranged side by side is low.It is configured at mesozone
The 3rd of territory 6 pn layer arranged side by side 43 and the 4th pn layer 46 arranged side by side are opposed.Additionally, the 3rd pn layer arranged side by side
43 and the 4th pn layer 46 arranged side by side can be to become each of the first pn layer 5, second pn layer 15 arranged side by side arranged side by side
Impurity between impurity injection zone spreads and the mode of overlap contacts.
Although being not particularly limited, but such as semiconductor device at embodiment 2 is longitudinal type MOSFET,
Pressure for 600V level in the case of, the size in each portion and impurity concentration are following value.Drift region
Thickness (thickness of the first pn layer 5 arranged side by side) be 35 μm, the first n-type region 3 and the first p-type
The width in region 4 is 6.0 μm (repeating pitch P1 is 12.0 μm).(described later being equivalent to drift region
Epitaxial layer 24) 1/2 the first n-type region 3 (n of n-type semiconductor layer 71c surface configuration of the degree of depth
Type semiconductor layer 71a～71f) the peak impurity concentration of width be 4.0 × 1015/cm3.Quite
In the n-type semiconductor layer 71c surface configuration of the degree of depth of the 1/2 of drift region (epitaxial layer 24 described later)
The peak impurity concentration of the width of the first p-type area 4 is 4.0 × 1015/cm3.Second n-type region
13 and second the width of p-type area 14 be 4.0 μm (repeating pitch P2 is 8.0 μm).Be equivalent to
The of the n-type semiconductor layer 71c surface configuration of the degree of depth of the 1/2 of drift region (epitaxial layer 24 described later)
The peak impurity concentration of the width of two p-type area 14 is 2.0 × 1015/cm3.The width of zone line 6
Degree w4 is 2 μm.The width w2 of pressure-resistance structure portion 10c is 150 μm, joining of the second pn layer 15 arranged side by side
The width w3 of the part being placed in pressure-resistance structure portion 10c is 110 μm.
In pressure-resistance structure portion 10c, in the position more more outward than the second pn layer 15 arranged side by side, at N-shaped
N-type region 70 it is provided with on cushion 2.
Should illustrate, preferably in 2, it is shown that at element active portion 10a, tie at mos gate
The first pn layer 5 arranged side by side it is provided with, at pressure-resistance structure portion 10c, at N-shaped between structure and N-type buffer layer 2
The form of the second pn layer 15 arranged side by side it is provided with but it also may at mos gate structure and n on cushion 2+
First pn layer 5 arranged side by side is set between type drop ply 1, at n+Second pn layer 15 arranged side by side is set on type drop ply 1.
It follows that the manufacture method of the semiconductor device of embodiment 2 is illustrated.Figure 20～24 is
The sectional view of the state in the manufacture process of the semiconductor device of expression embodiment 2.Figure 25,26 it is table
Show embodiment 2 semiconductor device manufacture process in the top view of state.Figure 25 show for
Formed the first pn layer 5, second pn layer 15 arranged side by side arranged side by side the first ion implanting 32 after and heat treatment
The plane figure of front impurity injection zone.Figure 26 shows the state of the zone line 6 after heat treatment.
The manufacture method of the semiconductor device of the manufacture method of the semiconductor device of embodiment 2 and embodiment 1
Difference be not carry out the second ion implanting 34 of ion implanting p-type impurity.
Specifically, first, as shown in figure 20, as n+The n of type drop ply 1+Type initial substrate
On front, formed N-type buffer layer 2 by epitaxial growth.It follows that as shown in figure 21, at N-shaped
On cushion 2, pile up (formation) first paragraph n-type semiconductor by epitaxial growth with predetermined thickness t
Layer 71a.It follows that as shown in figure 22, in n-type semiconductor layer 71a, formed and the first pn arranged side by side
First p-type area 4 of layer 5 and the formation region of the second p-type area 14 of the second pn layer 15 arranged side by side
The photoresistive mask 31 of corresponding outs open.The width of second direction x of the peristome of photoresistive mask 31
The narrow width of second direction x of ratio the first p-type area 4 in element active portion 10a, at pressure-resistance structure
The narrow width of second direction x of ratio the second p-type area 14 in portion 10c.It addition, photoresistive mask 31
The width of second direction x of peristome is narrower than in element active portion 10a in pressure-resistance structure portion 10c.
It follows that photoresistive mask 31 to be carried out the first ion implanting 32 to n-type impurity as mask.Pass through
This first ion implanting 32, at the surface layer of n-type semiconductor layer 71a, selects in element active portion 10a
Form to selecting property n-type impurity injection zone 22a, in pressure-resistance structure portion 10c, be formed selectively p-type miscellaneous
Matter injection zone 42a (with reference to Figure 25).The degree of depth of n-type impurity injection zone 22a, 42a is such as than N-shaped
The thickness t of semiconductor layer 71a is shallow.
In the first above-mentioned ion implanting 32, as shown in figure 25, element active portion 10a and pressure knot
Impurity injection zone 22a, 42a of the p-type of structure portion 10c is configured to extend to element active portion 10a and resistance to
Borderline region 10b between laminated structure portion 10c.Specifically, in a first direction on y, element active portion
The n-type impurity injection zone 22a of 10a is configured to extend to (the element active portion, inner side of borderline region 10b
10a side) first area 10e.The n-type impurity injection zone 42a of pressure-resistance structure portion 10c is configured to prolong
Extend the second area 10f in the outside (10c side, pressure-resistance structure portion) of borderline region 10b.Further, pass through
The 3rd region 10g between first area 10e and second area 10f is covered, to photoresistive mask 31
Three region 10g do not carry out the ion implanting of impurity, thus are noted by the impurity of the p-type of element active portion 10a
Divide on the impurity injection zone 42a y in a first direction of the p-type entering region 22a and pressure-resistance structure portion 10c
Liftoff configuration.3rd region 10g is by heat treatment described later as the first pn layer arranged side by side 5 and second also
The part of the zone line 6 between row pn layer 15.The first direction of the 3rd region 10g (zone line 6)
The width w4 of y can be less than 1/2 (w4≤t/2) of the thickness t of n-type semiconductor layer 71a.Its reason
By being, it is not easily susceptible to the difference of repetition pitch according to n-type region and p-type area and arranged side by side first
The harmful effect mutually produced between pn layer 5, second pn layer 15 arranged side by side, is difficult to produce at borderline region 10b
Raw pressure reduction.Specifically, at n-The thickness t of type semiconductor layer 21a be about 7 μm in the case of,
The width w4 of the first direction y of zone line 6 can be such as about 2 μm.
It follows that as shown in figure 23, after eliminating photoresistive mask 31, in n-type semiconductor layer 71a,
Piled up multistage n-type semiconductor layer 71b～71f by epitaxial growth further, formed by these multistage (examples
Such as 6 sections) n-type semiconductor layer 71a～the epitaxial layer 24 of predetermined thickness that constitutes of 71f.Now, every time
Pile up n-type semiconductor layer 71b～71e, all carry out first in the same manner as first paragraph n-type semiconductor layer 71a
Ion implanting 32, forms n-type impurity respectively at element active portion 10a and pressure-resistance structure portion 10c and injects
Region.At the n-type impurity injection zone that element active portion 10a and pressure-resistance structure portion 10c is formed respectively
The plane of plane figure and the n-type impurity injection zone formed in first paragraph n-type semiconductor layer 71a
Layout is identical.Figure 23 shows and distinguishes at n-type semiconductor layer 71b～the 71f of element active portion 10a
Define the state of n-type impurity injection zone 22b～22e.In the n-type semiconductor as epitaxial layer 24
Uppermost n-type semiconductor layer 71f in layer 71a～71f can not also carry out the first ion implanting 32.Logical
Cross operation so far, as n+The n of type drop ply 1+It is formed successively on the front of type initial substrate
The extension matrix of stacking N-type buffer layer 2 and epitaxial layer 24.
It follows that as shown in figure 24, by heat treatment, each p in n-type semiconductor layer 71a～71e is made
Type impurity injection zone spreads.Each n-type impurity injection zone is respectively formed as what y in the first direction extended
Linearity, so extend respectively centered by ion implanting position the generally a cylindrical shape of axle.Thus, exist
In element active portion 10a, along n-type impurity injection zone 22a～22e opposed for depth direction z each other with
The mode overlapped links, and forms the first p-type area 4.At pressure-resistance structure portion 10c similarly, edge
N-type impurity injection zone (not shown) opposed for depth direction z links each other in the way of overlapping,
Form the second p-type area 14.Now, at the 3rd region 10g of borderline region 10b, n-type impurity from
Each n-type impurity injection zone of element active portion 10a and pressure-resistance structure portion 10c spreads and forms centre
Region 6.
Although being not particularly limited, but such as semiconductor device at embodiment 2 is longitudinal type MOSFET,
Pressure for 600V level, the width w4 of the first direction y of zone line 6 is the situation about 2 μm
Under, the first ion implanting 32 and subsequent as described below for the condition of heat treatment of impurity diffusion.For
For first ion implanting 32, the dosage of the first p-type area 4 and the second p-type area 14 is set to
0.2×1013/cm2Above and 2.0 × 1013/cm2Following degree.Heat treatment temperature be more than 1000 DEG C and
The degree of less than 1200 DEG C.
The state of the zone line 6 after heat treatment is shown in Figure 26.By the first ion implanting 32
The impurity note of the p-type becoming the first pn layer 5, second pn layer 15 arranged side by side arranged side by side being separated from each other and formed
Enter the 3rd region of the interregional ion implanting not carrying out impurity
10g, is formed with zone line 6, zone line 6 possess the diffusion of this impurity injection zone the 3rd also
Row pn layer 43 and the 4th pn layer 46 arranged side by side.Specifically, as the mesozone of the 3rd region 10g
The inner side (chip center side) in territory 6 is formed in part with the 3rd pn layer 43 arranged side by side, the 3rd pn layer 43 arranged side by side
With the repetition pitch roughly equal with repetition pitch P1 of the first n-type region 3 and the first p-type area 4
Alternately configuration forms, and has the 3rd p-type area 42 that impurity concentration the most laterally is the lowest.Zone line 6
Outboard Sections be formed with the 4th pn layer 46 arranged side by side, the 4th pn layer 46 arranged side by side with the second n-type region
13 and second the roughly equal repetition pitch of repetition pitch P2 of p-type area 14 alternately configure and form,
There is the 4th more the lowest to inner side impurity concentration p-type area 45.That is, at zone line 6, it is formed
The 3rd n-type region 41 and the 4th n-type region 44 that mean impurity concentration is identical with the first n-type region 3
And the 3rd p-type area 42 and the 4th p-type area that mean impurity concentration is lower than the first p-type area 4
45, it is prone to the region exhausted when being off state compared with the first pn layer 5 arranged side by side.
The 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side that are configured at zone line 6 are opposed.Should
Illustrate, the 3rd pn layer 43 arranged side by side and the 4th pn layer 46 arranged side by side can also with become the first pn layer 5 arranged side by side,
Impurity between each impurity injection zone of the second pn layer 15 arranged side by side spreads and the mode of overlap contacts.Should
Illustrating, the embodiment 2 difference from embodiment 1 is not to the first n-type region 3 and the 2nd n
Type region 13 carries out the second ion implanting 34, but the element active portion of the semiconductor device of embodiment 2
10a is the composition identical with the element active portion 10a of the semiconductor device of embodiment 1.
(embodiment 3)
For the structure of the semiconductor device of embodiment 3, to have possessed the n-channel type of super-junction structure
Illustrate as a example by MOSFET.Figure 29 is the plane figure of the semiconductor device representing embodiment 3
Top view.Figure 30 is the top view being amplified in the X2 portion of Figure 29 and representing.Figure 31 is by Figure 29
The top view that X3 portion amplifies and represents.Figure 32 is cutting of the cross section structure of the line of cut D-D' representing Figure 29
Face figure.Figure 33 is the sectional view of the cross section structure of the line of cut E-E' representing Figure 29.Figure 29 shows
First pn layer 85, second pn arranged side by side arranged side by side of transversal element active portion 10a and component periphery portion 10d
The plane of layer 15, the such as degree of depth is the plane of the 1/2 of the first pn layer 85 arranged side by side of element active portion 10a
Shape.For clear and definite first n-type region 83 and repetition pitch P1 of the first p-type area 84 and
The difference of repetition pitch P2 of two n-type region 13 and the second p-type area 14, makes shown in Figure 29
The number in these regions fewer than Figure 30～34.
The semiconductor device of embodiment 3 difference from the semiconductor device of embodiment 1 is,
The plane figure of the striated that the direction orthogonal with the direction that the striped of the second pn layer 15 arranged side by side extends extends
Configuration the first pn layer 85 (Figure 29～33) arranged side by side.In embodiment 3, by the first pn layer 85 arranged side by side
Striped extend be laterally set to second direction x, horizontal by the extension of the striped of the second pn layer 15 arranged side by side
It is set to first direction y.Element active portion 10a in addition to the plane figure of the first pn layer 85 arranged side by side
Constitute identical with embodiment 1.The composition of component periphery portion 10d is identical with embodiment 1.Second also
Row pn layer 15 surrounds the first pn layer 85 arranged side by side across zone line 6 in the same manner as embodiment 1
Around, and adjacent with the first pn layer 85 arranged side by side via zone line 6.
That is, putting down with first direction y at the zone line 6 configured with the plane figure of substantially rectangular frame-shaped
Straight line portion (hereinafter referred to as the first straight line portion) 6b of row and the line part parallel with second direction x
Divide (hereinafter referred to as the second straight line portion) 6a, the 3rd pn layer the 43, the 4th pn layer 46 arranged side by side arranged side by side
Differently configured.3rd pn layer the 43, the 4th pn layer 46 arranged side by side arranged side by side in the same manner as embodiment 1,
It is each impurity injection zone diffusion becoming the first pn layer 85, second pn layer 15 arranged side by side arranged side by side respectively
(the 3rd above-mentioned district, region of the ion implanting not carrying out impurity between this each impurity injection zone
Territory) form.First n-type region 83 and repetition pitch P1 of the first p-type area 84 and the second N-shaped
Region 13 is identical with embodiment 1 with the condition of repetition pitch P2 of the second p-type area 14.
Specifically, as shown in figure 30, the first n-type region 83 and first of the first pn layer 85 arranged side by side
Outermost such as first n-type region 83 of the repeating part of p-type area 84, with the first pn arranged side by side
(first direction y) is across the second straight line portion 6a of zone line 6 in the orthogonal direction of striped of layer 85
The second n-type region 13 and striped end pair of the second p-type area 14 with the second pn layer 15 arranged side by side
Put.That is, the inboard portion at the second straight line portion 6a of zone line 6 is only configured with the 3rd pn arranged side by side
3rd n-type region 41 of layer 43, is equipped with the 4th n-type region in lateral part distribution across transition region 47
44 and the 4th the 4th pn layer 46 arranged side by side of alternately repeating in second direction x of p-type area 45.
Transition region 47 in second straight line portion 6a of zone line 6 is to become the first pn layer 85 arranged side by side
The second n-type region 13 and the 2nd p of the such as first n-type region 83, second pn layer 15 arranged side by side
The region of the impurity diffusion of each impurity injection zone in type region 14.The of width and zone line 6
The region a11 of identical for width w4 first of two straight line portion 6a side by side pn layer 85 and second arranged side by side
The p-type impurity amount of the region a13 of pn layer 15 is relative to the second straight line portion 6a of zone line 6, full
Foot Ca12 ＜ (Ca11+Ca13)/2.Ca11～Ca13 is region a11, the second straight line portion 6a respectively
And the p-type impurity amount of region a13.The n-type impurity amount of the second straight line portion 6a of zone line 6 from
Reduce inside lateral.
On the other hand, as shown in figure 31, the second n-type region 13 and second of the second pn layer 15 arranged side by side
Such as second n-type region 13 of the inner side of the repeating part of p-type area 14, with the second pn arranged side by side
(second direction x) is across the first straight line portion 6b of zone line 6 in the orthogonal direction of striped of layer 15
And with the first n-type region 83 and striped end of the first p-type area 84 of the first pn layer 85 arranged side by side
Opposed.That is, the inboard portion at the first straight line portion 6b of zone line 6 is configured with the 3rd n-type area
The 3rd pn layer 43 arranged side by side that territory 41 and the 3rd p-type area 42 y in the first direction is alternately repeated,
The 4th n-type region 44 of the 4th pn layer 46 arranged side by side only it is configured with at Outboard Sections across transition region 47.
Transition region 47 in first straight line portion 6b of zone line 6 is to become the first pn layer 85 arranged side by side
The first n-type region 83 and the first p-type area 84, and the such as the 2nd n of the second pn layer 15 arranged side by side
The region of the impurity diffusion of each impurity injection zone in type region 13.The of width and zone line 6
The region a21 of identical for width w4 first of one straight line portion 6b side by side pn layer 85 and second arranged side by side
The p-type impurity amount of the region a23 of pn layer 15 is relative to the first straight line portion 6b of zone line 6, full
Foot Ca22 ＜ (Ca21+Ca23)/2.Ca21～Ca23 is region a21, the second straight line portion respectively
The p-type impurity amount of 6b and region a23.The n-type impurity amount of the first straight line portion 6b of zone line 6
Reduce from Inside To Outside.
The manufacture method of the semiconductor device of embodiment 3 is the system of the semiconductor device at embodiment 1
Make in method, change the first ion for forming the first pn layer 85, second pn layer 15 arranged side by side arranged side by side
Putting down of the photoresistive mask 31,33 (with reference to Fig. 8～10) used in injection the 32, second ion implanting 34
Face layout.Specifically, the photoresistive mask 31 used in the first ion implanting 32 is with first also
First p-type area 84 of row pn layer 85 formed part corresponding to region and with the second pn layer 15 arranged side by side
The plane figure forming partial orthogonality corresponding to region of the second p-type area 14 and opening.Second ion
Inject the photoresistive mask 33 used in 34 with the shape with the first n-type region 83 of the first pn layer 85 arranged side by side
Become part corresponding to region and corresponding with the formation region of the second n-type region 13 of the second pn layer 15 arranged side by side
The plane figure of partial orthogonality and opening.
In embodiment 3, pressure for 600V level in the case of, zone line 6 (the first line part
Point 6b, the second straight line portion 6a) impurity concentration be such as preferably 1.0 × 1014/cm3Following degree.Separately
Outward, pressure for 300V level in the case of, the impurity concentration of zone line 6 such as be preferably 1.0 ×
1015/cm3Following degree.
Embodiment 3 can be applied to the semiconductor device of embodiment 2.
Above, as it has been described above, according to above-mentioned each embodiment, by becoming the first pn layer arranged side by side
Formed between impurity injection zone and the impurity injection zone becoming the second pn layer arranged side by side and do not carry out impurity
3rd region of ion implanting, at the 3rd region thermal diffusion each impurity injection zone, it is possible to first also
Row pn layer, the second pn interlayer arranged side by side, formation has that mean impurity concentration is lower than the first pn layer arranged side by side
Three pn layers arranged side by side and the mesozone of the mean impurity concentration fourth arranged side by side pn layer lower than the second pn layer arranged side by side
Territory.It addition, the impurity level of zone line is lower than the impurity level of the first pn layer arranged side by side, so arranged side by side with first
Pn layer is compared and is prone to exhaust, and is difficult to electric field and concentrates.Therefore, even if configure n-type region in pressure-resistance structure portion
The second arranged side by side pn layer narrow with the repetition pitch ratio element active portion of p-type area, makes the resistance to of pressure-resistance structure portion
The pressure height in pressure ratio element active portion, the borderline region electric charge between element active portion and pressure-resistance structure portion
Changes in balance also will not mutually produce harmful effect.Therefore, between element active portion and pressure-resistance structure portion
Borderline region in there is not pressure reduction.Accordingly, because can adjust respectively the first pn layer arranged side by side,
The charge balance of two pn layers arranged side by side, so that component periphery portion (pressure-resistance structure portion and borderline region)
The pressure height in the element active of resistance to pressure ratio portion and height pressureization that make element overall becomes easy.Therefore, it is possible to
Improve reliability.Even if it addition, increasing the mean impurity concentration of the first pn layer arranged side by side and achieve low conducting
Resistance, it is also possible to maintain component periphery portion and the resistance to pressure reduction in element active portion.Lead therefore, it is possible to reduce
Energising resistance, and pressure reduction can be suppressed.It addition, by making the element of resistance to pressure ratio in component periphery portion live
The pressure height in property portion such that it is able to faster puncture than component periphery edge in element active portion
(breakdown), it is possible to improve avalanche capability, Reverse recovery tolerance.
It addition, be provided with in component periphery portion as conventional (Fig. 8 of the most above-mentioned patent documentation 1)
In the composition of protection ring, due to embracing element active portion peripherally, be separated from each other in concentric circles and
Configure multiple protection ring, so the width in component periphery portion is elongated.On the other hand, according to above-mentioned each reality
Executing mode, the second p-type area of the second pn layer arranged side by side being arranged at component periphery portion plays and protection ring phase
As function.Therefore, by arranging the second pn layer arranged side by side in component periphery portion such that it is able to make element week
Edge is prone to exhaust when cut-off, and without arranging protection ring in component periphery portion, it is possible to prevent pressure
The width of structural portion is elongated.It addition, according to above-mentioned each embodiment, by than the second pn layer arranged side by side
More outward position arranges n-Type region, thus when cut-off state, energy to the second pn layer arranged side by side
Enough exhausting rapidly and the extension of depletion layer that rejection ratio second pn layer arranged side by side extends more laterally.Thus, consumption
Layer to the greatest extent is difficult to arrive n-type channel stop zone, is not likely to produce the electric field of local near n-type channel stop zone
Concentrate, it is possible to suppress pressure reduction.It addition, it is more more outward than the second pn layer arranged side by side by being configured at
N-Type region and n-type region suppress the extension of depletion layer such that it is able to shorten pressure-resistance structure portion
Width.It addition, according to embodiment 3, even if the direction extended at the striped being set to the first pn layer arranged side by side
In the case of the plane figure orthogonal with the direction that the striped of the second pn layer arranged side by side extends, it is also possible to adjust respectively
Whole first pn layer arranged side by side, the charge balance of the second pn layer arranged side by side.Therefore, the degree of freedom of design is high.
Above, the present invention is not limited to above-mentioned each embodiment, at the model of the purport without departing from the present invention
In enclosing, it is possible to carry out various change.Such as, at the size described in above-mentioned each embodiment, impurity
Concentration etc. are an example, and the present invention is not limited to these values.It addition, in above-mentioned each embodiment,
Although the first conductivity type is set to N-shaped, the second conductivity type is set to p-type, but the present invention is conducted electricity first
Type is set to p-type, the second conductivity type is set to N-shaped, sets up too.It addition, the invention is not restricted to
MOSFET, it is possible to be applied to IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar
Transistor npn npn), bipolar transistor, FWD (Free Wheeling Diode: fly-wheel diode) or
Schottky diode etc..
Industrial applicability
As it has been described above, the manufacture method of the semiconductor device of the present invention and semiconductor device is applied at bag
The component periphery portion of the surrounding enclosing element active portion possesses the big power semiconductor device in pressure-resistance structure portion,
Be specifically for use in using drift layer as the MOSFET of pn layer arranged side by side, IGBT, bipolar transistor,
FWD or the contour pressure semiconductor device of Schottky diode.
Claims (18)
1. a semiconductor device, it is characterised in that possess:
Surface element structure, it is arranged at the first interarea side；
Conductive formation, it is arranged at the second interarea side；
First pn layer arranged side by side, it is arranged between described surface element structure and described conductive formation, and
One the first conductive area and first the second conductive area alternately configure；
Second pn layer arranged side by side, it is placed around around the described first pn layer arranged side by side, and alternately joins
It is equipped with second the first conductive area and second the second conductive area to lead than described first first
Electricity type region and the narrow pitch of the repetition pitch of described first the second conductive area；With
Zone line, it is set between the described first pn layer arranged side by side and the described second pn layer arranged side by side,
Contact with the described first pn layer arranged side by side and the described second pn layer arranged side by side, wherein,
At described zone line, have:
3rd the second conductive area, itself and described first second conduction of the described first pn layer arranged side by side
Type area contact, and mean impurity concentration is lower than described first the second conductive area,
4th the second conductive area, itself and described second second conduction of the described second pn layer arranged side by side
Type area contact, and mean impurity concentration is lower than described second the second conductive area.
Semiconductor device the most according to claim 1, it is characterised in that
At described zone line, have:
3rd the first conductive area, itself and described first first conduction of the described first pn layer arranged side by side
Type area contact, and mean impurity concentration is lower than described first the first conductive area；
4th the first conductive area, itself and described second first conduction of the described second pn layer arranged side by side
Type area contact, and mean impurity concentration is lower than described second the first conductive area.
Semiconductor device the most according to claim 2, it is characterised in that
It is configured with at described zone line:
3rd pn layer arranged side by side, it is described 3rd the first conductive area and described 3rd second conduction
Type region alternately configures and forms.
4. according to the semiconductor device described in Claims 2 or 3, it is characterised in that
It is configured with at described zone line:
4th pn layer arranged side by side, its be described 4th the first conductive area and described 4th second lead
Electricity type region alternately configures and forms.
5. according to the semiconductor device according to any one of claims 1 to 3, it is characterised in that
Described first the first conductive area and described first the second conductive area are configured to striped
The plane figure of shape,
Described second the first conductive area and described second the second conductive area be configured to towards
The striated identical with described first the first conductive area and described first the second conductive area
Plane figure,
Described 3rd the second conductive area and described 4th the second conductive area be configured to towards
The striated identical with described first the second conductive area and described second the second conductive area
Plane figure.
6. according to the semiconductor device according to any one of claims 1 to 3, it is characterised in that
Described 3rd the second conductive area that center is opposed and described 4th the second conductive area every
Drift region adjacent.
7. according to the semiconductor device according to any one of claims 1 to 3, it is characterised in that
Described first the first conductive area and described first the second conductive area are configured to striped
The plane figure of shape,
Described second the first conductive area and described second the second conductive area be configured to towards
The striated orthogonal with described first the first conductive area and described first the second conductive area
Plane figure,
Described 3rd the second conductive area be configured to towards with described first the second conductive area phase
The plane figure of same striated,
Described 4th the second conductive area be configured to towards with described second the second conductive area phase
The plane figure of same striated.
8. according to the semiconductor device according to any one of claims 1 to 3, it is characterised in that further
Possess:
Element active portion, it is configured with described surface element structure and the described first pn layer arranged side by side, and
Current flowing is had when conducting state；
Component periphery portion, it is configured with the described second pn layer arranged side by side, and surrounds described element active portion；
Terminal area, it is in the opposite side relative to side, described element active portion in described component periphery portion,
It is arranged between described first interarea and described conductive formation；
5th the first conductive area, its be arranged at the described second pn layer arranged side by side and described terminal area it
Between, and mean impurity concentration is lower than described second the first conductive area；And
Conductive layer, it electrically connects with described terminal area.
9. the manufacture method of a semiconductor device, it is characterised in that include following operation:
Formation process, repeats the first operation and the second operation, wherein,
Described first operation, piles up the first conductive-type semiconductor layer,
Described second operation, at the surface layer of described first conductive-type semiconductor layer, with alternately configure
Mode forms first the first conductive-type impurity injection zone and first the second conductive-type impurity injection region
Territory, and than described first the first conductive-type impurity injection zone and described first second conduction
The more outward position separated with preset width of type impurity injection zone, with than described first first conduction
The joint that the repetition pitch of type impurity injection zone and described first the second conductive-type impurity injection zone is narrow
Form second the first conductive-type impurity injection zone away from the mode alternately configured and second second lead
Electricity type impurity injection zone；With
Heat treatment step, by heat treatment, make described first the first conductive-type impurity injection zone and
Described first second conductive-type impurity injection zone diffusion and formed first the first conductive area and
The first pn layer arranged side by side that first the second conductive area alternately configures, and make described second
First conductive-type impurity injection zone and described second the second conductive-type impurity injection zone spread and shape
Become that second the first conductive area and second the second conductive area alternately configure second
Pn layer side by side,
In described heat treatment step, between the described first pn layer arranged side by side and the described second pn layer arranged side by side,
Make described first the first conductive-type impurity injection zone, described first the second conductive-type impurity injection region
Territory, described second the first conductive-type impurity injection zone and described second the second conductive-type impurity note
Enter regional diffusion and formed have that mean impurity concentration is lower than described first the first conductive area the 3rd
Individual first conductive area, the 3rd that mean impurity concentration is lower than described first the second conductive area
The 4th that second conductive area, mean impurity concentration are lower than described second the first conductive area
One conductive area and four lower than described second the second conductive area of mean impurity concentration
The zone line of two conductive areas.
The manufacture method of semiconductor device the most according to claim 9, it is characterised in that
In described heat treatment step, formed and have described 3rd the first conductive area and described
The 3rd pn layer arranged side by side that 3rd the second conductive area alternately configures and by described 4th
The 4th pn arranged side by side that one conductive area and described 4th the second conductive area alternately configure
The described zone line of layer.
11. according to the manufacture method of the semiconductor device described in claim 9 or 10, it is characterised in that
In described second operation, by described first the first conductive-type impurity injection zone and described
One the second conductive-type impurity injection zone is formed as the plane figure of striated, and by described second
First conductive-type impurity injection zone and described second the second conductive-type impurity injection zone are formed as court
Note to described first the first conductive-type impurity injection zone and described first the second conductive-type impurity
Enter the plane figure of the identical striated in region.
12. according to the manufacture method of the semiconductor device described in claim 9 or 10, it is characterised in that
In described second operation, by described first the first conductive-type impurity injection zone and described
One the second conductive-type impurity injection zone is formed as the plane figure of striated, and by described second
First conductive-type impurity injection zone and described second the second conductive-type impurity injection zone are formed as court
Note to described first the first conductive-type impurity injection zone and described first the second conductive-type impurity
Enter the plane figure of the orthogonal striated in region.
The manufacture method of 13. 1 kinds of semiconductor devices, it is characterised in that include following operation:
Formation process, repeats the first operation and the second operation, wherein,
Described first operation, piles up the first conductive-type semiconductor layer,
Described second operation, at the surface layer of described first conductive-type semiconductor layer, with alternately configure
Mode forms first the second conductive-type impurity injection zone, and than described first the second conductivity type
The more outward position separated with preset width of impurity injection zone, with than described first the second conductivity type
The pitch that the repetition pitch of impurity injection zone is narrow forms second the second conductive-type impurity injection zone；With
Heat treatment step, by heat treatment, makes described first the second conductive-type impurity injection zone expand
Dissipate and form first the second conductive area and alternately configure with described first conductive-type semiconductor layer and form
The first pn layer arranged side by side, and make described second the second conductive-type impurity injection zone diffusion form the
It is second arranged side by side that two the second conductive areas and described first conductive-type semiconductor layer alternately configure
Pn layer,
In described heat treatment step, between the described first pn layer arranged side by side and the described second pn layer arranged side by side,
Described first the second conductive-type impurity injection zone and described second the second conductive-type impurity is made to inject
Regional diffusion and being formed has the 3rd that mean impurity concentration is lower than described first the second conductive area
Second conductive area and mean impurity concentration lower than described second the second conductive area the 4th
The zone line of individual second conductive area.
The manufacture method of 14. semiconductor devices according to claim 13, it is characterised in that
In described second operation, described first the second conductive-type impurity injection zone is formed as striped
The plane figure of shape, and described second the second conductive-type impurity injection zone is formed towards and institute
State the plane figure of first identical striated of the second conductive-type impurity injection zone.
The manufacture method of 15. semiconductor devices according to claim 13, it is characterised in that
In described second operation, described first the second conductive-type impurity injection zone is formed as striped
The plane figure of shape, and described second the second conductive-type impurity injection zone is formed towards and institute
State the plane figure of first orthogonal striated of the second conductive-type impurity injection zone.
16. according to the manufacture method of the semiconductor device according to any one of claim 9,13, and it is special
Levy and be,
Described preset width is described first conductive-type semiconductor layer piled up in the most described first operation
Thickness less than 1/2.
17. according to the manufacture method of the semiconductor device according to any one of claim 9,13, and it is special
Levy and be,
The conductive formation that first conductive-type semiconductor layer described in resistance ratio is low is formed the described first pn arranged side by side
Layer and the described second pn layer arranged side by side,
After described heat treatment step, in the phase relative to described conductive formation side of the described first pn layer arranged side by side
Anti-side forms surface element structure.
18. according to the manufacture method of the semiconductor device according to any one of claim 9,13, and it is special
Levy and be,
The element active portion of current flowing is had when described first pn layer arranged side by side is formed at conducting state,
Described second pn layer arranged side by side is formed at the component periphery portion surrounding described element active portion.
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| JP2015-076123 | 2015-04-02 | ||
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| JP2015217948A JP6668687B2 (en) | 2015-04-02 | 2015-11-05 | Semiconductor device and method of manufacturing semiconductor device |
| JP2015-217948 | 2015-11-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111384155A (en) * | 2020-05-29 | 2020-07-07 | 电子科技大学 | Super junction device |
| CN112768447A (en) * | 2021-01-11 | 2021-05-07 | 杭州士兰集昕微电子有限公司 | Reverse conducting insulated gate bipolar transistor and manufacturing method thereof |
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| TWI806414B (en) | 2022-02-09 | 2023-06-21 | 鴻海精密工業股份有限公司 | Power semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001298190A (en) * | 2000-02-09 | 2001-10-26 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2007311669A (en) * | 2006-05-22 | 2007-11-29 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| JP2008294214A (en) * | 2007-05-24 | 2008-12-04 | Toshiba Corp | Semiconductor device |
| CN103560148A (en) * | 2013-10-18 | 2014-02-05 | 西安龙腾新能源科技发展有限公司 | Junction terminal structure of super junction device and manufacturing method of super junction device |
| CN103794640A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device comprising a cell area and an edge area |
-
2015
- 2015-11-05 JP JP2015217948A patent/JP6668687B2/en active Active
-
2016
- 2016-03-03 CN CN201610121087.7A patent/CN106057866B/en active Active
- 2016-03-03 TW TW105106506A patent/TWI701831B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001298190A (en) * | 2000-02-09 | 2001-10-26 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2007311669A (en) * | 2006-05-22 | 2007-11-29 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| JP2008294214A (en) * | 2007-05-24 | 2008-12-04 | Toshiba Corp | Semiconductor device |
| CN103794640A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device comprising a cell area and an edge area |
| CN103560148A (en) * | 2013-10-18 | 2014-02-05 | 西安龙腾新能源科技发展有限公司 | Junction terminal structure of super junction device and manufacturing method of super junction device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111384155A (en) * | 2020-05-29 | 2020-07-07 | 电子科技大学 | Super junction device |
| CN112768447A (en) * | 2021-01-11 | 2021-05-07 | 杭州士兰集昕微电子有限公司 | Reverse conducting insulated gate bipolar transistor and manufacturing method thereof |
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| CN106057866B (en) | 2021-11-23 |
| JP2016197705A (en) | 2016-11-24 |
| TW201709507A (en) | 2017-03-01 |
| TWI701831B (en) | 2020-08-11 |
| JP6668687B2 (en) | 2020-03-18 |
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