CN115842045A - Power integrated circuit and preparation method thereof - Google Patents

Abstract

The invention relates to a power integrated circuit and a preparation method thereof, wherein the power integrated circuit comprises an isolation which is suitable for being manufactured by a VDMOS process, and the isolation comprises the following steps: the PNP tube comprises two P + well regions and an N-drift region positioned between the P + well regions; and the polysilicon field plate is positioned above the surface of the N-drift region and extends to at least partial surface of the two P + well regions, and the polysilicon field plate is electrically connected on the grid electrode of the power MOSFET for starting. When the starting tube works, the grid potential is not lower than the source potential, and when the source of the power MOSFET for starting is pulled up, the grid potential also rises, so that the surface electric field intensity of the device is effectively reduced, the isolation voltage of the device can well follow the drain potential within the oxidation voltage-resistant range, and the voltage-resistant performance of the device is improved.

Description

Power integrated circuit and preparation method thereof

Technical Field

The invention belongs to the field of semiconductor device preparation, and particularly relates to a power integrated circuit and a preparation method thereof.

Background

The power integrated circuit is an integrated circuit which integrates a high-voltage power device, a control circuit, a peripheral interface circuit, a protection circuit and the like on the same chip, and is a bridge of a system signal processing part and an execution part. In the power integration technology, process compatibility between a high-voltage device and a low-voltage device is realized, particularly, a proper isolation technology is selected, and reusability of process layers must be considered in order to control manufacturing cost. With the development of the application requirements of electronic systems, power integration technology needs to implement compatibility of high and low voltages, high performance, high efficiency and high reliability on a limited chip area.

Referring to fig. 1, fig. 1 is an integrated circuit of a self-starting power MOSFET with sampling monitoring protection, in which a starting power MOSFET3, a sampling tube 2, a main power tube 1 and a resistor R are integrated as shown. In the self-starting power MOSFET circuit with sampling monitoring protection, when self-starting, the source S3 of the power MOSFET3 for starting and the source S2 of the sampling tube 2 and the source S1 of the main power MOSFET1 have the requirement of isolation and withstand voltage, and usually, the field oxygen and the PNP tube are adopted for isolation, and the isolation method can meet the general isolation requirement, but has the following defects:

1. the field oxygen width directly influences the isolation voltage resistance, the widening of the field oxygen can improve the isolation voltage resistance, but the whole device can cause early breakdown, the narrowing of the field oxygen can improve the breakdown voltage of the whole device, but the isolation voltage resistance can not meet the requirement;

2. the field oxygen is thick, so that wet etching is generally adopted, and the process consistency is poor.

Therefore, there is a need for an improved self-starting power integrated circuit to overcome the problems of the prior art.

Disclosure of Invention

In view of this, the present invention provides a power integrated circuit manufactured by different processes, and the isolation manufactured by the VDMOS process is adapted to reduce the technical problems of poor field oxide width and process uniformity caused by the conventional MOSFET process.

According to the purpose of the invention, the power integrated circuit at least comprises a power MOSFET for starting and a main power MOSFET, wherein an isolation which is manufactured by a VDMOS process is arranged between the power MOSFET for starting and the main power MOSFET, and the isolation comprises:

the PNP tube comprises two P + well regions and an N-drift region positioned between the P + well regions;

and the polysilicon field plate is positioned above the surface of the N-drift region and extends to at least partial surface of the two P + well regions, and the polysilicon field plate is electrically connected on the grid electrode of the power MOSFET for starting.

Preferably, the starting power MOSFET, the main power MOSFET and the isolation comprise a common N + substrate and an N-epitaxial layer on the N + substrate.

Preferably, the two P + well regions are formed in the N-epitaxial layer, and an N-epitaxial layer region between the two P + well regions forms the N-drift region.

Preferably, the isolation is a VDMOS device, and the N + substrate constitutes a drain region of the isolation.

Preferably, an N + well region is further disposed in the two P + well regions, the two N + well regions forming the isolated source region, and the polysilicon field plate extends at least over and partially covers the two N + well regions.

Preferably, an oxide layer is arranged below the polysilicon field plate, and the polysilicon field plate and the oxide layer form the isolated gate region.

Preferably, the drains of the start-up power MOSFET, the sampling MOSFET, and the main power MOSFET are connected together, and the gate of the start-up power MOSFET is connected to the drain of the start-up MOSFET.

Preferably, the power MOSFET further comprises a pull-up resistor disposed between the gate and the drain of the power MOSFET for starting.

Preferably, the width of the polysilicon field plate is consistent with the width of a device cell region which is suitable for being manufactured by a VDMOS process.

According to the object of the present invention, there is also provided a method for manufacturing a power integrated circuit as described above, for forming at least a power MOSFET for start-up and a main power MOSFET on a substrate, further comprising forming an isolation between the power MOSFET for start-up and the main power MOSFET, the isolation being adapted to be manufactured by a VDMOS process, comprising the steps of:

forming at least two P + well regions on the substrate, wherein an N-drift region exists between the two P + well regions;

forming an oxide layer and a polysilicon field plate on the surface of the N-drift region, wherein the oxide layer and the polysilicon field plate at least extend to the P + well regions on two sides;

the polysilicon field plate is electrically connected to the gate of the power MOSFET for starting.

Preferably, the polysilicon field plate is formed by dry etching.

Preferably, the substrate comprises an N + substrate and an N-epitaxial layer positioned on the N + substrate,

the power MOSFET for starting, the main power MOSFET and the isolation are formed on the N-epitaxial layer.

Preferably, the isolation is a VDMOS device, and before forming the oxide layer and the polysilicon field plate, the isolation further includes:

forming an N + well region in the two P + well regions, wherein a predetermined distance exists between the N + well region and the N-drift region,

the polysilicon field plate covers at least a portion of a surface of the N + well region, wherein the N + substrate forms the isolated drain region, the N + well region forms the isolated source region, and the polysilicon field plate forms the isolated gate region.

Compared with the prior art, the invention has the technical effects that:

1. the polysilicon field plate can be connected to the grid of the power MOSFET for starting on a circuit, and because the grid potential is not lower than the source potential when the starting tube works, the grid potential can also rise when the source electrode of the power MOSFET for starting is pulled high, so that the surface electric field intensity is effectively reduced, and the isolation voltage resistance is improved. In the range of oxidation withstand voltage, the isolation voltage can well follow the drain terminal potential.

2. The width of the polysilicon field plate can be the same as that of a cell region of a VDMOS device (such as a main power tube, a tube or a starting tube), and the integral breakdown of the device is not influenced.

3. The polysilicon field plate is etched by a dry method, adopts a self-alignment process, is matched with a VDMOS process, and has excellent process consistency.

Drawings

Fig. 1 is an equivalent circuit diagram of a power integrated circuit in the prior art.

Fig. 2 is a schematic cross-sectional view of an isolation structure according to a first embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of an isolation structure according to a second embodiment of the present invention.

Fig. 4a-4d are cross-sectional views of device structures corresponding to various steps in a power integrated circuit fabrication process of the present invention.

Fig. 5 is a simulation diagram of isolation withstand voltage of the isolation structure of the present invention and a conventional isolation structure.

Detailed Description

The present invention will be described in detail with reference to the specific embodiments shown in the drawings, which are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the specific embodiments are included in the scope of the present invention.

Referring to fig. 1, the circuit portion according to the present invention mainly uses a power MOSFET circuit with a self-starting function as a main circuit, and the circuit structure at least includes a starting power MOSFET3 (hereinafter referred to as a starting tube 3) and a main power MOSFET1 (hereinafter referred to as a main power tube 1). In addition, a power MOSFET for sampling (hereinafter referred to as a sampling tube 2) is usually included in a self-starting power MOSFET circuit including an integrated sampling function. The starting tube 3, the sampling tube 2 and the drain electrode of the main power tube 1 are connected together, in one implementation mode, the substrate (usually an N + substrate) is used as a common drain electrode, and other electrodes of all devices are manufactured on the substrate. In other embodiments, the electrical connection may be made by metal wiring, so that the drains of the respective tubes are at a common potential. The grid electrode of the sampling tube 2 is connected with the grid electrode of the main power tube 1, and the grid electrode of the starting tube 3 is connected with the drain electrode of the starting tube 3. In one embodiment, a pull-up resistor R is further provided between the gate and the drain of the starting tube 3.

Taking a self-starting power integrated circuit with an integrated sampling function as an example (namely, in the case of a sampling tube 2), in order to make each source electrode of the main power tube 1, the sampling tube 2 and the starting tube 3 have a certain electrical isolation, an isolation structure is usually arranged between any two of the main power tube 1, the sampling tube 2 and the starting tube 3, as described in the background art, the existing isolation structure is arranged in a PNP + field oxygen manner. PNP can both be fine before the reverse breakdown voltage of arbitrary PN junction and play the isolation effect through setting up two PN junctions that reverse concatenate, and sets up field oxygen structure above the drift region, can further improve and keep apart withstand voltage, increases the isolation effect. However, in order to improve the isolation withstand voltage, the existing isolation structure often needs to increase the width of the field oxide, and the increase of the width of the field oxide increases the voltage drop of the junction region, so that the PN junction is reversely broken down in advance, and therefore, the field oxide structure has certain limitations in the application scenario. On the other hand, when field oxygen is manufactured, wet etching is usually adopted, the process consistency of the whole device is poor, and additional defects are introduced to the device.

In the invention, a PNP tube + polysilicon field plate structure is innovatively introduced, the polysilicon field plate replaces the original field oxide structure, the polysilicon field plate is connected with the grid electrode of the starting tube, and the potential of the grid electrode is higher than that of the source electrode when the starting tube works, so that when the voltage of the source electrode of the tube rises, the potential of the grid electrode is also raised, namely the potential at the polysilicon field plate is raised, the field intensity change on the surface of a device is reduced, therefore, the isolation voltage can well follow the potential of a drain terminal in the range of the gate oxide voltage resistance, thereby achieving the effect of improving the isolation voltage resistance. On the other hand, in the application scene, the structure of the PNP tube and the polysilicon field plate can be just manufactured by adapting to a VDMOS process, particularly, when the polysilicon field plate is manufactured, a dry etching process can be adopted to perform self-aligned etching, the process consistency is higher, and therefore, the process is optimized while the structure is improved, and a very outstanding effect is achieved.

Next, the isolation structure in the present application will be described in detail.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view of an isolation structure in the present application. As shown, the isolation structure includes two P + well regions 102 and an N-drift region 1011 located between the two P + well regions 102; the P + well region 102 and the N-drift region 1011 form a PNP transistor, which has two opposite PN junctions and therefore can cut off both positive and negative currents, and when a voltage is applied across the PNP transistor, electrons cannot move at the channel to form a current as long as the voltage is below the breakdown voltage of the PN junction, and the whole PNP transistor can perform an electrical isolation function.

The polysilicon field plate 104 is positioned above the surface of the N-drift region 1011 and extends to at least part of the surface of the two P + well regions 102, an oxide layer 105 is also arranged below the polysilicon field plate 104, the oxide layer 105 is thin silicon oxide prepared on the surface of the substrate by an oxidation process, and the thin silicon oxide is mainly used for isolating the polysilicon field plate 103 from the surface of the substrate. The polysilicon field plate 104 is mainly used to adjust the surface electric field distribution of the device, and in the present invention, the polysilicon field plate 104 is electrically connected to the gate of the start tube 3. Because the potential of the grid is higher than that of the source electrode in normal operation, when the voltage of the source electrode of the tube rises, the potential of the grid is also raised, namely the potential at the polysilicon field plate is raised, so that the field intensity change on the surface of the device is reduced, and the effect of improving the isolation withstand voltage is achieved.

Referring to fig. 2 again, in a preferred embodiment, the start-up transistor 3, the sampling transistor 2, the main power transistor 1 and the isolation structure include a common N + substrate 100 and an N-epitaxial layer 101 on the N + substrate 100, two P + well regions 102 are formed in the N-epitaxial layer 101, and an N-epitaxial layer region between the two P + well regions 102 forms the N-drift region 1011.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view of an isolation structure according to a second embodiment of the invention. In this embodiment, the entire isolation structure can also be fabricated as a VDMOS device, in which case the N + substrate constitutes the isolated drain region. The N + well region 103 is formed by pushing N + + ions into the two P + well regions 102, and the two N + well regions 103 may be externally connected with conductive materials such as metal or polysilicon to form isolated source regions, and the polysilicon field plate 104 is extended to cover at least a portion of the two N + well regions 103. Therefore, besides the PNP tube, the gate region of the isolation structure can be formed by connecting the polysilicon field plate 104 with external voltage, so that the VDMOS device is formed, at the moment, besides the polysilicon field plate 104 is connected with the gate of the starting tube, the VDMOS device can be directly controlled by a single voltage, the electron migration in the field region is modulated, the single voltage can be set to be lower, the switching performance of the vertical MOS device as a switching device can be controlled, the isolation performance of the vertical MOS device as an isolation device can be ensured, the PN junction of the PNP can not be broken down, the application characteristics of the tube can be further increased, and the use scenes of the tube can be increased.

Preferably, after the field plate is formed, a passivation layer or other insulating layer can be formed outside to protect and encapsulate the field plate.

Since the polysilicon field plate 102 adjusts the surface electric field mainly by applying voltage, the polysilicon field plate 102 can also have a width consistent with that of the whole device cell, and the breakdown voltage of the PN junction is not affected.

The method for manufacturing the integrated circuit of the present invention will be described in detail below.

Fig. 4a-4d are cross-sectional views of devices corresponding to some steps of the method for fabricating the self-starting power integrated circuit. In the whole process, through the design of the photoetching layout, different functional tubes integrated on the substrate can be obtained after a plurality of photoetching procedures, such as a starting power MOSFET, a sampling MOSFET, a main power MOSFET and the like. It should be noted that, in the schematic diagrams shown in fig. 4a-4d, only the cross-sectional schematic diagrams of the isolation structure are shown, and for other devices in the circuit, the structure between the devices is similar to that of each functional transistor in the existing self-starting power integrated circuit, and will not be described in detail. As shown, the isolation structure is formed between any two of the power MOSFET for starting, the MOSFET for sampling and the main power MOSFET to form isolation, and the isolation is suitable for VDMOS process manufacturing and comprises the following steps:

s1: a substrate is prepared. In a semiconductor material, an N + substrate 100 is formed by doping, and then an N-epitaxial layer 101 is formed by performing epitaxy on the N + substrate and performing N-type light doping. The N-epitaxial layer 101 can be used as a functional region for subsequently manufacturing devices, and the starting power MOSFET, the sampling MOSFET, the main power MOSFET and the isolation can be formed on the N-epitaxial layer. And when the isolation is used as a VDMOS device, the N + substrate 100 may also constitute a drain terminal of the isolation.

S2: at least two P + well regions 102 are formed on the substrate, and an N-drift region 1011 exists between each P + well region 102. And defining a region needing P + heavily doping through a photoetching layout, and then carrying out P + doping by using photoresist as a mask. The prepared several P + well regions and the N-region with interval form PNP tube structure. In one embodiment, the P + well region 102 may also be regarded as an isolated body region, and a VDMOS device is formed through a subsequent process.

S3: an oxide layer 105 and a polysilicon field plate 104 are formed on the surface of the N-drift region 1011, and the oxide layer 105 and the polysilicon field plate 104 at least extend to the P + well regions on both sides. The oxide layer 105 is a thin silicon oxide layer, and the polysilicon field plate 104 is also thin, so that the polysilicon field plate can be manufactured by dry etching, and meanwhile, the photoresist used as a doping process in the above process can be used as a mask for self-aligned etching, so that the process consistency is higher compared with a field oxide process.

S4: the polysilicon field plate is electrically connected to the gate of the power MOSFET for starting.

In a preferred embodiment, the method further comprises forming an N + well region 103 in the P + well region, wherein a distance exists between the N + well region 103 and the N-drift region, the N + well region 103 forms the isolated source, and the polysilicon field plate covers at least a part of the surface of the N + well region. When the N + well region is used as a source electrode, a layer of ohmic contact conductive material, such as metal or polysilicon layer, can be formed on the surface of the N + well region, so that the source electrode can be led out. Also in this embodiment, the oxide layer 105 and the polysilicon field plate 104 need to extend over and cover at least part of the surface of the N + well region in order to modulate the electrons in the N + well region by the electric field.

Referring to fig. 5, the left and right sides of fig. 5 are a simulation diagram of the breakdown voltage of the conventional isolation structure and a simulation diagram of the isolation structure of the present invention, respectively. In the figure, through comparison of measured data, in an integrated VDMOS device of 800V class, when starting, the voltage applied to the drain terminal is 38V, and the conventional isolation withstand voltage can only reach 22V at normal temperature, and by adopting the isolation structure of the invention, the drain voltage Vdrain can be almost reached to about 37.9V, and the isolation withstand voltage can still meet the requirement. Therefore, the novel isolation structure designed by the invention achieves a higher voltage-resistant electric isolation effect.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (13)

1. A power integrated circuit comprising at least a power MOSFET for start-up and a main power MOSFET, characterized in that: an isolation which is suitable for being manufactured by a VDMOS process is arranged between the power MOSFET for starting and the main power MOSFET, and the isolation comprises:

the PNP tube comprises two P + well regions and an N-drift region positioned between the two P + well regions;

and the polysilicon field plate is positioned above the surface of the N-drift region and extends to at least partial surface of the two P + well regions, and the polysilicon field plate is electrically connected on the grid electrode of the power MOSFET for starting.

2. The power integrated circuit of claim 1, wherein: the starting power MOSFET, the main power MOSFET and the isolation comprise a shared N + substrate and an N-epitaxial layer located on the N + substrate.

3. The power integrated circuit of claim 2, wherein: the two P + well regions are formed in the N-epitaxial layer, and an N-epitaxial layer region between the two P + well regions forms the N-drift region.

4. The power integrated circuit of claim 2, wherein: the isolation is a VDMOS device, and the N + substrate forms a drain region of the isolation.

5. The power integrated circuit of claim 4, wherein: and an N + well region is also arranged in the two P + well regions, the two N + well regions form the isolated source region, and the polysilicon field plate at least extends and covers part of the two N + well regions.

6. The power integrated circuit of claim 4 or 5, wherein: an oxide layer is arranged below the polysilicon field plate, and the polysilicon field plate and the oxide layer form the isolated gate region.

7. The power integrated circuit of claim 1, wherein: the drain electrodes of the starting power MOSFET and the main power MOSFET are connected together, and the grid electrode of the starting power MOSFET is connected with the drain electrode of the starting power MOSFET.

8. The power integrated circuit of claim 7, wherein: the power MOSFET for starting further comprises a pull-up resistor arranged between the grid electrode and the drain electrode of the power MOSFET for starting.

9. The power integrated circuit of claim 7, wherein: the width of the polysilicon field plate is consistent with the width of a device cell area which is suitable for VDMOS process manufacturing.

10. A method of fabricating a power integrated circuit according to any one of claims 1 to 9, for forming at least a starting power MOSFET and a main power MOSFET on a substrate, further comprising forming an isolation between said starting power MOSFET and said main power MOSFET, said isolation being adapted for VDMOS process fabrication, comprising the steps of:

forming at least two P + well regions on the substrate, wherein an N-drift region exists between the two P + well regions;

forming an oxide layer and a polysilicon field plate on the surface of the N-drift region, wherein the oxide layer and the polysilicon field plate at least extend to the P + well regions on two sides;

the polysilicon field plate is electrically connected to the gate of the power MOSFET for starting.

11. The method of manufacturing a power integrated circuit according to claim 10, wherein: the polysilicon field plate is formed by dry etching.

12. The method of manufacturing a power integrated circuit according to claim 10, wherein: the substrate comprises an N + substrate and an N-epitaxial layer positioned on the N + substrate,

the power MOSFET for starting, the main power MOSFET and the isolation are formed on the N-epitaxial layer.

13. The method of manufacturing a power integrated circuit according to claim 9, wherein: the isolation is a VDMOS device, and before an oxide layer and a polysilicon field plate are formed, the isolation further comprises:

forming an N + well region in the two P + well regions, wherein a predetermined distance exists between the N + well region and the N-drift region,

the polysilicon field plate covers at least a portion of the surface of the N + well region, wherein the N + substrate forms the isolated drain region, the N + well region forms the isolated source region, and the polysilicon field plate forms the isolated gate region.

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