CN116404032A - Preparation method of N-channel enhanced MOSFET device for realizing low on-resistance - Google Patents
Preparation method of N-channel enhanced MOSFET device for realizing low on-resistance Download PDFInfo
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Abstract
The invention relates to a preparation method of an N-channel enhanced MOSFET device for realizing low on-resistance, which comprises the following steps: etching a first groove and a second groove on one side of the upper end face of the substrate doped with p-ions, wherein the first groove gradually extends to the second groove from top to bottom, so that the distance between the first groove and the second groove gradually decreases from top to bottom; filling N-type silicon in the first groove and the second groove to form a first N-type heavily doped region and a second N-type heavily doped region; an insulating layer grows on the upper end face of the p-type substrate corresponding to a region between the first N-type heavily doped region and the second N-type heavily doped region; respectively growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, and growing a grid electrode on the upper surface of the insulating layer; and growing a high-hole-rate p-type AlGaN material on the lower end surface of the p-type substrate to form a high-hole-rate material layer.
Description
Technical Field
The invention relates to the field of MOSFET devices, in particular to a preparation method of an N-channel enhanced MOSFET device for realizing low on-resistance.
Background
The N-channel enhancement MOS transistor is a common field effect transistor, as shown in fig. 1, when no forward voltage is connected between the gate and the source of the N-channel enhancement MOS transistor, a depletion layer 1002 is formed between the N-channel and the P-substrate, so as to disconnect the two N-channels. When a forward voltage is applied between the gate and the source of the N-channel enhancement MOS transistor, electrons form an N-type thin layer on the surface of the P-substrate near the gate and are connected to the two n+ regions, thereby forming an N-type conduction channel 1001 between the drain and the source.
After the N-channel enhancement type MOS tube is conducted, the resistance value between the drain electrode D and the source electrode S is called as on-resistance R DS（ON） ，R DS（ON） The smaller the value, the smaller the loss in operation and the lower the heating value. This resistance is caused by a combination of factors, the most predominant of which is channel resistance. R is R DS（ON） The value is affected by the width, length, etc. of the conductive channel. To reduce R DS（ON） Numerical value, in the prior art, the length of a conducting channel is reduced, but when forward voltage is connected between a grid electrode and a source electrode of an N-channel enhanced MOS tube after the length of the conducting channel is reduced, a channel where electrons are converged near the grid electrode is correspondingly reduced, and the conduction time of the N-channel enhanced MOS tube is influenced.
The invention aims to solve the problems in the prior art and designs a preparation method of an N-channel enhanced MOSFET device for realizing low on-resistance.
Disclosure of Invention
The present invention is directed to a method for manufacturing an N-channel enhancement MOSFET device with low on-resistance, which is capable of effectively solving at least one of the problems of the prior art.
The technical scheme of the invention is as follows:
a preparation method of an N-channel enhanced MOSFET device for realizing low on-resistance comprises the following steps:
etching a first groove and a second groove on one side of the upper end face of the substrate doped with p-ions, wherein the first groove gradually extends to the second groove from top to bottom, so that the distance between the first groove and the second groove gradually decreases from top to bottom;
filling N-type silicon in the first groove and the second groove to form a first N-type heavily doped region and a second N-type heavily doped region;
an insulating layer grows on the upper end face of the p-type substrate corresponding to a region between the first N-type heavily doped region and the second N-type heavily doped region;
respectively growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, and growing a grid electrode on the upper surface of the insulating layer;
and growing a high-hole-rate p-type AlGaN material on the lower end surface of the p-type substrate to form a high-hole-rate material layer.
Further, before the high-hole-rate p-type AlGaN material grows on the lower end face of the p-type substrate to form a high-hole-rate material layer, the following steps are performed: photoetching the lower end surface of the p-type substrate into an arc shape;
the Gao Kongxue material layer is arc-shaped and matched with the lower end face of the p-type substrate.
Further, the photoetching of the lower end face of the p-type substrate into an arc is specifically as follows:
and photoetching the lower end face of the p-type substrate into a semicircle.
Further, growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region respectively, and growing a gate electrode on the upper surface of the insulating layer includes:
and depositing one metal of gold, copper and aluminum, respectively growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, and growing a grid electrode on the upper surface of the insulating layer.
Further, the cross section of the first groove obtained by etching is a right trapezoid, and the bottom angle of the cross section of the first groove towards the second groove is an acute angle.
Further, the cross section of the second groove obtained by etching is square.
Further, the width of the grid electrode is defined as D1, the length of the bottommost end of the first groove, which is obtained by etching, extending towards the second groove is defined as D2, and D1 and D2 meet the requirement that D2 is less than or equal to 20% D1.
Further, before growing a source and a drain on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, respectively, performing:
and respectively etching a third groove in the first N-type heavily doped region and the second N-type heavily doped region, and respectively growing a source electrode and a drain electrode in the third groove, so that the bottom end of the source electrode extends into the first N-type heavily doped region, and the bottom end of the drain electrode extends into the second N-type heavily doped region.
Accordingly, the present invention provides the following effects and/or advantages:
according to the method, the etched first groove extends to the second groove, so that the distance between the first groove and the second groove from top to bottom is shortened, the substrate is covered with Gao Kongxue-rate materials, and finally, the MOSFET device prepared by the method is formed by covering Gao Kongxue-rate material layers on the bottom end surfaces of the P-type substrates with high-hole-rate AlGaN material layers, the high-hole-rate material layers made of the high-hole-rate P-type AlGaN material are of the prior art, and due to diffusion movement, carrier concentration differences of n+ ions and P-ions corresponding to the manufactured semiconductor in the corresponding areas are large, free electrons of the N channels are inevitably diffused to the substrate at the junction between the N channels and the substrate, holes of the P region are inevitably diffused to the N region, and a depletion layer is formed at the junction as a result of diffusion. Because the metal aluminum in the source electrode s and the drain electrode d increases the concentration of free electrons in the N region, and the P-type AlGaN material layer increases the concentration of holes in the P region, so that the diffusion movement is intense, more free electrons and holes are gathered towards the junction, and finally the width of the conducting channel is widened. And more holes are gathered towards the junction so that the movement rate of electrons is higher, the problem of limited movement of electrons caused by narrower width between the bottom ends of the first N-type heavily doped region and the second N-type heavily doped region is solved, and on-resistance of the MOSFET device is reduced on the premise of ensuring the switching characteristic.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Drawings
Fig. 1 is a schematic diagram of a prior art structure.
Fig. 2 is a graph of the result obtained in step S1.
Fig. 3 is a schematic diagram of a prior art etched silicon substrate.
Fig. 4 is a schematic structural diagram of a MOSFET device obtained by the method.
Fig. 5 is a schematic diagram of a conductive channel and a depletion layer formed in this embodiment.
Fig. 6 is a diagram showing the comparison of the shapes of the conductive channel formed in the present embodiment and the conductive channel formed in the conventional rectangular N-type heavily doped region.
Fig. 7 is a schematic diagram of D1 and D2.
Description of the embodiments
For the purpose of facilitating understanding to those skilled in the art, the present invention will now be described in further detail with reference to the accompanying drawings:
referring to fig. 2-4, a method for fabricating an N-channel enhancement MOSFET device that achieves low on-resistance includes the steps of:
s1, etching a first groove 11 and a second groove 12 on one side of the upper end face of a substrate 1 doped with p-ions, wherein the first groove 11 gradually extends to the second groove 12 from top to bottom, so that the distance between the first groove 11 and the second groove 12 gradually decreases from top to bottom;
in this embodiment, the p-ion doped substrate 1 is a prior art, and may be obtained by doping p-ions in a silicon substrate. The p-ion doped substrate 1 is etched, i.e. on a silicon base. Etching methods are also known in the art.
And, before etching, photoresist may be coated on the surface of the silicon substrate, and the holes corresponding to the first trench 11 and the second trench 12 are exposed by developing after photo-etching exposure, and then etching is started. It should be noted that, referring to fig. 3, in the process of etching the silicon substrate, the etching system etches the silicon substrate layer by layer in a manner of arc scanning from left to right, so as to realize the structure that the first trench 11 gradually extends from top to bottom to the second trench 12 in this embodiment, in the process of preparing the first trench 11, the etching system may be controlled to etch from left to right in a manner of laser arc scanning, and the etching system performs laser scanning for a longer time on a side of the first trench 11 close to the second trench 12, so as to etch a trench structure that a side of the first trench 11 close to the second trench 12 extends obliquely.
S2, filling N-type silicon in the first groove 11 and the second groove 12 to form a first N-type heavily doped region 3 and a second N-type heavily doped region 4;
s3, an insulating layer 7 grows on the upper end face of the p-type substrate corresponding to the area between the first N-type heavily doped area 3 and the second N-type heavily doped area 4;
s4, respectively growing a source electrode 5 and a drain electrode 6 on the surfaces of the first N-type heavily doped region 3 and the second N-type heavily doped region 4, and growing a grid electrode 8 on the upper surface of the insulating layer 7;
in this embodiment, S2-S4 are all direct applications in the prior art, which are common techniques in the process of manufacturing MOSFET devices, and are not described herein in detail.
And S5, growing a high-hole-rate p-type AlGaN material on the lower end surface of the p-type substrate to form a high-hole-rate material layer 2.
In this step, the high hole rate material layer 2 made of the high hole rate P-type AlGaN material is in the prior art, and specific reference may be made to the chinese patent application No. 201811118793.1, "a high mobility high hole concentration P-type AlGaN material and a growth method thereof.
The product obtained in this example is shown in fig. 4.
The core technical point of the present embodiment is that when n+ ions are doped to form the first N-type heavily doped region 3 and the second N-type heavily doped region 4, the shape of the second N-type heavily doped region 4 is the same as that of the prior art, and the cross section of the second N-type heavily doped region 4 is a square structure. In the process of forming the first N-type heavily doped region 3, the lower right corner of the first N-type heavily doped region 3, that is, the surface of the first N-type heavily doped region 3, which is close to the second N-type heavily doped region 4, gradually extends toward the second N-type heavily doped region 4 so as to be close to the second N-type heavily doped region, so that the distance between the first N-type heavily doped region 3 and the second N-type heavily doped region 4 gradually decreases from top to bottom. As shown in fig. 5, it can be determined from the triangular shape that the shape of the first N-type heavily doped region 3 can increase the area of the first N-type heavily doped region 3 near the side of the second N-type heavily doped region 4, so that when the conductive channel 101 is formed between the first N-type heavily doped region 3 and the second N-type heavily doped region 4, the source end of the conductive channel 101 formed in this embodiment will be closer to the drain end, so that the overall path of the conductive channel 101 formed in this embodiment can be shortened, and the source end of the conductive channel 101 formed in this embodiment is the end surface where the first N-type heavily doped region 3 is disposed in an extended manner, so that the end surface area of the source end of the conductive channel 101 formed in this embodiment will be larger, so that the overall width of the conductive channel 101 formed in this embodiment can be increased. Meanwhile, the source end of the conductive channel 101 formed in this embodiment is closer to the drain, so that the surface with the largest voltage in the first N-type heavily doped region 3 is closer to the second N-type heavily doped region 4, which eventually results in the drain end of the conductive channel 101 formed in this embodiment being wider, and further increases the overall width of the conductive channel 101 formed in this embodiment.
Fig. 6 is a diagram showing the comparison of the shapes of the conductive channel 101 formed in the present embodiment and the conductive channel 103 formed in the conventional rectangular N-type heavily doped region.
According to the fact that the resistance is proportional to the length of the conductive channel and inversely proportional to the width, the conductive channel 101 formed by the embodiment reduces the overall length and improves the overall width, so that the RDS (ON) value corresponding to the application is reduced.
However, after the length of the conducting channel is reduced, when the forward voltage is connected between the gate and the source of the N-channel enhancement type MOS transistor, the channel in which electrons are converged near the gate is correspondingly reduced, which adversely affects the on-time of the N-channel enhancement type MOS transistor. This embodiment is further optimized by the high hole-rate material layer 2.
In this embodiment, the bottom surface of the P-type substrate 1 is covered with the Gao Kongxue high-hole-rate material layer 2 made of a high-hole-rate P-type AlGaN material, and the high-hole-rate material layer 2 made of the high-hole-rate P-type AlGaN material is in the prior art, and specific reference may be made to the chinese patent application No. 201811118793.1, i.e., a high-mobility high-hole-concentration P-type AlGaN material and a growth method thereof. The prior art has verified that the high hole rate material layer 2 made of p-type AlGaN material has high hole rate and high hole mobility. Since the diffusion motion is performed, the substance always moves from a high concentration place to a low concentration place, and therefore, since the carrier concentration difference of the n+ ions and the P-ions corresponding to the fabricated semiconductor is large in the corresponding region, free electrons of the N channel must diffuse toward the substrate at the interface between the N channel and the substrate, and holes of the P region must diffuse toward the N region at the same time, and as a result, a depletion layer is formed at the interface. Because the metal aluminum in the source electrode s and the drain electrode d increases the concentration of free electrons in the N region, and the P-type AlGaN material layer increases the concentration of holes in the P region, so that the diffusion movement is intense, more free electrons and holes are gathered towards the junction, and finally the width of the conducting channel is widened. And more holes are gathered towards the junction so that the movement rate of electrons is higher, the problem of limited movement of electrons caused by narrower width between the bottom ends of the first N-type heavily doped region 3 and the second N-type heavily doped region 4 is solved, and on-resistance of the MOSFET device is reduced on the premise of ensuring the switching characteristic.
Further, before the high-hole-rate p-type AlGaN material is grown on the lower end surface of the p-type substrate 1 to form the high-hole-rate material layer 2, performing: photoetching the lower end surface of the p-type substrate 1 into an arc shape;
the Gao Kongxue material layer 2 is arc-shaped and matched with the lower end face of the p-type substrate 1.
Further, the lower end face of the p-type substrate 1 is subjected to arc lithography specifically as follows:
the lower end face of the p-type substrate 1 is photoetched into a semicircle.
In this embodiment, when the arc-shaped p-type substrate 1 and the arc-shaped Gao Kongxue-rate material layer 2 receive a voltage between the gate electrode and the substrate, the arc-shaped substrate shortens a distance from two bottom corners to the vicinity of the gate electrode, so that electrons can be quickly migrated from each position by the arc-shaped substrate. And the substrate is made into a semi-cylindrical shape, so that the structure of the N-channel enhancement type MOS tube is more compact, the size of the N-channel enhancement type MOS tube is greatly reduced, the distance that the grid electrode attracts electrons to the inversion layer to move when the N-channel enhancement type MOS tube is conducted is further reduced by the reduction of the size, and the switching speed of the N-channel enhancement type MOS tube is guaranteed.
Further, growing a source electrode 5 and a drain electrode 6 on the surfaces of the first N-type heavily doped region 3 and the second N-type heavily doped region 4, respectively, and growing a gate electrode 8 on the upper surface of the insulating layer 7 includes:
by depositing one of gold, copper and aluminum, a source electrode 5 and a drain electrode 6 are grown on the surfaces of the first N-type heavily doped region 3 and the second N-type heavily doped region 4, respectively, and a gate electrode 8 is grown on the upper surface of the insulating layer 7.
Further, the cross section of the first groove 11 obtained by etching is a right trapezoid, and the bottom angle of the cross section of the first groove 11 towards the second groove 12 is an acute angle.
Further, the cross section of the second groove 12 obtained by etching is square.
Therefore, the cross section of the obtained first N-type heavily doped region 3 is a right trapezoid, and the bottom angle of the cross section of the first N-type heavily doped region 3 towards the second N-type heavily doped region 4 is an acute angle.
When a forward voltage is applied between the gate and the source, a certain drain current will be generated if a forward voltage is applied between d-s. At this time, along with the voltage change of the voltage Vds between d-s, a conductive channel is formed between the acute angle position of the trapezoid of the source electrode s and the right angle position of the drain electrode d, and compared with the conventional source electrode s and the drain electrode d which are manufactured into rectangles, the length of the conductive channel is reduced by the source electrode s and the drain electrode d which are manufactured into the trapezoid, which is beneficial to reducing the ON-state resistance RDS (ON).
Further, the cross section of the second N-type heavily doped region 3 is square.
Further, the width of the grid electrode is defined as D1, the length of the bottommost end of the first groove, which is obtained by etching, extending towards the second groove is defined as D2, and D1 and D2 meet the requirement that D2 is less than or equal to 20% D1.
Further, the width of the gate is defined as D1, and the length of the bottommost end of the first N-type heavily doped region extending toward the second N-type heavily doped region is D2, so that D1 and D2 satisfy D2 being less than or equal to 20% D1.
In this embodiment, referring to fig. 7, the condition that the width of the gate is D1 and the length of the first N-type heavily doped region extending from the bottommost end to the second N-type heavily doped region is D2 is defined, and the hole rate of the p-type substrate 1 can be increased on the premise of the Gao Kongxue material layer 2 by D2 being less than or equal to 20% D1, but the hole rate is not increased without limitation, and the increasing capability is limited. Therefore, the method and the device limit D1 with the D2 not exceeding 20%, so that the technical effects of improving the high hole rate of the substrate and shortening the bottom end surface distance between the first N-type heavily doped region and the second N-type heavily doped region can be balanced, and the characteristic of reducing the on-resistance on the premise of guaranteeing the on-switching characteristic is realized.
Further, before the source 5 and the drain 6 are grown on the surfaces of the first N-type heavily doped region 3 and the second N-type heavily doped region 4, respectively, performing:
etching third grooves in the first N-type heavily doped region 3 and the second N-type heavily doped region 4 respectively, and growing a source electrode 5 and a drain electrode 6 in the third grooves respectively, so that the bottom end of the source electrode 5 extends into the first N-type heavily doped region 3, and the bottom end of the drain electrode 6 extends into the second N-type heavily doped region 4.
In this embodiment, since the source s and the drain d have metals, and the metal is inserted into the N-type heavily doped region, the voltage obtained by the source 5 or the drain 6 is made to penetrate into the N-type heavily doped region through the metal, so that the voltage received by the N-type heavily doped region is more balanced in the N-type heavily doped region, the concentration of free electrons in the N-region is increased, and the width of the generated conductive channel is further increased.
Chip probe testing is carried out on the N-channel enhanced MOSFET device. The test is carried out in a standard clean factory building, the temperature is 24.0+/-2.0 ℃, and the humidity is 40.0%. A special tester for a T862 type high-voltage high-current discrete device of Shaoxing Hongbang and a UF200SA probe station of Japan TSK company are selected.
Table 1, on-resistance of MOSFET device provided herein
In the prior art, the on-resistance of the MOSFET device manufactured by the same process is about 150mΩ. Therefore, the on-resistance is effectively reduced.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms should not be understood as necessarily being directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Claims (8)
1. A preparation method of an N-channel enhanced MOSFET device for realizing low on-resistance is characterized by comprising the following steps: the method comprises the following steps:
etching a first groove and a second groove on one side of the upper end face of the substrate doped with p-ions, wherein the first groove gradually extends to the second groove from top to bottom, so that the distance between the first groove and the second groove gradually decreases from top to bottom;
filling N-type silicon in the first groove and the second groove to form a first N-type heavily doped region and a second N-type heavily doped region;
an insulating layer grows on the upper end face of the p-type substrate corresponding to a region between the first N-type heavily doped region and the second N-type heavily doped region;
respectively growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, and growing a grid electrode on the upper surface of the insulating layer;
and growing a high-hole-rate p-type AlGaN material on the lower end surface of the p-type substrate to form a high-hole-rate material layer.
2. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance of claim 1, wherein: before a high-hole-rate p-type AlGaN material grows on the lower end face of the p-type substrate to form a high-hole-rate material layer, the method comprises the following steps: photoetching the lower end surface of the p-type substrate into an arc shape;
the Gao Kongxue material layer is arc-shaped and matched with the lower end face of the p-type substrate.
3. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance of claim 2, wherein: photoetching the lower end face of the p-type substrate into an arc specifically comprises the following steps:
and photoetching the lower end face of the p-type substrate into a semicircle.
4. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance of claim 1, wherein: respectively growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, and growing a grid electrode on the upper surface of the insulating layer comprises the following steps:
and depositing one metal of gold, copper and aluminum, respectively growing a source electrode and a drain electrode on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, and growing a grid electrode on the upper surface of the insulating layer.
5. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance of claim 1, wherein: the cross section of the first groove obtained by etching is in a right trapezoid shape, and the bottom angle of the cross section of the first groove towards the second groove is an acute angle.
6. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance of claim 5, wherein: and the cross section of the second groove obtained by etching is square.
7. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance according to claim 5 or 6, wherein: and defining the width of the grid electrode as D1, and enabling the length extending from the bottommost end of the first groove to the second groove, which is obtained by etching, to be D2, wherein D1 and D2 meet the requirement that D2 is less than or equal to 20% D1.
8. The method for manufacturing an N-channel enhancement mode MOSFET device for achieving low on-resistance of claim 1, wherein: before the source electrode and the drain electrode are respectively grown on the surfaces of the first N-type heavily doped region and the second N-type heavily doped region, the method comprises the following steps:
and respectively etching a third groove in the first N-type heavily doped region and the second N-type heavily doped region, and respectively growing a source electrode and a drain electrode in the third groove, so that the bottom end of the source electrode extends into the first N-type heavily doped region, and the bottom end of the drain electrode extends into the second N-type heavily doped region.
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| CN117116994A (en) * | 2023-10-19 | 2023-11-24 | 深圳市冠禹半导体有限公司 | Groove type silicon carbide MOSFET and manufacturing process thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117116994A (en) * | 2023-10-19 | 2023-11-24 | 深圳市冠禹半导体有限公司 | Groove type silicon carbide MOSFET and manufacturing process thereof |
| CN117116994B (en) * | 2023-10-19 | 2024-01-26 | 深圳市冠禹半导体有限公司 | Groove type silicon carbide MOSFET and manufacturing process thereof |
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