CN117116994B - Groove type silicon carbide MOSFET and manufacturing process thereof - Google Patents
Groove type silicon carbide MOSFET and manufacturing process thereof Download PDFInfo
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- CN117116994B CN117116994B CN202311358779.XA CN202311358779A CN117116994B CN 117116994 B CN117116994 B CN 117116994B CN 202311358779 A CN202311358779 A CN 202311358779A CN 117116994 B CN117116994 B CN 117116994B
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000011159 matrix material Substances 0.000 claims description 29
- 238000001312 dry etching Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 229920001971 elastomer Polymers 0.000 claims description 4
- 239000000806 elastomer Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000012958 reprocessing Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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Abstract
The invention discloses a groove type silicon carbide MOSFET and a manufacturing process thereof, which relate to the technical field of semiconductor devices and comprise the following steps: the MOSFET comprises a substrate, wherein the top of the substrate is provided with a source electrode groove for installing a source electrode terminal and a drain electrode groove for installing a drain electrode terminal, the top of the source electrode terminal is connected with the top of the drain electrode terminal through a gate electrode terminal, the bottom of the substrate is provided with a main body terminal, and when the MOSFET is in a depletion type, the top of the substrate is also provided with a conductive groove filled with a conductive medium; when the MOSFET is enhanced, the source trench and the drain trench are separated by the substrate; and an epitaxial region is arranged on each of the source electrode groove and the drain electrode groove. By increasing the epitaxial region, the length of the circuit channel is shortened, and when the saturation current is reached under the condition of the same Vg, the minimum thickness Dh of the circuit channel is larger than the minimum thickness Dc of the circuit channel of a conventional MOSFET, so that the produced MOSFET can pass a larger saturation current.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a trench type silicon carbide MOSFET and a manufacturing process thereof.
Background
The trench MOSFET has the advantages of high switching speed, good frequency performance, high input impedance, small driving power, good temperature characteristic, no secondary breakdown problem and the like, and has been widely applied to the fields of voltage regulators, power management modules, electromechanical control, display control, automobile electronics and the like. A circuit channel exists between the source electrode and the drain electrode of the MOSFET, and as the voltage of the drain electrode terminal increases, the drain electrode of the MOSFET and the depletion region of the substrate increase due to reverse bias, so that the width of the circuit channel decreases, the flow of charges is restricted, and the current decreases until the saturation current is reached. However, it is a technical problem to be solved by the present invention how to obtain a larger saturation current without adjusting the threshold voltage and to produce a MOSFET that can meet this condition, which requires a controllable power supply of the gate terminal. Accordingly, there is a need for a trench silicon carbide MOSFET and a process for fabricating the same that at least partially addresses the problems of the prior art.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
To at least partially solve the above problems, the present invention provides a trench silicon carbide MOSFET comprising: a substrate, the top of the substrate is provided with a source groove for installing a source terminal and a drain groove for installing a drain terminal, the top of the source terminal is connected with the top of the drain terminal through a gate terminal, the bottom of the substrate is provided with a main body terminal,
when the MOSFET is depletion-type, the top of the substrate is also provided with a conductive groove filled with a conductive medium, the source groove and the drain groove are communicated through the conductive groove, and the gate terminal is connected with the source terminal and the drain terminal;
when the MOSFET is enhanced, the source groove and the drain groove are separated by the substrate, and the source terminal is connected with the drain terminal through the gate terminal;
and an epitaxial region is arranged on each of the source electrode groove and the drain electrode groove.
Preferably, the source trench is a vertical trench, and an epitaxial region is disposed on a sidewall of the source trench, which is close to the drain trench, and extends from the source trench to the drain trench.
Preferably, the drain trench is a vertical trench, and an epitaxial region is disposed on a sidewall of the drain trench, which is close to the source trench, and extends from the drain trench to the source trench.
Preferably, a dielectric layer is disposed between the source terminal and the drain terminal, and the gate terminal is disposed above the dielectric layer.
A manufacturing process of a groove type silicon carbide MOSFET comprises the following steps:
s1: etching the glued substrate through wet etching equipment to form a source electrode groove and a drain electrode groove;
s2: placing the substrate subjected to wet etching in dry etching equipment, and connecting and positioning the substrate with a fixed component in the dry etching equipment through a positioning component clamped on the substrate;
s3: reprocessing the source electrode groove and the drain electrode groove through dry etching equipment to form a source electrode groove with an epitaxial region and a drain electrode groove with an epitaxial region;
s4: ion implantation into the source and drain trenches, and deposition of source and drain terminals.
Preferably, in step S1, the source trench and the drain trench manufactured by the wet etching apparatus are V-shaped grooves.
Preferably, in step S2, the positioning component clamped on the substrate is composed of a fixing plate and a positioning matrix arranged on the fixing plate, one surface of the fixing plate is clamped and fixed with the substrate, the other surface of the fixing plate is connected and positioned with the fixing component on the dry etching device through the positioning matrix, and the positioning matrix is composed of a plurality of rectangular pyramids.
Preferably, the fixing component in the dry etching device is composed of a locating layer and a fixing layer, the locating layer is arranged above the fixing layer, a locating groove matrix which is adaptive to the locating matrix is arranged on the top surface of the locating layer, the locating groove matrix is composed of a plurality of locating grooves which penetrate through the locating layer and extend into the fixing layer, the shape of the locating groove is adaptive to the shape of a rectangular pyramid on the locating matrix, locating channels are arranged between the locating layer and the fixing layer, and the locating grooves in the locating groove matrix are all communicated through the locating channels;
the positioning channel is filled with an elastomer,
or the positioning channel extends to the side wall of the positioning layer and is connected with the vacuumizing equipment.
Preferably, in step S3, the dry etching apparatus performs eccentric etching on the source trench and the drain trench, and the V-shaped portion not dry etched forms the epitaxial region.
Preferably, in step S4, ions are implanted into the source trench and the drain trench to define source and drain regions, and then source metal, drain metal and gate terminal are deposited.
Compared with the prior art, the invention at least comprises the following beneficial effects:
the invention consists of a substrate, a source terminal arranged in a source groove, a drain terminal arranged in a drain groove, a main body terminal connected on the substrate, a dielectric layer connected between the source terminal and the drain terminal, and a gate terminal connected above the dielectric layer. It is noted that the source terminal and the drain terminal are identical in structure, and therefore there is no need to purposely distinguish between the source terminal and the drain terminal, i.e., one serves as the source terminal and the other serves as the drain terminal naturally. Taking an enhanced N-channel as an example, the source terminal and the drain terminal are N-type semiconductors, and the substrate is P-type semiconductor. The source terminal and the body terminal are electrically connected, a power supply can be connected between the drain terminal (connected with the positive electrode) and the source terminal (connected with the negative electrode), at this time, the voltage between the drain terminal and the source terminal is Vd, because the power supply increases the potential of the drain terminal, the depletion region between the drain terminal and the substrate is increased, and therefore, the current does not enter the source terminal from the drain terminal, so that the MOSFET is in an off state (normally closed), a channel is needed to be established again in order to enable the current to reach the source terminal from the drain terminal, a power supply is additionally arranged between the gate terminal and the source terminal, the positive electrode is connected with the gate terminal, the negative electrode is connected with the source terminal, at this time, the voltage between the gate terminal and the source terminal is Vg, because a dielectric layer exists, electrons cannot flow from the substrate to the gate terminal, the dielectric layer can block electrons, and can increase the charge on electrons (similar to a capacitor), so that more electrons are attracted, because the substrate at the gate terminal gathers a large amount of free electrons, so that the substrate near the gate terminal becomes a negative or N-type semiconductor, so that a channel is formed in the substrate, a channel connecting the source terminal and the drain terminal can be opened, namely, the channel can be opened from the drain terminal. The voltage of the gate terminal can be adjusted by changing Vg to change the thickness of the circuit channel, which can be referred to as the threshold voltage, and when the circuit paths are connected, the MOSFET is in an ohmic or linear region in which ohm's law is followed.
A problem arises in this case, namely, as the voltage increases, the depletion regions of the drain terminal and the substrate (the circuit channel portion) increase with reverse bias, as shown in fig. 3, and the depletion region in the circuit channel increases from the drain terminal toward the source terminal, thereby reducing the width of the channel, limiting the flow of charge, and resulting in a reduction in current (the depletion type changes the current magnitude through the conductive channel on the same principle, except that the depletion type requires a negative gate voltage to realize the open circuit), and when the voltage increases, the circuit channel is completely blocked by the depletion region, which is called pinch-off effect, but when in practice, the circuit channel is not completely blocked, but a constant saturation current is formed, and the voltage generating the saturation current is the saturation voltage. In order to increase the saturation current, the threshold voltage of the gate terminal is generally increased to increase the width of the circuit channel, thereby increasing the saturation current. Since the method needs to change Vg, we propose an embodiment of changing saturation current at the same Vg, that is, we add epitaxial regions on the source trench and the drain trench, as shown in fig. 4, by increasing the epitaxial regions, shortening the distance between the drain trench and the drain trench on the end face, and further shortening the length of the circuit channel, when the saturation current is reached at the same Vg, the minimum thickness Dh of the circuit channel is greater than the minimum thickness Dc of the circuit channel of the MOSFET processed in the conventional processing manner, as shown in fig. 5. Thus realizing that the produced MOSFET can pass a larger saturation current without changing Vg.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
fig. 1 is a schematic structural diagram of an enhanced MOSFET in the prior art.
Fig. 2 is a schematic diagram of a depletion MOSFET in the prior art.
Fig. 3 is a schematic diagram of a structure in which a depletion region increases.
Fig. 4 is a schematic structural diagram of a trench silicon carbide MOSFET according to the present invention.
Fig. 5 is a schematic diagram of the minimum thickness of the channel of the trench silicon carbide MOSFET circuit according to the present invention compared with the prior art (dashed line portion).
Fig. 6 is a schematic structural diagram of a source trench and a drain trench manufactured by a wet etching apparatus in the trench type silicon carbide MOSFET manufacturing process S1 according to the present invention.
Fig. 7 is a schematic diagram of a dry etching apparatus after processing a source trench and a drain trench in the trench silicon carbide MOSFET manufacturing process S3 according to the present invention.
Fig. 8 is a schematic structural diagram of a positioning component and a fixing component in the manufacturing process S2 of the trench silicon carbide MOSFET according to the present invention.
Fig. 9 is a partial top view and a cross-sectional view of a fixing component in the trench silicon carbide MOSFET manufacturing process S2 according to the present invention.
Fig. 10 is a schematic diagram of a positioning component before being connected to a fixing component (shown as C in the figure) and after being connected (shown as D in the figure) in the manufacturing process S2 of a trench silicon carbide MOSFET according to the present invention.
In the figure: 1 substrate, 11 source trench, 12 drain trench, 2 source terminal, 3 drain terminal, 4 gate terminal, 5 body terminal, 6 dielectric layer, 7 depletion region, 8 alignment element, 81 fixing plate, 82 alignment matrix, 9 fixing element, 91 alignment layer, 92 fixing layer, 93 alignment channel.
Description of the embodiments
The present invention is described in further detail below with reference to the drawings and examples to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
As shown in fig. 1 to 10, the present invention provides a trench silicon carbide MOSFET and a process for manufacturing the same, including: a substrate 1, the top of the substrate 1 being provided with a source trench 11 for mounting a source terminal 2 and a drain trench 12 for mounting a drain terminal 3, the top of the source terminal 2 being connected to the top of the drain terminal 3 through a gate terminal 4, the bottom of the substrate 1 being provided with a body terminal 5,
when the MOSFET is depletion-type, a conductive trench filled with a conductive medium is further provided on the top of the substrate 1, the source trench 11 and the drain trench 12 are communicated through the conductive trench, and the gate terminal 4 is connected with the source terminal 2 and the drain terminal 3;
when the MOSFET is enhanced, the source trench 11 and the drain trench 12 are separated by the substrate 1, and the source terminal 2 is connected to the drain terminal 3 through the gate terminal 4;
an epitaxial region is provided on both the source trench 11 and the drain trench 12.
The source trench 11 is a vertical trench, and an epitaxial region is disposed on a sidewall of the source trench 11, which is close to the drain trench 12, and extends from the source trench 11 toward the drain trench 12.
The drain trench 12 is a vertical trench, and an epitaxial region is disposed on a sidewall of the drain trench 12, which is close to the source trench 11, and extends from the drain trench 12 toward the source trench 11.
A dielectric layer 6 is arranged between the source terminal 2 and the drain terminal 3, and the gate terminal 4 is arranged above the dielectric layer 6.
The technical scheme has the working principle and beneficial effects that: MOSFETs are typically made of semiconductor materials such as silicon and because the conductivity of the semiconductor is between the conductor and the insulator, we add impurities to the silicon crystal to give it better conductivity, if pentavalent impurities are added then the resulting semiconductor is called N-type, if trivalent impurities are added then the resulting semiconductor is P-type, when the P-type and N-type semiconductors are connected together, electrons of the N-type semiconductor at the junction will fill into holes of the P-type semiconductor, thereby depleting the charge near the junction, forming a depletion region 7, as shown in fig. 1, 2. Depletion region 7 decreases upon energization, referred to as forward bias (e.g., P-type connected cell positive electrode, N-type connected cell negative electrode); the depletion region 7 increases upon energization, referred to as reverse bias. MOSFETs are generally classified into depletion type (provided with a conductive trench through which the MOSFET is turned on when there is no voltage across the gate terminal 4, conductivity is reduced when there is a voltage across the gate terminal 4) and enhancement type (non-conductive trench, device is turned off when there is no voltage across the gate terminal 4, device is turned on when there is a maximum voltage across the gate terminal 4), and depletion type and enhancement type can be subdivided into N-channel and P-channel types according to material selection of the substrate 1, the source terminal 2 and the drain terminal 3, and the invention does not further limit the channel selection, i.e., whether N-channel or P-channel is selected, and neither depletion type nor enhancement type should be included in the scope of the invention.
The invention consists of a substrate 1, a source terminal 2 arranged in a source trench 11, a drain terminal 3 arranged in a drain trench 12, a body terminal 5 connected to the substrate 1, a dielectric layer 6 connected between the source terminal 2 and the drain terminal 3, and a gate terminal 4 connected above the dielectric layer 6. It should be noted that the source terminal 2 and the drain terminal 3 are identical in structure, and therefore it is not necessary to purposely distinguish between the source terminal 2 and the drain terminal 3, i.e., one is used as the source terminal 2 and the other is naturally used as the drain terminal 3. Taking an enhanced N-channel as an example, i.e., the source terminal 2 and the drain terminal 3 are N-type semiconductors, and the substrate 1 is P-type semiconductor. The source terminal 2 and the body terminal 5 are electrically connected, a power supply can be connected between the drain terminal 3 (connected with the positive electrode) and the source terminal 2 (connected with the negative electrode), at this time, the voltage between the drain terminal 3 and the source terminal 2 is Vd, because the power supply increases the potential of the drain terminal 3, the depletion region 7 between the drain terminal 3 and the substrate 1 is increased, so that the current does not enter the source terminal 2 from the drain terminal 3, and the MOSFET is in an off state (normally closed), in order to enable the current to reach the source terminal 2 from the drain terminal 3, a channel is required to be established again, a power supply is additionally arranged between the gate terminal 4 and the source terminal 2, the positive electrode is connected with the gate terminal 4, the negative electrode is connected with the source terminal 2, at this time, the voltage between the gate terminal 4 and the source terminal 2 is Vg, because the dielectric layer 6 is present, electrons cannot flow from the substrate 1 to the gate terminal 4, and besides the electrons can be blocked, the dielectric layer 6 can also increase the charge on the electrons (similar to a capacitor), so that more electrons are attracted, because the substrate 1 at the gate terminal 4 gathers a large number of free electrons, so that the substrate 1 near the gate terminal 4 can reach the source terminal 2, and a channel is formed in the drain terminal 3, i.e. the channel is opened, the channel is formed from the drain terminal 2, and the channel is formed in the drain terminal 2, and the channel is similar to the channel is formed. The voltage of the gate terminal 4 can be adjusted by changing Vg to change the thickness of the circuit channel, which can be referred to as the threshold voltage, and when the circuit paths are connected, the MOSFET is in the ohmic or linear region, in which the ohm's law is followed.
A problem arises in this case that as the voltage increases, the drain terminal 2 and the depletion region 7 of the substrate 1 (the circuit channel portion) increase with reverse bias, as shown in fig. 3, and the depletion region 7 in the circuit channel increases from the drain terminal 3 toward the source terminal 2, thereby reducing the channel width, limiting the charge flow, resulting in a reduced current (the depletion type requires a negative gate voltage to achieve an off-state, although the principle of changing the current magnitude through the conductive channel is the same), and when the voltage increases, the circuit channel is completely blocked by the depletion region 7, which is referred to as pinch-off effect, but when in practice, the circuit channel is not completely closed, but a constant saturation current is formed, and the voltage at which the saturation current is generated is the saturation voltage. In order to increase the saturation current, the threshold voltage of the gate terminal 4 is generally increased to increase the width of the circuit channel, thereby increasing the saturation current. Since the method needs to change Vg, we propose an embodiment of changing saturation current at the same Vg, that is, we add an epitaxial region on the source trench 11 and the drain trench 12, as shown in fig. 4, and by increasing the epitaxial region, shorten the distance between the drain trench 12 and the drain trench 11 on the end face, and further shorten the length of the circuit channel, when the saturation current is reached at the same Vg, the minimum thickness Dh of the circuit channel is greater than the minimum thickness Dc of the circuit channel of the MOSFET processed in the conventional processing manner, as shown in fig. 5. Thus realizing that the produced MOSFET can pass a larger saturation current without changing Vg.
The invention provides a manufacturing process of a groove type silicon carbide MOSFET, which comprises the following steps:
s1: isotropically etching the glued substrate 1 by wet etching equipment to form a source trench 11 and a drain trench 12, wherein an alkaline solution is required to be adopted for processing the source trench 11 and the drain trench 12 into V-shaped grooves, and the etching depth should be avoided from being too deep;
s2: the substrate 1 after wet etching is placed in dry etching equipment for anisotropic etching, and is connected and positioned with a fixed component 9 in the dry etching equipment through a positioning component 8 clamped on the substrate 1 (in practice, the difficulty of etching processing is not in etching, while in positioning, because the existing dry etching equipment is provided with a plurality of etching equipment such as CCP and ICP, the invention needs to process an epitaxial region in a groove, so that an inclined plane needs to be processed by wet etching firstly, and then the inclined plane and depth at the other side need to be processed by dry etching, so that the accuracy of a processing position can be ensured after the equipment is converted, and the problem to be solved by the process is solved);
the positioning component 8 clamped on the substrate 1 consists of a fixed plate 81 and a positioning matrix 82 arranged on the fixed plate 81, wherein one surface of the fixed plate 81 is clamped and fixed with the substrate 1 (the clamping and fixing of the fixed plate 81 and the substrate 1 can be realized by adopting conventional technical means, such as side groove clamping and the like), the other surface of the fixed plate is connected and positioned with the positioning component 9 on the dry etching equipment through the positioning matrix 82, and the positioning matrix 82 consists of a plurality of rectangular pyramids;
the fixed subassembly 9 in the dry etching equipment comprises locating layer 91 and fixed layer 92, the locating layer 91 sets up the top of fixed layer 92, the top surface of locating layer 91 be provided with the constant head tank matrix that the matrix 82 suited, the constant head tank matrix is run through by a plurality of locating layer 91 to extend to the constant head tank in the fixed layer 92 constitutes, the shape of constant head tank with the shape of the rectangular pyramid on the matrix 82 suits, and when transferring processing equipment, the rectangular pyramid of matrix 82 inserts in the constant head tank of matrix, adopts matrix type constant head tank and rectangular pyramid to realize quick grafting location to guarantee the fastness after the location. A positioning channel 93 is arranged between the positioning layer 91 and the fixing layer 92, and positioning grooves in the positioning groove matrix are communicated through the positioning channel 93;
in order to increase the firmness of the connection, we present two solutions:
1. the friction between the single rectangular pyramid and the positioning groove is increased by filling the positioning channel 93 with an elastomer, which may be a silica gel pad, and in this embodiment, a fixing device capable of being pressed against the fixing plate 81, such as a buckle, a screw, etc., is required to be arranged on the dry etching device, and this method is generally not adopted because the structure is complex and more additional devices are required.
2. The positioning channel 93 extends to the side wall of the positioning layer 91 and is connected with a vacuum pumping device; after the rectangular pyramid is inserted into the positioning groove, the vacuumizing equipment is started to suck air so as to fix and position the positioning matrix. Since dry etching needs to be performed under a specified vacuum pressure, there is no need to separately provide a vacuum-pumping apparatus, and this embodiment is simple in structure and can be used in common, so that it is generally employed in actual production.
S3: eccentrically etching the source trench 11 and the drain trench 12 by a dry etching apparatus (i.e., when the dry etching is performed, the inclined plane of the source trench 11 near the drain trench 12 side is reserved, and similarly, the inclined plane of the drain trench 12 near the source trench 11 side is reserved, and the V-shaped part which is not dry etched forms an epitaxial region), and processing to a specified depth, so as to form the source trench 11 with the epitaxial region and the drain trench 12 with the epitaxial region;
s4: implanting ions into the source trench 11 and the drain trench 12, depositing the source terminal 2 and the drain terminal 3; ions are implanted into the source trench 11 and the drain trench 12 to define source and drain regions, and then source metal, drain metal and gate terminal 4 are deposited.
The MOSFET processed by the production process can effectively shorten the length of a circuit channel, and meanwhile, compared with the traditional MOSFET, the device has higher processing precision and smaller volume of a finished product.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (4)
1. The manufacturing process of the groove type silicon carbide MOSFET is characterized by comprising the following steps of:
s1: etching the glued substrate (1) through wet etching equipment to form a source electrode groove (11) and a drain electrode groove (12);
s2: placing the substrate (1) subjected to wet etching in dry etching equipment for anisotropic etching, and connecting and positioning the substrate with a fixed component (9) in the dry etching equipment through a positioning component (8) clamped on the substrate (1);
s3: reprocessing the source trench (11) and the drain trench (12) by a dry etching device to form a source trench (11) with an epitaxial region and a drain trench (12) with an epitaxial region;
s4: implanting ions into the source trench (11) and the drain trench (12), and depositing a source terminal (2) and a drain terminal (3);
in the step S2, a positioning component (8) clamped on a substrate (1) consists of a fixed plate (81) and a positioning matrix (82) arranged on the fixed plate (81), one surface of the fixed plate (81) is clamped and fixed with the substrate (1), the other surface of the fixed plate is connected and positioned with a fixing component (9) on dry etching equipment through the positioning matrix (82), and the positioning matrix (82) consists of a plurality of rectangular pyramids;
the fixing assembly (9) in the dry etching equipment is composed of a locating layer (91) and a fixing layer (92), the locating layer (91) is arranged above the fixing layer (92), a locating channel (93) is arranged between the locating layer (91) and the fixing layer (92), the locating channel matrix is composed of a plurality of locating grooves penetrating through the locating layer (91) and extending into the fixing layer (92), the shape of each locating groove is matched with that of a quadrangular pyramid on the locating matrix (82), when the processing equipment is transferred, the quadrangular pyramid of the locating matrix (82) is inserted into the locating groove of the locating channel matrix, and locating grooves in the locating channel matrix are all communicated through the locating channel (93);
the positioning channel (93) is filled with an elastomer,
or the positioning channel (93) extends to the side wall of the positioning layer (91) and is connected with a vacuumizing device;
when the positioning channel (93) is filled with an elastomer, the dry etching equipment is provided with a fixing equipment capable of being pressed on the fixing plate (81);
when the positioning channel (93) extends to the side wall of the positioning layer (91) and is connected with the vacuumizing device, the vacuumizing device is started to suck air after the rectangular pyramid is inserted into the positioning groove.
2. The process for fabricating a trench type silicon carbide MOSFET according to claim 1, wherein in step S1, the source trench (11) and the drain trench (12) fabricated by the wet etching apparatus are V-shaped grooves.
3. The process for fabricating a trench type silicon carbide MOSFET according to claim 1, wherein in step S3, the dry etching apparatus performs eccentric etching on the source trench (11) and the drain trench (12), and V-shaped portions not dry etched form an epitaxial region.
4. The process according to claim 1, wherein in step S4 ions are implanted into the source trench (11) and the drain trench (12), defining source and drain regions, and then source metal, drain metal and gate terminal (4) are deposited.
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