CN111969064B - Parasitic LDMOS device and manufacturing method thereof - Google Patents
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 17
- 210000000746 body region Anatomy 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 230000002411 adverse Effects 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 10
- 238000005859 coupling reaction Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
Abstract
The invention provides a parasitic LDMOS device and a manufacturing method thereof, wherein the parasitic LDMOS device comprises: the device comprises a substrate, an epitaxial layer formed on the substrate, and an LDMOS device and a Schottky diode which are formed in the epitaxial layer. Through designing the controllable structure of access of a kind of schottky diode for the electric current of schottky diode just can be switched on to the drain electrode of LDMOS by the drift region when need form the afterflow, and under the non-operating condition, the schottky diode will be kept apart, thereby stop the adverse effect that brings to LDMOS device of schottky diode, overcome the not enough that exist among the prior art.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a parasitic LDMOS device and a manufacturing method thereof.
Background
Among semiconductor power devices, MOS devices play an important role, wherein a Double-Diffused metal-oxide-semiconductor field-effect transistor (DMOS) is one of the most commonly used power device forms, and DMOS devices are mainly classified into two types, namely, a vertical DMOS (VDMOS for short) and a lateral DMOS (LDMOS for short). The parasitic LDMOS device is a voltage control type device, has the advantages of high voltage resistance, high input impedance, good safe working area, low power consumption and the like compared with a bipolar device, and is generally applied to motor driving, automobile electronics, industrial control and grid-like switch power supply circuits.
In many application scenarios, the parasitic LDMOS device needs to be connected in parallel with a schottky diode to realize freewheeling. In order to improve the stability of the system, the volume of the system is reduced. Therefore, the parasitic LDMOS device and the schottky diode (SBD) are integrated together in the prior art.
However, in the conventional integrated arrangement mode, when the schottky diode is parasitic on the LDMOS device, electrons on the schottky diode may be connected in series in the drift region of the LDMOS device when the schottky diode is turned on, which results in large leakage current of the LDMOS device during operation, and the on-resistance in the channel is reduced due to the extra electrons, so that the Breakdown Voltage (BV) of the LDMOS device is reduced, which greatly affects the performance of the LDMOS device.
Therefore, it is necessary to provide a further solution to the above problems.
Disclosure of Invention
The invention aims to provide a parasitic LDMOS device and a manufacturing method thereof, and by designing an access controllable structure of a Schottky diode, the current of the Schottky diode can be conducted to the drain electrode of the LDMOS from a drift region only when freewheeling is required to be formed, and the Schottky diode is isolated in a non-working state, so that the adverse effect of the Schottky diode on the LDMOS device is avoided, and the defects in the prior art are overcome.
To achieve the above object, the present invention provides a parasitic LDMOS device, which includes:
a substrate of a first conductivity type;
an epitaxial layer having a second conductivity type formed on the substrate, and an LDMOS device region and a co-operating device region formed in the epitaxial layer,
the LDMOS device comprises a source region, a drain region and a gate region, wherein the source region and the drain region are respectively distributed in two side regions of the gate region;
the combined device region is arranged at the other side of the drain region relative to the gate region, a Schottky diode is arranged in the combined device region, the Schottky diode comprises an anode and a metal cathode in contact with the anode,
the combined device region further comprises a body region with the first conductivity type and arranged around the anode, and a grid-like switch arranged on the body region, wherein the body region isolates the Schottky diode from the LDMOS;
when the parasitic LDMOS device needs to freewheel, the grid-like switch is switched on to turn on voltage, so that a conductive channel is formed between the Schottky diode and the drain region.
Preferably, the gate-like switch is a gate structure which surrounds the schottky diode by one circle and comprises a gate oxide layer which is contacted with the surface of the first conduction type body region and a gate electrode which is positioned on the gate oxide layer.
Preferably, the metal cathode of the schottky diode is surrounded by the gate structure and is isolated from the gate electrode of the gate-like switch by the gate oxide layer.
Preferably, the anode of the schottky diode is formed by heavily doping ions of the second conductive type.
Preferably, a drift region is arranged between the source region and the drain region, and one of shallow trench isolation, a field oxide layer or a thick oxide layer is arranged on the surface of the drift region.
Preferably, the gate region includes a gate oxide layer and a gate electrode disposed on the gate oxide layer, and a portion of the gate electrode extends onto the shallow trench isolation, the field oxide layer or the thick oxide layer to form a field plate.
Preferably, the epitaxial layer is a lightly doped high resistance layer.
The invention also provides a manufacturing method of the parasitic LDMOS device, which comprises the following steps:
a1, providing a substrate of a first conduction type, and manufacturing a lightly doped epitaxial layer of a second conduction type on the substrate;
a2, respectively forming an LDMOS and a schottky diode in the epitaxial layer such that the schottky diode is located at one side of the LDMOS drain and away from the channel in the LDMOS, the schottky diode comprising a heavily doped anode of the second conductivity type and a metal cathode in contact with the anode, the schottky diode further comprising a body region of the first conductivity type around the schottky diode and a gate-like switch disposed on the body region of the first conductivity type.
Preferably, the source region of the LDMOS includes a first conductive type well region, and the first conductive type body region and the first conductive type well region are formed in the same doping process.
Preferably, the drain region or the source region of the LDMOS includes a heavily doped region of the second conductivity type, and the heavily doped anode of the second conductivity type of the schottky diode and the heavily doped region of the second conductivity type in the drain region or the source region of the LDMOS are formed in the same heavily doped process.
Compared with the prior art, the invention has the beneficial effects that: the parasitic LDMOS device and the coupling device are arranged in an isolated mode, and the similar grid switch is adopted to control the opening and closing of a channel between the parasitic LDMOS device and the coupling device. The channel between the parasitic LDMOS device and the coupling device can be opened under the condition that follow current is needed, and therefore the negative effect of the coupling device on the parasitic LDMOS device is effectively eliminated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a parasitic LDMOS device according to an embodiment of the invention.
Fig. 2a to fig. 2d are schematic cross-sectional views of devices at various steps corresponding to a method for manufacturing a parasitic LDMOS device according to an embodiment of the invention.
Detailed Description
The present invention is described in detail below with reference to various embodiments, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should be able to make modifications and substitutions on the functions, methods, or structures of these embodiments without departing from the scope of the present invention.
As shown in fig. 1, an embodiment of the invention provides a parasitic LDMOS device, which includes: the device comprises a substrate 1, an epitaxial layer 2 formed on the substrate 1, an LDMOS device region and a combined device region formed in the epitaxial layer 2. The substrate 1 may be a P-type substrate, and the epitaxial layer 2 is usually a lightly doped high resistance layer, and the doping type may depend on the device type. For example, when a P-type LDMOS is selected as the parasitic LDMOS device of the present invention, the epitaxial layer 2 may be a P-type doped layer, and when an N-type LDMOS is selected, the epitaxial layer 2 may be an N-type doped layer.
The parasitic LDMOS device of the present invention is described below with an N-type parasitic LDMOS device as an example.
The parasitic LDMOS device comprises an LDMOS device region and a combined device region, wherein the LDMOS region is provided with a source electrode region S, a drain electrode region D and a gate electrode region G. In a preferred embodiment, the source region S and the drain region D are respectively distributed in two side regions of the gate region G, wherein the drift region 3 is disposed between the source region S and the drain region D, when the parasitic LDMOS device operates, the drift region 3 can form a channel for carriers to move, and the region can be switched between on and off states under the control of the gate region G, so as to achieve the device efficacy of the parasitic LDMOS. Specifically, the drain region D is formed on the drift region 3 side, and includes a heavily doped N + region and a drain electrode disposed on the N + region and in ohmic contact with the N + region. A source region S and a gate region G are formed at the other side of the drift region 3, the source region S including a P-well S1, a P-type heavily doped region S2 and an N-type heavily doped region S3 formed in the P-well S1, and a source electrode on the P-type heavily doped region S2 and the N-type heavily doped region S3 and in ohmic contact with the P-type heavily doped region S2 and the N-type heavily doped region S3. The gate region G includes a gate oxide G1 disposed on the P-type doped region S1 and a gate electrode disposed on the gate oxide G1. In one embodiment, the surface of the drift region 3 may also be formed with a Shallow Trench Isolation (STI), a field oxide layer or a thick oxide layer, and the gate electrode may partially extend onto the STI, the field oxide layer or the thick oxide layer, so as to form a field plate above the drift region 3 to improve the breakdown voltage.
The combined device region is arranged at the other side of the drain region D relative to the gate region G. The coupling device is used for realizing a certain function, so that the parasitic LDMOS device can better meet the application requirement of an actual scene. In this embodiment, the device is a schottky diode comprising an N-type heavily doped anode 5 and a metal cathode 4 in contact with the N-type heavily doped anode 5. At the moment, the Schottky diode used in parallel can form a parallel connection use relation with the parasitic LDMOS device in the application process of the parasitic LDMOS device, so that follow current of the parasitic LDMOS device is realized, and the stability of a system where the parasitic LDMOS device is located is improved.
In order to enable the Schottky diode to be used during freewheeling and not to form a coupling relation with a parasitic LDMOS device when no freewheeling is needed, a circle of P-type body regions (Pbody)7 is arranged around the anode 5, and the Pbody regions 7 are used for isolating the Schottky diode from the LDMOS device, especially isolating a channel of the LDMOS device, so that electrons are still provided for the drift region 3 when the Schottky diode does not need to work, and the breakdown voltage of the LDMOS device is reduced. Meanwhile, a similar grid switch 6 is arranged on the Pbdoy region 7, the similar grid switch 6 initially blocks a connecting channel, and when the parasitic LDMOS device needs to continue current, the similar grid switch 6 is connected to a starting voltage, so that electrons float up to the surface of the Pbdoy region 7, and a connecting channel is formed between the Schottky diode and the drain region D of the LDMOS. Due to the design, the channel between the parasitic LDMOS device and the combined device is opened through the similar grid switch 6 only under the condition that follow current is needed, and the negative influence of the combined device on the parasitic LDMOS device is effectively eliminated.
In one embodiment, the gate-like switch 6 may be a gate structure that wraps around the schottky diode and includes a gate oxide layer in contact with the surface of the Pbody region 7 and a gate electrode on the gate oxide layer, and also the gate structure may extend partially over the epitaxial layer to form a field plate. The metal cathode 4 of the schottky diode is surrounded by the gate structure of the gate-like switch 6 and is isolated from the gate electrode of the gate-like switch 6 by a gate oxide layer. In the invention, when the parasitic LDMOS device needs to follow current, the gate structure of the gate-like switch 6 is connected with the gate of the LDMOS in a short circuit mode or connected with an external high potential to realize the connection of the connection channel.
The working principle of the device is as follows: when no schottky diode is required to freewheel, the gate-like switch 6 is floated or low-voltage, and the interface between Pbody7 and drift region 3 is depleted of electrons and holes, the schottky diode is electrically isolated from its state by Pbody7 regardless of the applied voltage. At this time, if a turn-on voltage is applied to the gate of the LDMOS, the channel of the LDMOS is opened so that current can normally flow through the drain and the source, and the channel is not affected by the schottky diode. When the schottky diode is required to generate follow current to work, a conducting voltage is applied to the grid-like switch 6, so that electrons float upwards to form a conducting channel between the schottky diode and the drain region D, and if current is formed on the schottky diode, the current can be output to the drain through the channel so as to follow current for the LDMOS.
Because the on-voltage of the Schottky diode is smaller than that of the LDMOS device, current can be generated when the LDMOS is not turned on, and therefore the LDMOS device can meet the working requirement in some scenes needing follow current. In addition, a Pbody area is formed between the Schottky diode and the drift area 3, and the grid electrode is manufactured on the Pbody area, so that whether the Schottky diode is connected or not can be controlled in an active grid electrode switch mode, the performance of the LDMOS is not influenced when the Schottky diode is in a non-working state, and the defect that the breakdown voltage is reduced in the existing LDMOS combined device is overcome.
Based on the same inventive concept, the invention also provides a manufacturing method of the parasitic LDMOS device. Referring to fig. 2a to fig. 2c, fig. 2a to fig. 2d are schematic cross-sectional views of devices at steps corresponding to a method for manufacturing a parasitic LDMOS device according to an embodiment of the present invention, as shown in the drawings, the method for manufacturing a parasitic LDMOS device according to the embodiment includes the following steps:
a1, providing a P-type substrate 1, and fabricating an N-type lightly doped epitaxial layer 2 on the P-type substrate 1, as shown in fig. 2 a.
A2, forming an LDMOS and a schottky diode in epitaxial layer 2, respectively, such that the schottky diode is located at one side of the LDMOS drain and away from the channel 3 in the LDMOS, the schottky diode comprising an N-type heavily doped anode 5 and a metal cathode 4 in contact with the anode 5, the schottky diode further comprising a Pbody region 7 around the schottky diode and a gate-like switch 6 arranged on the Pbody region 7, as shown in fig. 2 d.
As shown in fig. 2b, in the present embodiment, the Pbody region 7 of the schottky diode and the pwell region S1 in the LDMOS source region S can be formed in the same doping process. That is, the P-well region and the Pbody region are opened in one photolithography process using one photomask, and then P-ion implantation is performed, thereby forming the two regions.
As shown in fig. 2c, in this embodiment, the anode region 5 of the schottky diode and the N-type heavily doped region S3 in the drain region D1 or the source region in the LDMOS may be formed in one doping process. Even if one photomask is used, the anode region 5 of the schottky diode and the opening of the N-type heavily doped region S3 in the drain region D1 or the source region in the LDMOS are formed in one photolithography process, and then N ion implantation is performed, thereby forming the two regions.
In the parasitic LDMOS device, when the combined device is manufactured, almost the same photoetching can be shared in the manufacturing process of the LDMOS device, and only a mask (mask) for photoetching needs to be specially designed to match the graphs required by the devices, so that no extra photoetching process is brought, and the manufacturing cost of the parasitic LDMOS device is greatly reduced.
In the above embodiments, only the N-channel LDMOS device is used as an illustration, it should be understood that when the P-type LDMOS device is replaced, the opposite type ion doping is performed only on each functional region for realizing communication conduction, and no further description is given here.
In summary, the parasitic LDMOS device and the coupling device are isolated, and the gate-like switch is used to control the on and off of the channel between the parasitic LDMOS device and the coupling device. The channel between the parasitic LDMOS device and the coupling device can be opened under the condition that follow current is needed, and therefore the negative effect of the coupling device on the parasitic LDMOS device is effectively eliminated.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (9)
1. A parasitic LDMOS device, comprising:
a substrate of a first conductivity type;
an epitaxial layer having a second conductivity type formed on the substrate, and an LDMOS device region and a co-operating device region formed in the epitaxial layer,
the LDMOS device region comprises a source region, a drain region and a gate region, wherein the source region and the drain region are respectively distributed in two side regions of the gate region;
the combined device region is arranged on the other side of the drain region opposite to the gate region, a Schottky diode is arranged in the combined device region, the Schottky diode comprises an anode and a metal cathode in contact with the anode, the anode of the Schottky diode is formed by heavily doping ions of the second conduction type,
the combined device region further comprises a body region with a first conduction type and arranged around the anode, and a grid-like switch arranged on the body region, wherein the body region isolates the Schottky diode from the LDMOS device region;
when the parasitic LDMOS device needs to freewheel, the grid-like switch is switched on to turn on voltage, so that a conductive channel is formed between the Schottky diode and the drain region.
2. The parasitic LDMOS device set forth in claim 1 wherein said gate-like switch is a gate structure which wraps around said schottky diode and includes a gate oxide layer in contact with the surface of said first conductivity type body region and a gate electrode on said gate oxide layer.
3. The parasitic LDMOS device of claim 2, wherein the metal cathode of the schottky diode is surrounded by the gate structure and is isolated from the gate electrode of the gate-like switch by the gate oxide layer.
4. The parasitic LDMOS device of claim 1, wherein a drift region is disposed between the source and drain regions, and a surface of the drift region is provided with one of shallow trench isolation, field oxide layer, or thick oxide layer.
5. The parasitic LDMOS device of claim 4, wherein the gate region comprises a gate oxide and a gate electrode disposed on the gate oxide, a portion of the gate electrode extending over the shallow trench isolation, field oxide, or thick oxide to form a field plate.
6. The parasitic LDMOS device of claim 4, wherein the epitaxial layer is a lightly doped high resistance layer.
7. A method for fabricating the parasitic LDMOS device of any one of claims 1-6, comprising:
a1, providing a substrate of a first conduction type, and manufacturing a lightly doped epitaxial layer of a second conduction type on the substrate;
a2, respectively forming an LDMOS and a schottky diode in the epitaxial layer such that the schottky diode is located at one side of the LDMOS drain and away from the channel in the LDMOS, the schottky diode comprising a heavily doped anode of the second conductivity type and a metal cathode in contact with the anode, the schottky diode further comprising a body region of the first conductivity type around the schottky diode and a gate-like switch disposed on the body region of the first conductivity type.
8. The method of claim 7, wherein the source region of the LDMOS comprises a first-conductivity-type well region, and the first-conductivity-type body region and the first-conductivity-type well region are formed in a same doping process.
9. The method of claim 7, wherein the drain or source region of the LDMOS comprises a heavily doped region of the second conductivity type, and wherein the heavily doped anode of the Schottky diode of the second conductivity type is formed in the same heavily doped process as the heavily doped region of the second conductivity type in the drain or source region of the LDMOS.
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| US9196723B1 (en) * | 2014-12-08 | 2015-11-24 | United Microelectronics Corp. | High voltage semiconductor devices with Schottky diodes |
| US10879230B2 (en) * | 2016-06-17 | 2020-12-29 | Infineon Technologies Americas Corp. | Schottky integrated high voltage terminations and related HVIC applications |
| CN110176488A (en) * | 2018-02-20 | 2019-08-27 | 马克西姆综合产品公司 | Ldmos transistor with breakdown voltage clamper |
| CN108447913B (en) * | 2018-05-21 | 2020-09-29 | 电子科技大学 | LDMOS device integrated with Schottky diode |
| TWI668838B (en) * | 2019-01-08 | 2019-08-11 | 立錡科技股份有限公司 | High voltage device and manufacturing method thereof |
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