CN113345964B

CN113345964B - Transverse double-diffusion transistor

Info

Publication number: CN113345964B
Application number: CN202110533925.2A
Authority: CN
Inventors: 韩广涛; 王炜槐
Original assignee: Joulwatt Technology Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2021-05-17
Filing date: 2021-05-17
Publication date: 2022-05-10
Anticipated expiration: 2041-05-17
Also published as: CN113345964A

Abstract

The invention provides a transverse double-diffused transistor, wherein a main device region of the transverse double-diffused transistor comprises a first transistor, a second transistor and a first ESD device arranged between the first transistor and the second transistor; the first transistor and the second transistor are provided with a commonly connected source end, a commonly connected drain end, a commonly connected grid end and a commonly connected body end; the first ESD device comprises a cathode connected to the commonly-connected grid end and two anodes arranged on the left side and the right side of the cathode, and the two anodes are connected to the commonly-connected source end; the auxiliary device region comprises a second ESD device, the input end of the second ESD device is connected with the common-connection grid end, and the output end of the second ESD device is grounded. The invention can overcome the damage caused by non-uniform opening of the device when ESD is injected from the drain terminal in the prior art, thereby improving the ESD prevention capability of the device.

Description

Transverse double-diffusion transistor

Technical Field

The invention relates to the technical field of semiconductors, in particular to a transverse double-diffused transistor.

Background

Among semiconductor power devices, MOS devices play an important role, wherein a Double-Diffused metal-oxide-semiconductor field-effect transistor (DMOS) is one of the most commonly used power device forms, and DMOS devices are mainly classified into two types, namely, a vertical DMOS (VDMOS for short) and a lateral DMOS (LDMOS for short). The LDMOS device is a voltage control type device, has the advantages of high withstand voltage, high input impedance, good safe working area, low power consumption and the like compared with a bipolar device, and is generally applied as a high-voltage power device in motor driving, automotive electronics, industrial control, and switching power supply circuits.

An ultra-high voltage lateral double diffused transistor (UHV LDMOS) is often used in a power management chip, and its drain and source terminals are used as external pins. In such application scenarios, the requirements on the electrostatic discharge (ESD) capability of the LDMOS are high.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a UHV LDMOS device in the prior art. The body structure of the UHV LDMOS is shown disposed in a high voltage N-type deep well 10 ' (HV Nwell) on the left side of the device, and is shown as a symmetrical structure comprising two transistors, each transistor comprising a drain terminal 11 ', a source terminal 12 ', a gate terminal 13 ' and a body terminal 14 '. The right P-well 20 ' (Pwell) has a grounded gate NMOS structure (GGNMOS) therein, and its input terminal (i.e., drain 21 ') is connected to the source terminal 12 ' of the body for ESD protection of the source terminal. The simple circuit diagram is shown in fig. 2, when the source terminal 12' is inrush ESD current to groundESD energy is discharged through the GGNMOS; when the drain terminal 11 ' is inrush to ground, due to the parasitic capacitances Cgd and Cgs between the gate drain and the gate source, the potentials of the gate terminal 13 ' and the source terminal 11 ' are coupled up in 10ns of ESD rising edge pulse. When the potential of the source terminal 11 ' reaches the trigger voltage of the GGNMOS, hysteresis (parasitic NPN is opened), and a transient voltage difference is formed between the gate terminal 13 ' and the source terminal 12 ' of the UHV LDMOS at the moment, so that V is caused_GSIt will become momentarily larger (larger than Vth) and the UHV LDMOS is in an on state. At this time, the instantaneous turn-on caused by the ESD energy may cause the turn-on of the device to exhibit an uneven turn-on to cause a local damage of the device.

Therefore, there is a need for further solutions to the above problems.

Disclosure of Invention

The invention aims to provide a lateral double-diffusion transistor, which is used for overcoming the defect that in the prior art, when ESD is injected from a drain terminal, a device is opened unevenly so as to generate damage, and therefore the ESD prevention capability of the device is improved.

To achieve the above object, the present invention provides a lateral double diffused transistor comprising a substrate, a main device region provided on the substrate, and a sub device region provided at one side of the main device region,

the main device region comprises a first transistor, a second transistor and a first ESD device arranged between the first transistor and the second transistor;

the first transistor and the second transistor are provided with a commonly connected source end, a commonly connected drain end, a commonly connected grid end and a commonly connected body end;

the first ESD device comprises a cathode connected to the commonly-connected grid end and two anodes arranged on the left side and the right side of the cathode, and the two anodes are connected to the commonly-connected source end;

the auxiliary device region comprises a second ESD device, the input end of the second ESD device is connected with the common-connection grid end, and the output end of the second ESD device is grounded.

Preferably, the main device region includes a main device deep well region having a first conductivity type disposed on the substrate, the sub device region includes a sub device well region disposed on the substrate, and isolation is provided between the main device deep well region and the sub device well region.

Preferably, the first transistor, the second transistor and the first ESD device are respectively disposed on the main part deep well region, and an isolation well of the first conductivity type and an isolation located on the isolation well are disposed between the first transistor and the first ESD device and between the second transistor and the first ESD device.

Preferably, the first ESD device includes a well region of the second conductivity type formed in the main device deep well region, and the two anodes of the first ESD device include a heavily doped region of the second conductivity type formed in the well region and an anode conductive layer in ohmic contact with the heavily doped region of the second conductivity type; the cathode of the first ESD device is a heavily doped region with a first conduction type formed in the potential well region and a cathode conducting layer in ohmic contact with the heavily doped region with the first conduction type, and the two anodes and the cathode are respectively connected to the commonly connected source terminal and the commonly connected gate terminal through outgoing lines.

Preferably, a separation is provided between the heavily doped regions with the second conductivity type of the two positive electrodes and the heavily doped regions with the first conductivity type of the negative electrode.

Preferably, with the first ESD device as a reference, the body terminal, the source terminal, the gate terminal, and the drain terminal of the first transistor and the second transistor are sequentially and gradually away from the first ESD device, and a distance between the drain terminal of the first transistor and the drain terminal of the second transistor is close to a maximum span of the deep well region of the main device.

Preferably, isolation is provided between the body terminal, the source terminal, the gate terminal and the drain terminal of the first transistor and the second transistor.

Preferably, the isolation is shallow trench isolation or thick field oxide isolation.

Preferably, the second ESD device is a GGNMOS device.

Preferably, the drain terminal of the GGNMOS device forms the input terminal of the GGNMOS device, and the gate terminal, the source terminal and the body terminal of the GGNMOS device form the output terminal of the GGNMOS device.

Compared with the prior art, the invention has the beneficial effects that:

the invention is characterized in that a forward diode is arranged in a transverse double-diffusion transistor device and is connected between a source end and a grid end in series, and an input end of an external ESD device is connected to the grid end, so that when ESD current at a drain end surges, although the voltages of the grid end and the source end are also coupled and pulled high, when the external ESD device is started and decompressed, the grid-source voltage VGS between the grid end and the source end cannot be instantly increased due to the action of the diode, thereby avoiding non-uniform starting of the device caused by ESD energy, and improving the ESD prevention capability of the device.

And secondly, the first ESD device is arranged in the original device region, and the PN junction of the diode is formed by utilizing the original P-type well region, so that the anti-ESD capability of the UHV LDMOS device is improved on the premise that the whole volume of the UHV LDMOS device is not increased.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a UHV LDMOS device according to the prior art.

Fig. 2 is an equivalent circuit diagram of a conventional UHV LDMOS device.

Fig. 3 is a schematic diagram of a UHV LDMOS device of the present invention.

Fig. 4 is an equivalent circuit diagram of a UHV LDMOS device of the present invention.

Detailed Description

The present invention is described in detail below with reference to various embodiments, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should be able to make modifications and substitutions on the functions, methods, or structures of these embodiments without departing from the scope of the present invention.

As shown in fig. 3, an embodiment of the present invention provides a lateral double diffused transistor, which includes: a substrate 1, a main device region 10 provided on the substrate 1, and a sub device region 20 also provided on the substrate 1 and located on the side of the main device region 10. The auxiliary component area 20 is shown to the right of the main component area 10, but in other embodiments, the auxiliary component area 20 may be located to the left of the main component area 10.

The main device region 10 includes a main device deep well region 11 having a first conductivity type disposed on the substrate 1, and a first transistor 110 and a second transistor 120 formed in the main device deep well region 11, the first transistor 110 and the second transistor 120 being lateral diffusion type MOS devices (LDMOS) including

drain terminals

111, 121, source terminals 112, 122, gate terminals 113, 123, and body terminals 114, 124, respectively.

In an embodiment of the present invention, the substrate 1 may be a P-type substrate 1, and the main deep well region 11 is doped with impurities of a certain conductivity type, so that the main deep well region 11 has certain electrical properties, the doping type may be determined according to the types of two LDMOS devices in the main region, for example, when the LDMOS is an N-type LDMOS, the doping type of the main deep well region 11 is an N-type doping, and when the LDMOS is a P-type LDMOS, the doping type of the main deep well region 11 is a P-type doping. Further, the main deep well region 11 is usually formed by a lightly doping process, so that the main deep well region 11 is a lightly doped high resistance layer of a certain conductivity type.

In fig. 3, an N-type LDMOS device is taken as an example, and referring to fig. 3 again, the main deep well 11 is a lightly doped N-type well, and the first transistor 110 and the second transistor 120 are N-type LDMOS devices. In the N-type main device deep well region 11, a P-type doped region 12 is formed, the

drain terminals

111 and 121 include a drain terminal well region Nwell formed in the main device deep well region 11 and having N-type doping, an N + region formed on Nwell, and a drain terminal electrode formed on the N + region, and the two

drain terminals

111 and 121 are connected together by a lead. The source terminals 112, 122 include an N + region formed on the P-type doped region 12, and a source terminal electrode formed on the N + region, and the two source terminals 112, 122 are connected in common by a wire. The gate terminals 113 and 123 are respectively arranged between the corresponding drain terminal and the source terminal and used for regulating and controlling the opening or the closing of a channel between the source terminal and the drain terminal by applying voltage, and the two gate terminals 113 and 123 are connected in common through a lead. Body terminals 114,124 are provided on P-doped region 12 along with source terminals 112,122, the two body terminals 114,124 also being commonly connected by wire bonds. Furthermore, isolation is provided between each body terminal 114, 124, source terminal 112, 122, gate terminal 113, 123 and drain terminal 111, 121 of the first transistor 110 and the second transistor 120, and the isolation is shallow trench isolation or thick field oxide isolation.

In the present invention, a first ESD device 130 is further disposed between the first transistor 110 and the second transistor 120, the first ESD device 130 includes a cathode 131 connected to the gate terminals 113 and 123, and two anodes 132 and 133 disposed on the left and right sides of the cathode 131, and the two anodes 132 and 133 are connected to the source terminals 112 and 122. As shown in the figure, the first ESD device 130 is disposed in the P-type doped region 12, the cathode 131 is a heavily doped N + region, and the two anodes 132 and 133 are heavily doped P + regions, so that the first ESD device 130 corresponds to a pair of parallel diodes disposed between the source terminals 112 and 122 and the gate terminals 113 and 123, as shown in fig. 4. Isolation is arranged between the P + heavily doped regions of the two anodes 132 and 133 and the N + heavily doped region of the cathode 131, and the isolation is shallow trench isolation or thick field oxide isolation. Because the first ESD device 130 is disposed in the original P-type doped region 12, and is isolated from the two transistors by the N-type well region for isolation, no additional region is used, so that the change of the overall size of the device is avoided, and the improvement of the ESD capability of the UHV LDMOS device of the present invention can be realized without increasing the size.

Preferably, an N-type isolation well and an isolation located on the N-type isolation well are disposed between the first transistor 110 and the first ESD device 130, and between the second transistor 120 and the first ESD device 130, where the isolation is a shallow trench isolation or a thick field oxide isolation, so as to prevent the conductive majority molecules from drifting into the device to cause leakage.

Preferably, referring to the first ESD device 130, the body terminals 114, 124, the source terminals 112, 122, the gate terminals 113, 123 and the

drain terminals

111, 121 of the first transistor 110 and the second transistor 120 are sequentially and gradually disposed away from the first ESD device 130, and the distance between the drain terminal 111 of the first transistor 110 and the drain terminal 121 of the second transistor 120 is close to the maximum span of the main device deep well region 11.

The sub-element region 20 includes a P-type sub-element well region 21 provided on the substrate 1, and isolation is provided between the sub-element well region 21 and the main-element deep well region 11. A second ESD device 210 is disposed on the sub-device well region 21, the second ESD device 210 is preferably implemented as a GGNMOS device, as shown in the figure, a drain terminal of the GGNMOS device constitutes an input terminal 211 of the GGNMOS device and is connected to gate terminals 113 and 123 commonly connected to two transistors in the main device region 10, and a gate terminal, a source terminal and a body terminal of the GGNMOS device serve as an output terminal and are grounded 212. It should be understood that the connection manner of the second ESD device is not limited to the above-described embodiment, and it may be directly or indirectly connected between the source terminal of the main device region 10 and the ground.

Referring to fig. 4, fig. 4 is an equivalent circuit diagram of the UHV LDMOS device of the present invention. As shown, when ESD current is injected into the

drain terminals

111 and 121, the potentials of the gate terminal and the source terminal are coupled up in the ESD rising edge pulse of 10ns due to the parasitic capacitances Cgd and Cgs between the gate and the drain and between the gate and the source. When the potential of the grid end reaches the trigger voltage of the GGNMOS, hysteresis (parasitic NPN is turned on) occurs, and at the moment, due to the existence of the diode between the grid end and the source end, VGS of the UHV LDMOS cannot be suddenly enlarged, and the UHV LDMOS is still in a closed state. At this time, the ESD energy is discharged through the parasitic NPN inside the UHV LDMOS device, so the device is not easily damaged.

In summary, the diode connected between the gate terminal and the source terminal is arranged in the two LDMOS devices to serve as the ESD device, and when ESD current surges from the drain terminal of the UHV LDMOS, the ESD device can prevent the voltage between the gate and the source from changing instantaneously due to parasitic capacitance, so that the device can be prevented from being turned on unevenly, and the ESD resistance of the device is improved.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A lateral double diffused transistor comprising a substrate, a main device region provided on the substrate, and an auxiliary device region provided on one side of the main device region,

the first ESD device comprises a cathode connected to the commonly connected grid end and two anodes arranged on the left side and the right side of the cathode, and the two anodes are connected to the commonly connected source end;

2. The lateral double diffused transistor of claim 1 wherein: the main component region comprises a main component deep well region which is arranged on the substrate and has a first conduction type, the auxiliary component region comprises an auxiliary component well region arranged on the substrate, and isolation is arranged between the main component deep well region and the auxiliary component well region.

3. The lateral double diffused transistor of claim 2 wherein: the first transistor, the second transistor and the first ESD device are respectively arranged on the main part deep well region, and an isolation well of a first conduction type and isolation positioned on the isolation well are arranged between the first transistor and the first ESD device and between the second transistor and the first ESD device.

4. The lateral double diffused transistor of claim 3 wherein: the first ESD device comprises a well region with a second conductive type formed in the main part deep well region, and two anodes of the first ESD device comprise a heavily doped region with the second conductive type formed in the well region and an anode conductive layer in ohmic contact with the heavily doped region with the second conductive type; the cathode of the first ESD device is a heavily doped region with a first conduction type formed in the potential well region and a cathode conducting layer in ohmic contact with the heavily doped region with the first conduction type, and the two anodes and the cathode are respectively connected to the commonly connected source terminal and the commonly connected gate terminal through outgoing lines.

5. The lateral double diffused transistor of claim 4 wherein: and isolation is arranged between the heavily doped regions with the second conductivity type of the two anodes and the heavily doped regions with the first conductivity type of the cathode.

6. The lateral double diffused transistor of claim 2 wherein: and taking the first ESD device as a reference, the body end, the source end, the grid end and the drain end of the first transistor and the second transistor are sequentially and gradually far away from the first ESD device, and the distance between the drain end of the first transistor and the drain end of the second transistor is close to the maximum span of the deep well region of the main part.

7. The lateral double diffused transistor of claim 6 wherein: and isolation is arranged between the body end, the source end, the grid end and the drain end of the first transistor and the second transistor.

8. The lateral double diffused transistor of any one of claims 2, 3, 5 or 7 wherein: the isolation is shallow trench isolation or thick field oxide isolation.

9. The lateral double diffused transistor of claim 1, wherein the second ESD device is a GGNMOS device.

10. The ldmos transistor set forth in claim 9 wherein the drain terminal of said GGNMOS device forms the input terminal of the GGNMOS device and the gate, source and body terminals of said GGNMOS device form the output terminal of the GGNMOS device.