CN111129002B - Electrostatic protection circuit - Google Patents

Electrostatic protection circuit Download PDF

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Publication number
CN111129002B
CN111129002B CN201911256096.7A CN201911256096A CN111129002B CN 111129002 B CN111129002 B CN 111129002B CN 201911256096 A CN201911256096 A CN 201911256096A CN 111129002 B CN111129002 B CN 111129002B
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region
diffusion region
trigger
protection circuit
voltage
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CN111129002A (en
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苏庆
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

Abstract

The invention discloses an electrostatic protection circuit, comprising: parasitic thyristors and trigger circuits; the first PLDMOS comprises a body region, a drift region, a grid structure, a first source end P + diffusion region, a first source end N + diffusion region and a first drain end P + diffusion region. Parasitic silicon controlled rectifiers are formed in the first PLDMOS by inserting a first drain terminal N + diffusion region; the grid structure, the first source end N + diffusion region and the first source end P + diffusion region are connected together to form an anode, and the anode is connected with an electrostatic end; the first drain end N + diffusion region is grounded to form a cathode; the first drain terminal P + diffusion region is used as a trigger electrode, and a first resistor is connected between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region; the trigger circuit is connected between the anode and the trigger electrode; when no static electricity exists, the trigger circuit is closed; when static electricity exists, the trigger circuit is conducted and triggers the parasitic silicon controlled rectifier to be conducted. The invention can adjust the trigger voltage of the controllable silicon of the circuit, thereby effectively protecting the protected internal high-voltage device.

Description

Electrostatic protection circuit
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an electrostatic protection circuit.
Background
As shown in fig. 1, it is an applied circuit diagram of the electrostatic protection circuit; the electrostatic protection circuit 102 is disposed between the input/output pad 101 and the ground, and when static electricity occurs in the input/output pad 101, the electrostatic protection circuit 102 is triggered and discharges the static electricity, thereby protecting the internal circuit 103.
FIG. 2 is a schematic cross-sectional view of a conventional ESD protection circuit; the circuit shown in fig. 2 adopts a high-voltage PLDMOS structure, a body region 202 composed of a high-voltage N well and a drift region 203 composed of a high-voltage P well are formed on a P-type semiconductor substrate such as a silicon substrate 201, and a gate dielectric layer such as a gate oxide layer 204 and a polysilicon gate 205 covers the surface of the body region 202 and extends to the surface of the drift region 203. A source region 206 composed of a P + region formed in the body region 202 and a first side of the polysilicon gate 205 are self-aligned, a P + region formed in the body region 202 is composed of a body region lead-out region 209, and a field oxide layer 210b is isolated between the source region 206 and the body region lead-out region 209. A drain P + diffusion region 207 composed of a P + region and a drain N + diffusion region 208 composed of an N + region are formed in the drift region 203, and the drain P + diffusion region 207 and the polysilicon gate 205 are spaced apart by a certain distance and are isolated by a field oxide layer 210 a. The source region 206, the body lead-out region 209 and the polysilicon gate 205 are all connected to a static terminal, the resistor R101 is connected between the polysilicon gate 205 and the static terminal, and the drain terminal N + diffusion region 208 is connected to the ground GND.
In the existing method, a high-voltage Silicon Controlled Rectifier (SCR) structure composed of a high-voltage PLDMOS shown in fig. 2 is usually an external structure, but the general SCR structure itself does not have the capability of adjusting trigger voltage, and sometimes it is impossible to effectively protect an internal high-voltage device to be protected.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an electrostatic protection circuit, which can adjust the trigger voltage of the controllable silicon of the circuit, thereby effectively protecting the protected internal high-voltage device.
In order to solve the above technical problem, the present invention provides an electrostatic protection circuit, including: parasitic thyristors and trigger circuits.
The parasitic silicon controlled rectifier is a parasitic structure of the first PLDMOS.
The first PLDMOS comprises an N-type lightly doped body region, a P-type lightly doped drift region and a grid structure.
And a first source end P + diffusion region consisting of a P + region and a first source end N + diffusion region consisting of an N + region are formed in the body region.
A first drain-end P + diffusion region composed of a P + region is formed in the drift region.
And a first drain end N + diffusion region consisting of an N + region is also formed in the drift region, and the parasitic controlled silicon is formed by inserting the first drain end N + diffusion region.
The grid structure, the first source end N + diffusion region and the first source end P + diffusion region are connected together to form an anode, and the anode is connected with an electrostatic end.
And the first drain terminal N + diffusion region is grounded to form a cathode.
The first drain terminal P + diffusion region is used as a trigger electrode, and a first resistor is connected between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region.
The trigger circuit is connected between the anode of the parasitic thyristor and the trigger electrode.
When the static end is free of static electricity, the trigger circuit is closed; when the static end has static electricity, the trigger circuit is conducted and forms trigger current from the static end to the trigger electrode, so that the parasitic silicon controlled rectifier is conducted.
In a further refinement, the trigger circuit includes a second PLDMOS, a second resistor and a first capacitor.
And the source electrode of the second PLDMOS is connected with the electrostatic end, and the drain electrode of the second PLDMOS is connected with the trigger electrode.
The first end of the second resistor is connected with the electrostatic end, the second end of the second resistor is connected with the grid electrode of the second PLDMOS and the first end of the first capacitor, and the second end of the first capacitor is connected with the trigger electrode.
In a further improvement, the second PLDMOS is a high voltage device capable of withstanding electrostatic voltages.
In a further improvement, the first capacitor is a high voltage device capable of withstanding an electrostatic voltage.
In a further improvement, the second resistor is a polysilicon resistor or a doped diffused resistor.
In a further improvement, the trigger circuit forms an adjustable structure of trigger voltage for enabling the parasitic thyristor to be conducted.
In a further improvement, the adjustable structure of the trigger voltage for the conduction of the parasitic thyristor comprises the first capacitor, and the larger the first capacitor is, the smaller the trigger voltage is.
In a further improvement, the adjustable structure of the trigger voltage for the conduction of the parasitic thyristor comprises the second resistor, and the larger the second resistor is, the smaller the trigger voltage is.
In a further improvement, the adjustable structure of the trigger voltage for the conduction of the parasitic thyristor comprises an effective channel width of the second PLDMOS, and the smaller the effective channel width of the second PLDMOS, the smaller the trigger voltage.
In a further improvement, the first PLDMOS is a high voltage device capable of withstanding electrostatic voltages.
In a further improvement, the body region is composed of a high-voltage N well, the drift region is composed of a high-voltage P well, the high-voltage N well and the high-voltage P well are both formed in a P-type semiconductor substrate, and the body region is laterally contacted with the drift region.
In a further improvement, a first field oxide is formed on the surface of the drift region between the first drain P + diffusion region and the body region, a distance is provided between a first side surface of the first field oxide and the body region, and a second side surface of the first field oxide is in contact with the first drain P + diffusion region.
And second field oxygen is formed between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region.
In a further improvement, the gate structure overlies the body surface and extends laterally to the surface of the first field oxide.
In a further improvement, the first source P + diffusion region is self-aligned to the first side of the gate structure, and a third field oxide is isolated between the first source P + diffusion region and the first source N + diffusion region.
The gate structure is further improved by superposing a gate dielectric layer and a polysilicon gate.
The first resistor is a polysilicon resistor or a doped diffusion resistor.
The SCR of the electrostatic protection circuit is directly formed by inserting the high-voltage P-type LDMOS, namely the first PLDMOS into the first drain terminal N + diffusion region and then parasitizing the high-voltage P-type LDMOS, the SCR does not need to be externally connected, the SCR is connected with the trigger circuit, the trigger circuit can adjust the trigger voltage of the SCR, and finally the trigger voltage of the controllable silicon of the circuit can be adjusted, so that the protected internal high-voltage device can be effectively protected.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a circuit diagram of an application of an electrostatic protection circuit;
FIG. 2 is a schematic cross-sectional view of a conventional ESD protection circuit;
FIG. 3 is a schematic cross-sectional diagram of an ESD protection circuit according to an embodiment of the present invention;
fig. 4 is an equivalent circuit of the electrostatic protection circuit according to the embodiment of the present invention.
Detailed Description
Fig. 3 is a schematic cross-sectional view of an electrostatic protection circuit according to an embodiment of the invention; the electrostatic protection circuit of the embodiment of the invention comprises: parasitic thyristors 302 and a trigger circuit 304.
The parasitic thyristor 302 is a parasitic structure of the first PLDMOS 301.
The first PLDMOS301 includes an N-type lightly doped body region 2, a P-type lightly doped drift region 3, and a gate structure.
A first source P + diffusion region 6 composed of a P + region and a first source N + diffusion region 9 composed of an N + region are formed in the body region 2.
A first drain-side P + diffusion region 7 composed of a P + region is formed in the drift region 3.
A first drain terminal N + diffusion region 8 composed of an N + region is also formed in the drift region 3, and the parasitic thyristor 302 is formed by inserting the first drain terminal N + diffusion region 8.
The gate structure, the first source end N + diffusion region 9 and the first source end P + diffusion region 6 are connected together to form an anode, and the anode is connected to an electrostatic end.
The first drain terminal N + diffusion region 8 is grounded to form a cathode.
The first drain P + diffusion region 7 serves as a trigger electrode, and a first resistor R1 is connected between the first drain P + diffusion region 7 and the first drain N + diffusion region 8.
The trigger circuit 304 is connected between the anode of the parasitic thyristor 302 and the trigger electrode.
When the static end is free of static electricity, the trigger circuit 304 is turned off; when the electrostatic end has static electricity, the trigger circuit 304 is turned on and forms a trigger current from the electrostatic end to the trigger electrode, so that the parasitic thyristor 302 is turned on.
The trigger circuit 304 includes a second PLDMOS303, a second resistor R2 and a first capacitor C1.
The source electrode of the second PLDMOS303 is connected with the electrostatic terminal, and the drain electrode is connected with the trigger electrode.
A first terminal of the second resistor R2 is connected to the electrostatic terminal, a second terminal of the second resistor R2 is connected to the gate of the second PLDMOS303 and a first terminal of the first capacitor C1, and a second terminal of the first capacitor C1 is connected to the trigger electrode.
The second PLDMOS303 is a high voltage device capable of withstanding electrostatic voltages.
The first capacitor C1 is a high-voltage device capable of withstanding electrostatic voltages.
The second resistor R2 is a polysilicon resistor or a doped diffused resistor.
The trigger circuit 304 forms an adjustable structure for the trigger voltage that turns on the parasitic thyristor 302.
The adjustable structure of the trigger voltage of the parasitic thyristor 302 comprises the first capacitor C1, and the larger the first capacitor C1 is, the smaller the trigger voltage is.
The adjustable structure of the trigger voltage of the parasitic thyristor 302 comprises the second resistor R2, and the larger the second resistor R2 is, the smaller the trigger voltage is.
The adjustable structure of the trigger voltage for the parasitic thyristor 302 to turn on comprises the effective channel width of the second PLDMOS303, and the smaller the effective channel width of the second PLDMOS303, the smaller the trigger voltage.
The first PLDMOS301 is a high voltage device capable of withstanding electrostatic voltages.
The body region 2 is composed of a high-voltage N well, the drift region 3 is composed of a high-voltage P well, the high-voltage N well and the high-voltage P well are both formed in a P-type semiconductor substrate, and the body region 2 is in lateral contact with the drift region 3.
The first field oxide 10a is formed on the surface of the drift region 3 between the first drain P + diffusion region 7 and the body region 2, a first side surface of the first field oxide 10a is spaced apart from the body region 2, and a second side surface of the first field oxide 10a is in contact with the first drain P + diffusion region 7.
A second field oxide 10b is formed between the first drain P + diffusion region 7 and the first drain N + diffusion region 8. A field oxide 10d is further formed outside the first drain-side N + diffusion region 8.
The gate structure covers the surface of the body region 2 and extends laterally to the surface of the first field oxide 10 a.
The first source end P + diffusion region 6 and the first side surface of the gate structure are self-aligned, and a third field oxide 10c is isolated between the first source end P + diffusion region 6 and the first source end N + diffusion region 9.
The grid structure is formed by superposing a grid dielectric layer 4 and a polysilicon grid 5.
The first resistor R1 is a polysilicon resistor or a doped diffused resistor.
As shown in fig. 4, it is an equivalent circuit of the electrostatic protection circuit according to the embodiment of the present invention; the PNP device 305 is composed of the first source terminal P + diffusion region 6, the body region 2, the drift region 3, and the first drain terminal P + diffusion region 7. The NPN device 304 is composed of the first source-side N + diffusion region 9, the body region 2, the drift region 3, and the first drain-side N + diffusion region 8.
The resistance Rnw is a parasitic resistance of the body region 2 between the first source terminal P + diffusion region 6 and the drift region 3.
The resistor R1a is a parallel resistance formed by the parasitic resistance of the drift region 3 between the body region 2 and the first drain-side N + diffusion region 8 and the resistor R1.
When static electricity occurs, the base voltage Vbn of the NPN device 304 rises to turn on the NPN device 304, and after the NPN device 304 is turned on, the base voltage Vbp of the PNP device 305 falls to turn on the PNP device 305, and finally, the conduction of the parasitic thyristor 302 is realized.
The SCR of the electrostatic protection circuit in the embodiment of the invention is formed by inserting a high-voltage P-type LDMOS (i.e. a first PLDMOS 301) into a first drain terminal N + diffusion region 8 and then parasitizing the high-voltage P-type LDMOS without external connection, and the SCR is connected with a trigger circuit 304, the trigger circuit 304 can realize the regulation of the trigger voltage of the SCR, and finally the trigger voltage of the controllable silicon of the circuit can be regulated, so that an internal high-voltage device to be protected can be effectively protected.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (14)

1. An electrostatic protection circuit, comprising: parasitic thyristors and trigger circuits;
the parasitic silicon controlled rectifier is a parasitic structure of the first PLDMOS;
the first PLDMOS comprises an N-type lightly doped body region, a P-type lightly doped drift region and a grid structure;
a first source end P + diffusion region consisting of a P + region and a first source end N + diffusion region consisting of an N + region are formed in the body region;
a first drain terminal P + diffusion region composed of a P + region is formed in the drift region;
a first drain end N + diffusion region consisting of an N + region is also formed in the drift region, and the parasitic controlled silicon is formed by inserting the first drain end N + diffusion region;
the grid structure, the first source end N + diffusion region and the first source end P + diffusion region are connected together to form an anode, and the anode is connected with an electrostatic end;
the first drain end N + diffusion region is grounded to form a cathode;
the first drain terminal P + diffusion region is used as a trigger electrode, and a first resistor is connected between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region;
the trigger circuit is connected between the anode of the parasitic thyristor and the trigger electrode;
the trigger circuit comprises a second PLDMOS, a second resistor and a first capacitor;
the source electrode of the second PLDMOS is connected with the electrostatic end, and the drain electrode of the second PLDMOS is connected with the trigger electrode;
the first end of the second resistor is connected with the electrostatic end, the second end of the second resistor is connected with the grid electrode of the second PLDMOS and the first end of the first capacitor, and the second end of the first capacitor is connected with the trigger electrode.
2. The electrostatic protection circuit of claim 1, wherein: the second PLDMOS is a high-voltage device capable of withstanding electrostatic voltages.
3. The electrostatic protection circuit of claim 1, wherein: the first capacitor is a high-voltage device capable of withstanding electrostatic voltages.
4. The electrostatic protection circuit of claim 1, wherein: the second resistor is a polysilicon resistor or a doped diffusion resistor.
5. The electrostatic protection circuit of claim 1, wherein: the trigger circuit forms an adjustable structure of trigger voltage for conducting the parasitic silicon controlled rectifier.
6. The electrostatic protection circuit of claim 5, wherein: the adjustable structure of the trigger voltage conducted by the parasitic silicon controlled rectifier comprises the first capacitor, and the larger the first capacitor is, the smaller the trigger voltage is.
7. The electrostatic protection circuit of claim 5, wherein: the adjustable structure of the trigger voltage conducted by the parasitic silicon controlled rectifier comprises the second resistor, and the larger the second resistor is, the smaller the trigger voltage is.
8. The electrostatic protection circuit of claim 5, wherein: the adjustable structure of the trigger voltage for the conduction of the parasitic silicon controlled rectifier comprises the effective channel width of the second PLDMOS, and the smaller the effective channel width of the second PLDMOS is, the smaller the trigger voltage is.
9. The electrostatic protection circuit of claim 1, wherein: the first PLDMOS is a high-voltage device capable of withstanding electrostatic voltages.
10. The electrostatic protection circuit of claim 9, wherein: the body region is composed of a high-voltage N well, the drift region is composed of a high-voltage P well, the high-voltage N well and the high-voltage P well are both formed in the P-type semiconductor substrate, and the body region is in lateral contact with the drift region.
11. The electrostatic protection circuit of claim 10, wherein: the first field oxygen is formed on the surface of the drift region between the first drain terminal P + diffusion region and the body region, a distance is reserved between the first side surface of the first field oxygen and the body region, and the second side surface of the first field oxygen is in contact with the first drain terminal P + diffusion region;
and a second field oxide is formed between the first drain terminal P + diffusion region and the first drain terminal N + diffusion region.
12. The electrostatic protection circuit of claim 11, wherein: the gate structure covers the body region surface and extends laterally to the surface of the first field oxide.
13. The electrostatic protection circuit of claim 11, wherein: the first source end P + diffusion region and the first side face of the grid structure are self-aligned, and third field oxygen is isolated between the first source end P + diffusion region and the first source end N + diffusion region.
14. The electrostatic protection circuit of claim 11, wherein: the grid structure is formed by superposing a grid dielectric layer and a polysilicon grid;
the first resistor is a polysilicon resistor or a doped diffusion resistor.
CN201911256096.7A 2019-12-10 2019-12-10 Electrostatic protection circuit Active CN111129002B (en)

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Publication number Priority date Publication date Assignee Title
CN112736124B (en) * 2020-12-28 2023-10-27 矽力杰半导体技术(杭州)有限公司 ESD protection device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148438A (en) * 2018-07-26 2019-01-04 上海华虹宏力半导体制造有限公司 High-voltage electrostatic protection device and equivalent circuit
CN110190052A (en) * 2019-06-04 2019-08-30 电子科技大学 A kind of compact compound SCR device in three ends for full chip ESD protection

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148438A (en) * 2018-07-26 2019-01-04 上海华虹宏力半导体制造有限公司 High-voltage electrostatic protection device and equivalent circuit
CN110190052A (en) * 2019-06-04 2019-08-30 电子科技大学 A kind of compact compound SCR device in three ends for full chip ESD protection

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