CN211428176U - Semiconductor device with a plurality of transistors - Google Patents

Abstract

The application discloses a semiconductor device, this semiconductor device includes: a substrate; a body region located on a surface of a substrate; the surface of the body region extends into the body region; the gate stack is positioned on the surface of the body region; and the conductive channel comprises a groove which penetrates through the body region and is in contact with the substrate and a conductive material filled in the groove, the conductive channel is separated from the doped region, a channel is formed between the doped region and the conductive channel, and the substrate is communicated with the doped region through the conductive channel and the channel. The semiconductor device forms a conductive channel by filling the conductive material in the groove, and the groove is not used for manufacturing a groove gate any more, so that the etching quality requirement on the groove is reduced, the etching difficulty is reduced, and the groove gate is replaced by the gate lamination formed on the surface of the body region, so that the threshold voltage of the device is more stable.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to a semiconductor device makes the field, and more specifically relates to a semiconductor device.

Background

A Trench-type VDMOS (vertical double-diffused metal oxide semiconductor field effect transistor) forms a gate by growing a gate dielectric layer on the sidewall of a Trench (Trench) and filling the Trench with a conductive material. The groove grid structure greatly improves the utilization efficiency of the plane area of the power device, so that larger device unit groove width and current density can be obtained in unit area, and the device can obtain larger current conduction capability. At present, the groove type VDMOS is widely applied to various fields of motor speed regulation, inverters, power supplies, electronic switches, sound equipment, automobile electric appliances and the like.

The trench-type VDMOS includes a U-shaped trench structure, and is therefore also called UMOS. Fig. 1 shows a schematic structural diagram of a UMOS device in the prior art. As shown in fig. 1, a typical UMOS device includes a substrate 10, an epitaxial layer 11, a body region 12, a U-shaped trench, a source region 15, a contact hole 16, and a channel 17. Wherein a gate dielectric layer 13 is formed on the sidewall of the U-shaped trench, and a conductive material serving as a gate conductor 14 is filled in the U-shaped trench.

In the conventional UMOS manufacturing process, due to the limitation of the etching technology, the outer profile and the side wall roughness of the U-shaped trench are not easy to control, and after the U-shaped trench is formed by dry etching, a series of complex processes such as Rounding Etch, sacrificial oxidation, acid washing and the like are required, so that the control difficulty of the outer profile and the side wall roughness of the U-shaped trench is further increased. In addition, since the gate dielectric layer 13 is grown on the sidewall of the U-shaped trench and is affected by the oxidation atmosphere, the sidewall roughness, and the crystal orientation (atomic density), it is difficult to form a high quality gate dielectric layer 13 having a uniform thickness.

In addition, since the channel 17 of the UMOS device extends longitudinally in the body region 12 (the thickness direction of the body region 12), it is easily affected by the longitudinal impurity concentration gradient in the body region 12. Therefore, the doping concentration of the channel 17 is poor in consistency, so that the channel resistance Rch and the threshold voltage Vt are unstable, the on resistance of the device is difficult to control, and great difficulty is added to process development and device manufacturing.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides a semiconductor device having lower manufacturing difficulty and higher uniformity.

The embodiment of the utility model provides a semiconductor device includes: a substrate; a body region on a surface of the substrate; a doped region extending from the body region surface into the body region; the gate stack comprises a gate dielectric layer and a gate conductor layer, the gate dielectric layer covers the surface of the body region, and the gate conductor layer is positioned on the gate dielectric layer; and the conductive channel comprises a groove which penetrates through the body region and is in contact with the substrate and a conductive material filled in the groove, and the conductive channel is separated from the doped region, wherein the body region is of a first doping type, the substrate, the conductive channel and the doped region are of a second doping type, the first doping type is opposite to the second doping type, the grid conductor layer receives a control voltage, and the substrate is conducted with the doped region through a channel among the conductive channel, the doped region and the conductive channel.

Preferably, the channel is proximate to a surface of the body region.

Preferably, the gate conductor corresponds at least to the body region between the doped region and the conductive channel.

Preferably, the method further comprises the following steps: the interlayer dielectric layer covers the gate dielectric layer and the gate conductor layer; the first conductive plug penetrates through the interlayer dielectric layer and the gate dielectric layer and is respectively contacted with the doped region and the body region; the second conductive plug penetrates through the interlayer dielectric layer and is in contact with the grid conductor layer; the source electrode is positioned on the surface of the interlayer dielectric layer and is in contact with the first conductive plug; and the gate electrode is positioned on the surface of the interlayer dielectric layer and is in contact with the second conductive plug.

Preferably, the device further comprises a drain electrode on the other surface of the substrate.

Preferably, the conductive channel extends from the body region surface to the surface of the substrate or into the substrate.

Preferably, on a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are arranged in the body region in an array, each doped region is surrounded by the conductive channel, and a channel between each doped region and the conductive channel is in a shape of a Chinese character 'hui'; or on a cross section perpendicular to the thickness direction of the body region, the plurality of doped regions are rectangular and are arranged in the body region in parallel along the long side direction of the rectangle, at least one conductive channel is arranged between every two adjacent doped regions, and a channel between each doped region and the conductive channel is rectangular.

Preferably, a plurality of the doped regions are connected to the same source electrode.

Preferably, the conductive material comprises polysilicon.

Preferably, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

Compare in traditional UMOS device, through at the technical scheme that slot lateral wall growth gate dielectric layer and filling conducting material and form the trench gate structure, the embodiment of the utility model provides a semiconductor device has following advantage:

1. the trench is formed in the body region, the conductive material is filled in the trench to form the conductive channel, and the gate dielectric layer is formed on the surface of the body region, so that the trench gate structure in the prior art is replaced, and the adverse effect of the roughness of the outer contour and the side wall of the trench on the performance parameters of the device is eliminated, thereby greatly reducing the requirements on the etching quality of the trench, reducing the processing and manufacturing difficulty of the device, and being beneficial to improving the uniformity of the performance of the device.

2. Because the gate dielectric layer is formed on the surface of the body region, the thickness uniformity and quality of the gate dielectric layer are better controlled, so that the gate dielectric layer with high quality is easier to obtain, and the threshold voltage of the device is more stable.

3. Because the gate stack is of a planar gate structure, the channel is adjacent to the gate dielectric layer and is close to the surface of the body region, so that the doping concentration of the channel is more uniform and is easier to control, the influence of the longitudinal concentration gradient of impurities in the doped concentrated receptor body region of the channel is avoided, the channel resistance Rch is stable and easy to control, and the threshold voltage Vt of the device is more stable.

4. By forming the conductive channel penetrating through the body region and forming the gate stack on the surface of the body region, after the gate stack receives the control voltage, a channel is formed between the doped region and the conductive channel, and the substrate is conducted with the doped region through the conductive channel and the channel, the on-resistance of the device is reduced, the on-resistance is easier to control, and the performance and the consistency of the device are further improved.

Drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings in the following description only relate to some embodiments of the present invention, and are not intended to limit the present invention.

Fig. 1 shows a schematic structural diagram of a UMOS device in the prior art.

Fig. 2a shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

Fig. 2b shows a schematic cross-sectional view of the semiconductor device in fig. 2 a.

Fig. 2c shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Fig. 3a to 3p show cross-sectional views of a method of manufacturing a semiconductor device at various stages according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions. If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

Fig. 2a shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. As shown in fig. 2a, the semiconductor device according to the embodiment of the present invention includes: substrate 101, body region 120, conductive via 130, gate stack 140, doped region 150, interlayer dielectric layer 160, first conductive plug 171, second conductive plug 172, source electrode 181, and gate electrode 182.

The body region 120 is located on a surface of the substrate 101 (in the semiconductor field, of two surfaces of the substrate 101, a surface for forming the epitaxial layer 110 is generally referred to as a front surface, and the other surface is referred to as a back surface). Conductive via 130 passes through body region 120 and contacts substrate 101, and the depth of conductive via 130 is no less than the junction depth of body region 120. In this embodiment, the conductive channel 130 extends from the surface of the body region 120 into the substrate 101. In some other embodiments, the conductive vias 130 may also be in contact with only the front surface of the substrate 101. The doped region 150 extends from the surface of the body region 120 into the body region 120, and the conductive via 130 and the doped region 150 are separated by the body region 120.

The body region 120 is of a first doping type and the substrate 101, the conductive channel 130 and the doped region 150 are of a second doping type, the first doping type being opposite to the second doping type. The second doping type is selected from one of P type doping and N type doping, and the first doping type is selected from the other of P type doping and N type doping.

In the present embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. In other embodiments, the first doping type is selected from N-type doping and the second doping type is selected from P-type doping.

The gate stack 140 specifically includes a gate dielectric layer 141 and a gate conductor layer 142, which are stacked, wherein the gate dielectric layer 141 covers the surface of the body region 120, and the gate conductor layer 142 is located on the gate dielectric layer 141. The gate conductive layer 142 is located above the conductive via 130 and extends along the gate dielectric layer 141 to both sides of the conductive via 130 to cover the body region 120 between the doped region 150 and the conductive via 130. The gate stack 140, and more specifically the gate conductor layer 142, receives the control voltage to form a channel 190 between the doped region 150 and the conductive via 130. Conduction is provided between the substrate 101 and the doped region 150 through the conductive via 130 and the channel 190. Wherein channel 190 is adjacent to gate dielectric layer 141 and is proximate to the surface of body region 120.

An interlayer dielectric layer (ILD)160 covers the gate dielectric layer 141 and the gate conductor layer 142. The first conductive plug 171 penetrates the interlayer dielectric layer 160 and the gate dielectric layer 141 while contacting the doped region 150 and the body region 120. I.e., the first conductive plug 171, passes through the interlayer dielectric layer 160, the gate dielectric layer 141, and the doped region 150, and contacts the body region 120 under the doped region 150. The second conductive plug 172 penetrates through the interlayer dielectric layer 160 and contacts the gate conductor layer 142. In this embodiment, the second conductive plug 172 penetrates through the interlayer dielectric layer 160 and contacts the surface of the gate conductor layer 142 away from the body region 120; in other embodiments, the second conductive plug 172 penetrates through the interlayer dielectric layer 160 and into the gate conductor layer 142.

The source electrode 181 is located on the surface of the interlayer dielectric layer 160 and contacts the first conductive plug 171. The gate electrode 182 is located on the surface of the interlayer dielectric layer 160 and contacts the second conductive plug 172. Of course, there is no direct contact between source electrode 181 and gate electrode 182.

Fig. 2B shows a schematic cross-sectional view of the semiconductor device in fig. 2a, wherein a cross-sectional view corresponding to the source connection region S is taken in fig. 2a along the position indicated by the arrow a and a cross-sectional view corresponding to the gate connection region G is taken in fig. 2a along the position indicated by the arrow B.

As shown in fig. 2a and 2b, a plurality of doped regions 150 are arranged in an array in the body region 120 on a cross section perpendicular to the thickness direction of the body region 120, each doped region 150 being surrounded and surrounded by the conductive channel 130. Wherein the channel 190 between each doped region 150 and the conductive via 130 is in a zigzag shape to increase the current density. The plurality of doped regions 150 may be connected to the same source electrode 181 through the first conductive plug 171. The gate conductor layer 142 may be connected to the same gate electrode 182 through a plurality of second conductive plugs 172.

It should be noted that, in fig. 2b, there are 4 doped regions 150, and the doped regions are arranged in a 2 × 2 array. In the specific implementation process, the number of the doped regions 150 in each cell (cell) can reach hundreds of thousands or even millions, and the arrangement mode can be reasonably set according to the performance requirement of the product, which is not described herein again.

As shown in fig. 2c, in some other embodiments, in a cross section perpendicular to the thickness direction of the body region 120, the doped regions 150 are rectangular and arranged in parallel in the body region 120 along the long side direction of the rectangle, and at least one conductive via 130 is spaced between two adjacent doped regions 150. Wherein the channel 190 between each doped region 150 and the conductive via 130 is rectangular. Each of the doped regions 150 is connected to a plurality of first conductive plugs 171 which are uniformly arranged, and the plurality of doped regions 150 are connected to the same source electrode 181 through the first conductive plugs 171. The plurality of gate conductor layers 142 are connected to the same gate electrode 182 through the respective second conductive plugs 172.

In fig. 2c, there are 2 doped regions 150 in total and arranged in parallel. In the specific implementation process, the number of the doped regions 150 in each cell (cell) can reach hundreds of thousands or even millions, and the arrangement mode can be reasonably set according to the performance requirement of the product, which is not described herein again.

Fig. 3a to 3p show cross-sectional views of a method of manufacturing a semiconductor device at various stages according to an embodiment of the present invention. The method for manufacturing the semiconductor device of the present invention will be described in detail with reference to fig. 3a to 3 p.

In this embodiment, the body region 120 can be fabricated in two ways:

in one implementation, as shown in fig. 3a, an epitaxial layer 110 is formed on a surface of a substrate 101; as shown in fig. 3b, the epitaxial layer 110 is doped to form a body region 120 at the front side of the substrate 101. The present embodiment is not particularly limited to the formation processes of the epitaxial layer 110 and the body region 120, wherein the epitaxial layer 110 may adopt a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, and the like; the body region 120 may be formed by implanting dopant impurities into the epitaxial layer 110 and annealing to ensure that the junction depth of the body region 120 is the same as the thickness of the epitaxial layer 110.

The substrate 101 and the epitaxial layer 110 are doped with the same type, for example, both are doped with N type, and the doping concentration of the epitaxial layer 110 is less than that of the substrate 101. In the present embodiment, the implantation into the epitaxial layer 110 is performed by P-type doping, the doping impurity may be boron (B), for example, and the implantation dose is generally not greater than E14cm^-2An order of magnitude.

Alternatively, the step of forming the body region 120 by implanting P-type dopant impurities into the epitaxial layer 110 may also be provided before and after forming the gate dielectric layer 141. For example, after the gate dielectric layer 141 is formed, doping impurities are implanted into the epitaxial layer 110 to form a body region 120; for another example, after forming the conductive via 130, doping impurities are implanted into the epitaxial layer 110 to form the body region 120, and then the gate dielectric layer 141 is formed.

In another implementation, referring to fig. 3b, the body region 120 may also be directly obtained by performing an epitaxial growth process on the front surface of the substrate 110. Of course, the doping type of the substrate 101 is opposite to the doping type of the body region 120 (or epi). Such as N-type substrate P-type epitaxy. Of course, epitaxial wafers meeting this requirement are also directly commercially available.

Since the channel 190 will be formed in the body region 120 and near the surface of the body region 120 when the device is formed and turned on, the doping concentration of the channel region can be monitored by the implanted and annealed sheet resistance. In the embodiment of the present invention, no matter form district region 120 by doping impurities into epitaxial layer 110, or directly utilize epitaxial layer 110 to form district region 120, the vertical concentration gradient of doping impurities in district region 120 does not need to be considered, and the uniformity of doping impurities on the surface of district region 120 only needs to be controlled, thereby reducing the difficulty of doping process, and making channel resistance Rch and threshold voltage Vt after the device is turned on stable and easy to control.

Further, a mask 102 is formed on the surface of the body region 120, as shown in fig. 3 c.

In this step, for example, a non-metal dielectric layer is formed on the surface of the body region 120 by using a thin film growth process, and then the non-metal dielectric layer is patterned by using an etching process to form the mask 102 having a plurality of windows 103. In the present embodiment, the material of the mask 102 includes, but is not limited to, an insulating material such as silicon oxide, silicon nitride, etc.

Further, the body region 120 is anisotropically etched through the via 103 to form a plurality of trenches 104 through the body region 120, as shown in fig. 3 d.

In this step, the anisotropic etching is, for example, ion milling etching, plasma etching, reactive ion etching, laser ablation. By controlling the etching time and etching rate, the depth of the trench 104 is not less than the junction depth of the body region 120. In the present embodiment, the trench 104 may be a U-shaped trench in the current UMOS, and the bottom of the trench 104 passes through the body region 120 and extends into the substrate 101.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other settings on the depth of the trench 104 as needed, for example, the bottom of the trench 104 is located on the front surface of the substrate 101.

In the subsequent steps, the trench 104 needs to be filled with a conductive material to form a conductive channel, and the shape and the edge flatness of the trench 104 do not have a great influence on the quality of the device. Therefore, in the step of forming the trench 104, the inner surface of the trench 104 does not have to be perfectly flat intentionally, thereby reducing the difficulty of controlling the etching process.

Further, a polysilicon layer 105 is deposited on the surface of the mask 102 and in the trench 104, as shown in fig. 3 e.

In this step, the polysilicon layer 105 is formed, for example, by a CVD process, and the polysilicon layer 105 may be doped with a concentration of E18cm or more by thermal diffusion, post-ion implantation annealing, or the like^-3An order of magnitude of impurities. In the present embodiment, the polysilicon layer 105 is, for example, in-situ N-type doped with an impurity concentration of 1E19cm^-3Polysilicon layer 105 is deposited to a thickness of no less than 1000 angstroms.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art can flexibly adjust the parameters of the polysilicon layer 105 according to the filling effect of the trench 104.

Further, the polysilicon layer 105 is etched back, and the height of the surface of the polysilicon layer 105 after etching is not lower than the interface between the body region 120 and the mask 102, for example, in fig. 3f, the surface of the polysilicon layer 105 after etching is substantially equal to the surface of the body region 120; in other embodiments, the surface of polysilicon layer 105 after etching is slightly above the surface of body region 120 but not beyond the surface of mask 102.

Further, the mask 102 is removed, and the surface of the body region 120 is re-exposed, as shown in fig. 3g, wherein the polysilicon layer 105 in the trench 104 and the trench 104 together serve as a conductive channel 130, the outer contour of the conductive channel 130 is U-shaped, and the surface of the body region 120 extends into the substrate 101.

Further, a gate dielectric layer 141 is formed on the surface of the body region 120, as shown in fig. 3 h.

In this step, the gate dielectric layer 141 is formed, for example, using a thin film growth process. The material of the gate dielectric layer 141 includes, but is not limited to, silicon oxide, and the thickness is not less than 30 angstroms.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art can flexibly adjust the thickness of the gate dielectric layer 141 according to different requirements of the threshold voltage Vt of the device.

Further, a gate conductor layer 142 is formed on the surface of the gate dielectric layer 141, as shown in fig. 3 i.

In this step, a polysilicon layer is deposited on the surface of the gate dielectric layer 141 by, for example, a CVD process. Wherein the thickness of the polysilicon layer is not less than 1000 angstroms, the doping type of the polysilicon layer is N type, and the doping concentration is not less than 1E19cm^-3. And patterning the polysilicon layer by using photolithography and etching processes to form a gate conductor layer 142, wherein the gate dielectric layer 141 and the gate conductor layer 142 jointly form a gate stack 140.

In the present embodiment, the gate conductive layer 142 is located above the conductive via 130, and extends a predetermined length along the gate dielectric layer 141 to both sides of the conductive via 130, covering the channel 190 and the conductive via 130.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art may set the thickness and the doping concentration of the polysilicon layer as needed.

In some other embodiments, the material of the gate conductor layer 142 may also be a conductive material such as metal, metal oxide, etc.

Further, a doped region 150 is formed extending from the surface of body region 120 into body region 120, as shown in fig. 3 j.

In this step, a self-aligned implantation process is first used to implant N-type dopant impurities into the body region 120. The gate conductor layer 142 made of polysilicon serves as a mask layer. Then, annealing is performed to diffuse the dopant impurities from the surface of the body region 120 into the body region 120, thereby forming the doped region 150. In the present embodiment, the doped region 150 serves As a source region of the device, the N-type dopant impurity is arsenic (As), and the implantation dose is not less than E15cm^-2。

However, the embodiments of the present invention are not limited thereto, and those skilled in the art can make other settings on the doping impurity and the doping concentration of the doped region 150 as required, and reasonably adjust the annealing conditions according to actual needs.

Further, an interlayer dielectric layer 160 is formed to cover the gate dielectric layer 141 and the gate conductor layer 142, as shown in fig. 3 k.

In this step, for example, a thin film growth process is first used to deposit an insulating material, such as silicon oxide, silicon nitride, etc., on the surfaces of the gate dielectric layer 141 and the gate conductor layer 142. The insulating material is then planarized, for example, by Chemical Mechanical Polishing (CMP), to form an interlayer dielectric layer 160. In the present embodiment, the thickness of the planarized interlayer dielectric layer 160 is not less than 1000 angstroms.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings on the material and thickness of the interlayer dielectric layer 160 as required.

Further, an anisotropic etching is used to form the first contact hole 106 penetrating through the interlayer dielectric layer 160, the gate dielectric layer 141 and the doped region 150, and form the second contact hole 107 penetrating through the interlayer dielectric layer 160, as shown in fig. 3 l.

In this step, the anisotropic etching is, for example, ion milling etching, plasma etching, reactive ion etching, laser ablation. By controlling the etch rate and etch time, the bottom of the first contact hole 106 is made to pass through the doped region 150 and enter the body region 120; also, by controlling the etching rate and the etching time, the bottom of the second contact hole 107 reaches into the gate conductor layer 142 or passes through the gate conductor layer 142. In forming the second contact hole 107, the gate dielectric layer 141 may serve as an etching stop layer, and the second contact hole 107 may also penetrate through the surface of the gate dielectric layer 141 to reach the middle of the gate dielectric layer 141.

Further, a first conductive plug 171 is formed through the interlayer dielectric layer 160, the gate dielectric layer 141 and the doped region 150, and a second conductive plug 172 is formed through the interlayer dielectric layer 160, as shown in fig. 3 m.

In this step, a metal material, such as titanium, titanium nitride, tungsten, or copper, is filled in the first contact hole 106 and the second contact hole 107, respectively, for example, by CVD or PVD processes. Wherein the bottom of the first conductive plug 171 extends through the doped region 150 into the body region 120 below the doped region 150. The bottom of the second conductive plug 172 reaches the gate conductor layer 142, and may also reach the surface or the middle of the gate dielectric layer 141 through the gate conductor layer 142.

Further, a source electrode 181 and a gate electrode 182 are respectively formed on the surface of the interlayer dielectric layer 160, wherein the source electrode 181 is in contact with the first conductive plug 171, and the gate electrode 182 is in contact with the second conductive plug 172, as shown in fig. 3 n.

In this step, for example, a PVD process is first used to deposit a metal layer on the surface of the interlayer dielectric layer 160, where the material of the metal layer is, for example, aluminum, copper, silver, aluminum-copper alloy, aluminum-silicon-copper alloy, and the like. An opening 108 is then formed in the metal layer using an etching process to separate the metal layer into a source electrode 181 and a gate electrode 182.

Preferably, a drain electrode (not shown) may be formed on the back surface of the substrate 101. Of course, before the drain electrode is formed on the back surface of the substrate 101, the back surface of the substrate 101 may be thinned according to actual requirements.

In some other embodiments, if the gate conductor layer 142 is formed of a metal material, after the step shown in fig. 3h is completed, the doped region 150 is formed in the body region 120, as shown in fig. 3 o. A metallic gate conductor layer 142 is then formed on the gate dielectric layer 141 as shown in figure 3 p. The subsequent steps refer to fig. 3k to fig. 3n, which are not described herein again.

A control voltage is applied to the gate electrode 182, the gate conductor layer 142 receives the control voltage, and a channel 190 is formed between the doped region 150 and the conductive via 130. The substrate 101 is in communication with the doped region 150 through the conductive via 130 and the channel 190. The current flows through the substrate 101, the longitudinal conductive via 130, the channel 190, the doped region 150, and the longitudinal first conductive plug 171 in sequence to reach the source electrode 181, as shown in fig. 2 a.

The method for manufacturing a semiconductor device according to the embodiment of the present invention is particularly suitable for manufacturing a low voltage (operating voltage is not greater than 100V) NMOS device. The manufacturing principle of the PMOS device is the same, and the doping types in the corresponding structures are directly switched. But the polysilicon is doped in different N-type and P-type modes. In-situ polycrystalline doping, i.e. growing N-type doped polysilicon, is mostly adopted for N-type doping. The P-type doping is limited by the processing means, and is generally achieved by depositing polysilicon, then implanting boron and annealing. In addition, the formation of the N-type polycrystalline silicon can also adopt a mode of phosphorus implantation and annealing, and the in-situ N-type polycrystalline deposition is a preferable scheme.

As shown in fig. 1, the on-resistance of the conventional UMOS device includes: a substrate resistance Rsub, an epitaxial resistance Repi, an accumulation region resistance Racc, a channel resistance Rch, a source resistance Rsc, and a via contact resistance Rcon. After the device is turned on, a vertically flowing current (in the direction of an arrow) needs to pass through the whole device, particularly, the current flows through a section of high-resistance region, namely the epitaxial layer 11, in the midway, and the resistance value of the epitaxial resistor Repi is very large, so that the device has very high on-resistance.

In contrast, according to the semiconductor device of the present invention, as shown in fig. 2a, by forming the conductive via 130 that passes through the body region 120 and contacts the substrate 101, the epitaxial resistor Repi originally connected in series in the conventional UMOS device is eliminated, thereby reducing the on-resistance of the entire device. The material of the conductive channel 130 is in-situ doped polysilicon, and the conductive channel 130 is only used as a low-resistance conductive path for leading current from the drain electrode on the back side of the substrate 101 to the front side, so that the functional characteristic that the current vertically flows between the two ends of the source electrode 181 and the drain electrode of the VDMOS is not changed, and the utilization efficiency of the plane area of the device is ensured. Since the gate stack 140 is formed on the surface of the body region 120, the trench gate structure in the prior art is replaced, thereby avoiding the problems that the profile of the U-shaped trench and the roughness of the sidewall affect the gate oxidation quality and the like.

Furthermore, since the gate dielectric layer 141 is only formed on the surface of the body region 120, the thickness uniformity and quality of the gate dielectric layer 141 are better controlled; in addition, the body region 120 is made of a semiconductor material with a single crystal orientation, so that the thickness uniformity and quality of the gate dielectric layer 141 can be better controlled, the threshold voltage Vt is more stable, and the resistance of the on-resistance is more easily controlled.

Furthermore, since the gate stack 140 is a planar gate structure, the channel 190 formed during the operation of the device is adjacent to the gate dielectric layer 141 and is close to the surface of the body region 120, so that the resistance of the channel 190 is more uniform and easy to control, the resistance of the channel 190 is prevented from being easily affected by the longitudinal concentration gradient of impurities in the body region 120, the channel resistance Rch is further stable and easy to control, and the on-resistance and the threshold voltage Vt of the device are more stable.

Further, when the polysilicon gate conductor layer is formed, compared with the conventional process, only one polysilicon deposition and lithography is added, but an automatic quasi-process can be adopted in the implantation step of the doped region 150, a lithography mask is saved, and the total lithography times are not significantly increased. In addition, all steps of the whole manufacturing process of the device can be completed by adopting the existing process technology, so that the manufacturing process of the device is very easy to integrate with the existing semiconductor process and is convenient for practical popularization.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present invention, and these alternatives and modifications are intended to fall within the scope of the present invention.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a body region on a surface of the substrate;

a doped region extending from the body region surface into the body region;

the gate stack comprises a gate dielectric layer and a gate conductor layer, the gate dielectric layer covers the surface of the body region, and the gate conductor layer is positioned on the gate dielectric layer; and

a conductive channel comprising a trench through the body region and in contact with the substrate and a conductive material filled within the trench, the conductive channel being separated from the doped region,

wherein the body region is of a first doping type, the substrate, the conductive channel and the doped region are of a second doping type, the first doping type being opposite to the second doping type,

the grid conductor layer receives control voltage, and the substrate is conducted with the doped region through the conductive channel and the channels between the doped region and the conductive channel.

2. The semiconductor device of claim 1, wherein the channel is proximate a surface of the body region.

3. A semiconductor device as claimed in claim 1 or 2, characterized in that the gate conductor corresponds at least to the body region between the doped region and the conductive channel.

4. The semiconductor device according to claim 1 or 2, further comprising:

the interlayer dielectric layer covers the gate dielectric layer and the gate conductor layer;

the first conductive plug penetrates through the interlayer dielectric layer and the gate dielectric layer and is respectively contacted with the doped region and the body region;

the second conductive plug penetrates through the interlayer dielectric layer and is in contact with the grid conductor layer;

the source electrode is positioned on the surface of the interlayer dielectric layer and is in contact with the first conductive plug; and

and the gate electrode is positioned on the surface of the interlayer dielectric layer and is in contact with the second conductive plug.

5. The semiconductor device according to claim 4, further comprising a drain electrode on the other surface of the substrate.

6. A semiconductor device according to claim 1 or 2, wherein the conductive channel extends from the body surface to the surface of the substrate or into the substrate.

7. The semiconductor device according to claim 4, wherein, in a cross section perpendicular to a thickness direction of the body region, a plurality of the doped regions are arranged in an array in the body region, each of the doped regions is surrounded by the conductive channel, wherein a channel between each of the doped regions and the conductive channel is in a shape of a Chinese character 'hui';

or,

on a cross section perpendicular to the thickness direction of the body region, the doped regions are rectangular and are arranged in the body region in parallel along the long side direction of the rectangle, at least one conductive channel is arranged between every two adjacent doped regions, and a channel between each doped region and the conductive channel is rectangular.

8. The semiconductor device according to claim 7, wherein a plurality of the doped regions are connected to the same source electrode.

9. A semiconductor device according to claim 1 or 2, wherein the conductive material is polysilicon.

10. The semiconductor device according to claim 1 or 2, wherein the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

Images