CN114784110A - Shielding gate trench MOSFET and manufacturing method thereof - Google Patents
Shielding gate trench MOSFET and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The embodiment of the invention discloses a shielded gate trench MOSFET and a manufacturing method thereof. The shielded gate trench MOSFET includes: an N + substrate; an N-epitaxial layer arranged on one side of the N + substrate; a shielding groove and a P-type doped layer are arranged in the N-epitaxial layer, and a first oxide layer and shielding polysilicon are arranged in the shielding groove; the P-type doping layer is a film layer formed by doping N-epitaxial layers positioned at the bottom and the side wall of the shielding groove, and the first oxidation layer is arranged between the shielding groove and the shielding polycrystalline silicon. Further optimizing device performance. According to the technical scheme of the embodiment, the P-type doped layers are formed at the bottom and the side wall of the shielding groove, so that the charge balance inside the N-epitaxial layer can be realized, the breakdown voltage of the source and the drain of the device is improved, and the performance of the device is further improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a shielded gate trench MOSFET and a manufacturing method thereof.
Background
In the prior art, a shielded Gate Trench Metal Oxide Semiconductor Field Effect Transistor (SGT MOSFET) realizes charge balance by forming a shielding dielectric layer (usually an Oxide layer) in a Trench, and the higher the source-drain breakdown voltage is, the thicker the required shielding dielectric layer is. However, in the mainstream design of the SGT device at present, in order to obtain a lower on-resistance per unit area, the cell size needs to be reduced as much as possible, and the width of the trench becomes smaller and smaller, so that a thick dielectric layer is difficult to form in the trench, the source-drain breakdown voltage cannot be further improved, and the improvement of the performance of the SGT MOSFET device is limited.
Disclosure of Invention
The invention provides a shielded gate trench MOSFET and a manufacturing method thereof, which are used for realizing charge balance inside an N-epitaxial layer, improving the breakdown voltage of a source and a drain of a device and further improving the performance of the device.
According to an aspect of the present invention, there is provided a shielded gate trench MOSFET comprising:
an N + substrate;
the N-epitaxial layer is arranged on one side of the N + substrate;
a shielding groove and a P-type doping layer are arranged in the N-epitaxial layer, and a first oxide layer and shielding polycrystalline silicon are arranged in the shielding groove; the P-type doped layer is a film layer formed by doping N-epitaxial layers positioned at the bottom and the side wall of the shielding groove, and the first oxidation layer is arranged between the shielding groove and the shielding polycrystalline silicon.
Optionally, the shielded gate trench MOSFET further comprises:
the drain electrode metal layer is arranged on one side, far away from the N-epitaxial layer, of the N + substrate;
the N + source region and the P-well region are arranged on one side, far away from the N + substrate, of the N-epitaxial layer, and the N + source region is arranged on one side, far away from the N + substrate, of the P-well region; the P-well region is provided with a gate groove which penetrates through the N + source region and the P-well region and extends into the N-epitaxial layer; a second oxide layer and a polysilicon gate are arranged in the gate trench, and the second oxide layer is arranged between the gate trench and the polysilicon gate;
the semiconductor device comprises a dielectric layer arranged on one side of the N-epitaxial layer, which is far away from the P-well region, and a source electrode metal layer arranged on one side of the dielectric layer, which is far away from the N-epitaxial layer, wherein the source electrode metal layer is respectively connected with the P-well region and the N + source region.
Optionally, the gate trench width includes 0.5 ~ 2.5um, the shielding trench width includes 0.4 ~ 2.4um, the gate trench depth includes 0.6 ~ 1.5um, the shielding trench depth includes 1um ~ 6um, the thickness of P type doped layer includes 0.1 ~ 0.5 um.
Optionally, the doping material of the P-type doped layer comprises boron or aluminum.
According to another aspect of the present invention, there is provided a method for fabricating a shielded gate trench MOSFET, the method comprising:
providing an N + substrate;
forming an N-epitaxial layer on one side of the N + substrate;
forming a shielding groove in the N-epitaxial layer, and doping the N-epitaxial layer positioned at the bottom and the side wall of the shielding groove to form a P-type doped layer;
forming a first oxide layer and shielding polysilicon in the shielding groove; wherein the first oxide layer is disposed between the shield trench and the shield polysilicon gate.
Optionally, forming a shielding trench and a P-type doped layer in the shielding trench in the N-epitaxial layer includes:
forming a shielding groove on the N-epitaxial layer;
injecting P-type impurities into the side wall and the bottom of the shielding groove along the first direction, the second direction and the third direction respectively; wherein the first direction, the second direction, and the third direction are different;
and carrying out high-temperature annealing treatment to form a P-type doped layer.
Optionally, an included angle between the first direction and the second direction and a normal of the N-epitaxial layer is greater than 0 ° and less than or equal to 30 °, and the third direction is parallel to the normal of the N-epitaxial layer.
Optionally, the P-type impurity comprises boron or aluminum, and the implantation dose comprises 1012～1015Per cm2The implantation energy is 10 Kev-120 Kev.
Optionally, before forming the shield trench in the N-epitaxial layer, the method further includes:
forming a gate trench in the N-epitaxial layer;
forming a third oxide layer on the surface of the gate trench, wherein the third oxide layer covers the side wall of the gate trench and the surface of the N-epitaxial layer far away from the N + substrate;
forming a shielding groove on the N-epitaxial layer, wherein the shielding groove comprises:
etching the bottom of the gate trench to form the shielding trench;
after the high-temperature annealing treatment is carried out to form the P-type doped layer, the method further comprises the following steps: removing the third oxide layer;
after forming the first oxide layer and the shield polysilicon in the shield trench, the method further comprises:
forming a second oxide layer and a polysilicon gate in the gate trench, wherein the second oxide layer is arranged between the gate trench and the polysilicon gate;
doping one side of the N-epitaxial layer, which is far away from the substrate, to form an N + source region and a P-well region, wherein the N + source region is arranged on one side of the P-well region, which is far away from the N + substrate;
forming a dielectric layer on one side of the N-epitaxial layer far away from the P-well region;
forming a source metal layer on one side of the dielectric layer far away from the N-epitaxial layer, wherein the source metal layer is respectively connected with the P-well region and the N + source region;
and forming a drain metal layer on one side of the N + substrate far away from the N-epitaxial layer.
Optionally, the temperature of the high-temperature annealing treatment includes 800 ℃ to 1000 ℃.
According to the technical scheme, the P-type doping layer is formed by doping the N-epitaxial layer 20 at the bottom and on the side wall of the shielding groove, the problem that in the prior art, due to the fact that the size of the groove is reduced, the increase of the thickness of the dielectric layer in the groove is difficult, the improvement of source-drain breakdown voltage is limited is solved, the limitation of the reduction of the size of the groove and the thickness of the dielectric layer in the groove is avoided, the breakdown voltage of the source-drain of the device can be greatly improved, the doping concentration of the N-epitaxial layer is improved under the same breakdown voltage level, the unit area on-resistance is reduced, the charge balance inside the N-epitaxial layer is realized, and the performance of the device is further improved.
It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a shielded gate trench MOSFET according to an embodiment of the present invention;
fig. 2 is a flow chart of a method of fabricating a shielded gate trench MOSFET according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of the structure corresponding to step S120 in the method for manufacturing the shielded gate trench MOSFET according to the embodiment of the invention;
fig. 4 is a cross-sectional view of the structure corresponding to step S130 in the method for manufacturing the shielded gate trench MOSFET according to the embodiment of the invention;
fig. 5 is a cross-sectional view of a structure provided in accordance with an embodiment of the present invention, showing a P-type impurity implantation performed on the sidewalls and bottom of a shield trench along a first direction;
fig. 6 is a cross-sectional view of a structure provided in accordance with an embodiment of the present invention, showing a P-type impurity implantation performed on the sidewalls and bottom of the shield trench along a second direction;
fig. 7 is a cross-sectional view of a structure provided in accordance with an embodiment of the present invention, wherein P-type impurity implantation is performed on the sidewalls and bottom of the shield trench along a third direction;
fig. 8 is a cross-sectional view of a corresponding structure for forming a gate trench in an N-epi layer according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a structure corresponding to a third oxide layer formed on the surface of a gate trench according to an embodiment of the present invention;
fig. 10 is a cross-sectional view of a structure provided in accordance with an embodiment of the present invention for etching the bottom of a gate trench to form a shield trench.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The SGT MOSFET has wide application in the field of medium and low voltage power devices due to excellent performance. Compared with a conventional MOSFET, the SGT structure has a charge coupling effect, and horizontal depletion is introduced on the basis of vertical depletion, so that the SGT MOSFET can obtain higher source-drain breakdown voltage compared with a common MOS device by adopting the epitaxial specification with the same doping concentration, namely the SGT device can adopt the epitaxy with the higher doping concentration under the same breakdown voltage level, and the reduction of the on-resistance of the device in unit area is facilitated.
An embodiment of the present invention provides a shielded gate trench MOSFET, and fig. 1 is a schematic structural diagram of a shielded gate trench MOSFET provided according to an embodiment of the present invention, and referring to fig. 1, the shielded gate trench MOSFET includes: an N + substrate 10; an N-epitaxial layer 20 disposed on one side of the N + substrate 10; a shielding groove 30 and a P-type doping layer 203 are arranged in the N-epitaxial layer 20, and a first oxidation layer 31 and shielding polysilicon 32 are arranged in the shielding groove 30; the P-type doped layer 203 is a film formed by doping the N-epitaxial layer 20 located at the bottom and the sidewall of the shielding trench 30, and the first oxide layer 31 is disposed between the shielding trench 30 and the shielding polysilicon 32.
The shielding polysilicon 32 can be used as a field plate to optimize the electric field in the N-epitaxial layer 20, so as to improve the doping concentration in the N-epitaxial layer 20 to reduce the resistance thereof, and obtain a lower on-resistance than a common MOSFET under the same breakdown voltage; the first oxide layer 31 and the shielding polysilicon 32 form a shielding gate structure, and the shielding gate structure can effectively reduce the dead-against area of the control gate and the drain, effectively reduce the miller capacitance, have a higher input capacitance/reverse transmission capacitance value, and improve the drain voltage oscillation resistance of the device gate.
At present, in order to obtain a lower on-resistance per unit area in the prior art, the cell size and the width of a trench become smaller and smaller, so that a thick dielectric layer is difficult to form in the trench, the source-drain breakdown voltage cannot be further improved, and the improvement of the performance of an SGT MOSFET device is limited. In the embodiment of the invention, the shielding groove 30 is formed in the N-epitaxial layer 20 of the shielding gate groove MOSFET, and the P-type doping layer 203 is formed by doping the N-epitaxial layer 20 at the bottom and the side wall of the shielding groove 30 by adopting an ion implantation process. The P-type doped layer 203 has the charge balance capability, can change the electric field distribution in the N-epitaxial layer 20, is not limited by the reduction of the size of the groove and the thickness of a dielectric layer in the groove, can reduce the conduction loss, can obtain lower on-resistance per unit area, and can improve the source-drain breakdown voltage and the performance of a device.
It should be noted that fig. 1 only exemplarily shows the case where the N-epitaxial layer 20 is provided with 3 shield trenches 30, but those skilled in the art will appreciate that the N-epitaxial layer is not limited to 3 shield trenches 30 and may be provided according to actual needs.
The technical scheme of this embodiment forms the P type doping layer through doping the N-epitaxial layer 20 of the bottom and the lateral wall that shield the slot, because of the slot size reduces among the prior art, the increase difficulty of medium layer thickness makes the promotion of source-drain breakdown voltage receive the restriction problem, the P type doping layer in this embodiment does not receive the restriction that the slot size reduces and medium layer thickness in the slot, the breakdown voltage of improvement device source-drain that can be very big, thereby reach the doping concentration who improves the N-epitaxial layer under the same breakdown voltage level, reduce unit area on-resistance, realize the inside charge balance of N-epitaxial layer, and then promote the performance of device.
With continued reference to fig. 1, optionally, the shielded gate trench MOSFET further comprises: the drain metal layer 40 is arranged on one side, far away from the N-epitaxial layer 20, of the N + substrate 10; the N + source region 201 and the P-well region 202 are arranged on one side, far away from the N + substrate 10, of the N-epitaxial layer 20, and the N + source region 201 is arranged on one side, far away from the N + substrate 10, of the P-well region 202; the P-well region 202 is provided with a gate trench 50, and the gate trench 50 penetrates through the N + source region 201 and the P-well region 202 and extends into the N-epitaxial layer 20; a second oxide layer 501 and a polysilicon gate 502 are arranged in the gate trench 50, and the second oxide layer 501 is arranged between the gate trench 50 and the polysilicon gate 502; the source electrode structure comprises a dielectric layer 60 arranged on one side of the N-epitaxial layer 20 far away from the P-well region 202, and a source electrode metal layer 70 arranged on one side of the dielectric layer 60 far away from the N-epitaxial layer 20, wherein the source electrode metal layer 70 is respectively connected with the P-well region 202 and the N + source region 201. With continued reference to fig. 1, optionally, the width of the gate trench 50 includes 0.5-2.5 um, the width of the shielding trench 30 includes 0.4-2.4 um, the depth of the gate trench 50 includes 0.6-1.5 um, the depth of the shielding trench 30 includes 1 um-6 um, and the thickness of the P-type doped layer 203 includes 0.1-0.5 um.
The relative positions of the gate trench 50 and the shield trench 30 can be divided into an upper-lower structure and a left-right structure, and in order to reduce the difficulty of the device manufacturing process, the embodiment of the invention mainly adopts the upper-lower structure.
Specifically, the width of the gate trench 50 may be 0.5 to 2.5um, and the depth may be 0.6 to 1.5 um; the width of the shielding groove 30 can be 0.4-2.4 um, and the depth of the shielding groove 30 can be 1-6 um; when the width and depth ranges are adopted, the process difficulty can be reduced, the device manufacturing process is simplified, the oxide layer in the groove can be enabled to have proper thickness, the cell size is reduced, and the device size is reduced. The thickness of the P-type doping layer 203 can be 0.1-0.5 um, so that the size range of the shielding trench 30 is small, and the breakdown voltage of the device can be greatly improved.
When the thickness of the P-type doped layer 203 is less than 0.1um, the process is complex and difficult to realize, and the charge balancing capability inside the N-epitaxial layer is poor; when the thickness of the P-type doped layer 203 is greater than 0.5um, the thickness of the first oxide layer 31 in the shielding trench 30, the shielding trench 30 and the cell size are affected. Therefore, when the thickness of the P-type doped layer 203 is 0.1 to 0.5um, the process difficulty can be reduced, the capability of balancing the charges inside the N-epitaxial layer is strong, the thickness of the first oxide layer 31 cannot be affected, the size of the shielding trench 30 cannot be increased, and the cell has a smaller size.
With continued reference to fig. 1, optionally, the doping material of P-type doped layer 203 comprises boron or aluminum.
The lightly doped ions of the N-epitaxial layer 20 are pentavalent elements (phosphorus or arsenic), and the ions implanted by the P-type doped layer 203 may be trivalent elements (boron or boron fluoride), or may be aluminum. When the doping material of the P-type doping layer 203 is boron or aluminum, the doping of the formed P-type doping layer 203 is more uniform, so that the charge balance of the N-epitaxial layer 20 is realized, and the source-drain breakdown voltage of the device is improved.
An embodiment of the present invention provides a method for manufacturing a shielded gate trench MOSFET, and fig. 2 is a flowchart of a method for manufacturing a shielded gate trench MOSFET according to an embodiment of the present invention, and with reference to fig. 2, the method includes:
s110, providing an N + substrate.
Wherein the material of the N + substrate may include silicon, and is mainly manufactured by a czochralski or float zone process.
And S120, forming an N-epitaxial layer on one side of the N + substrate.
Fig. 3 is a cross-sectional view of a structure corresponding to step S120 in the method for manufacturing a shielded gate trench MOSFET according to the embodiment of the present invention, and referring to fig. 3, an N-epitaxial layer 20 is grown on a surface of an N + substrate 10 formed by heavily doping a silicon material, where a thickness of the N-epitaxial layer 20 is determined according to a source-drain withstand voltage required by a device, for example, the thickness may range from 5 micrometers to 20 micrometers.
S130, forming a shielding groove in the N-epitaxial layer, and doping the N-epitaxial layer at the bottom and the side wall of the shielding groove to form a P-type doped layer.
Fig. 4 is a cross-sectional view of a structure corresponding to step S130 in the method for manufacturing a shielded gate trench MOSFET according to an embodiment of the present invention, and referring to fig. 4, photolithography and dry etching are performed in the N-epitaxial layer 20 to form a shielded trench 30, and then implantation of P-type impurities is performed on the N-epitaxial layer 20 at the bottom and the sidewalls of the shielded trench 30 to form a P-type doped layer 203.
S140, forming a first oxidation layer and shielding polycrystalline silicon in the shielding groove; the first oxide layer is arranged between the shielding groove and the shielding polysilicon gate.
The growth of the first oxide layer adopts a method of high-density plasma chemical vapor deposition and thermal oxidation or is used alternately.
The manufacturing method of the shielded gate trench MOSFET is used for manufacturing the shielded gate trench MOSFET provided by any embodiment of the invention, and the P-type doped layer is formed by doping the N-epitaxial layers at the bottom and on the side wall of the shielded trench, so that the space of the first oxide layer and the shielded polysilicon in the shielded trench is not influenced, the problem that in the prior art, due to the fact that the size of the trench is reduced, the increase of the thickness of a dielectric layer in the trench is difficult, the increase of the source-drain breakdown voltage is limited is solved, the limitation of the size reduction of the trench and the thickness of the dielectric layer in the trench can be avoided, the source-drain breakdown voltage of a device can be greatly improved, the doping concentration of the N-epitaxial layer is improved under the same breakdown voltage level, the on-resistance of a unit area is reduced, the charge balance inside the N-epitaxial layer is realized, and the performance of the device is improved.
Fig. 5 is a cross-sectional view of a structure provided according to an embodiment of the present invention, wherein P-type impurity implantation is performed on sidewalls and a bottom of a shield trench along a first direction, fig. 6 is a cross-sectional view of a structure provided according to an embodiment of the present invention, wherein P-type impurity implantation is performed on sidewalls and a bottom of a shield trench along a second direction, fig. 7 is a cross-sectional view of a structure provided according to an embodiment of the present invention, wherein P-type impurity implantation is performed on sidewalls and a bottom of a shield trench along a third direction, and referring to fig. 5-7, optionally, a shield trench and a P-type doped layer located in the shield trench are formed on an N-epitaxial layer 20, including:
forming a shielding groove 30 on the N-epitaxial layer 20;
implanting P-type impurities into the sidewall and the bottom of the shield trench 30 along the first direction 1, the second direction 2, and the third direction 3, respectively; wherein the first direction 1, the second direction 2 and the third direction 3 are different;
and carrying out high-temperature annealing treatment to form a P-type doped layer.
The P-type impurities are injected into the N-epitaxial layer 20 on the side wall and the bottom of the shielding trench 30 along the first direction 1, the second direction 2 and the third direction 3, but the injection is shallow, the initially formed P-type doped layer is narrow, and a subsequent high-temperature annealing process is required to perform junction pushing, so that the P-type doped layer is thicker, has stronger charge balance capability, and forms a final shielding trench.
With continued reference to fig. 5-7, optionally, the first direction 1 and the second direction 2 are at an angle greater than 0 ° and less than or equal to 30 ° to the normal to the N-epitaxial layer 20, and the third direction 3 is parallel to the normal to the N-epitaxial layer 20.
Specifically, the first direction 1 and the second direction 2 are respectively injected at a left inclination angle and a right inclination angle, the third direction 3 is vertically injected at the front, and P-type impurities are injected for three times into the N-epitaxial layer 20 at the bottom and the side wall of the shielding groove 30 in a front and oblique angle mode to form a P-type doped layer, so that the distribution uniformity of injected ions is improved, the doping for forming the P-type doped layer is more uniform, the charge balance of the N-epitaxial layer 20 is realized, and the source-drain breakdown voltage of the device is improved.
Therefore, the angles of implanting the P-type impurities in the first direction 1 and the second direction 2 in the embodiment of the invention are critical, and the doping of the formed P-type doped layer can be more uniform. The depth and the width of the shielding groove 30 and the thickness of the oxide layer can be reasonably adjusted, the injection angles are different, and the thickness of the P-type doped layer around the shielding groove 30 can be adjusted, so that the source-drain breakdown voltage of the device is improved.
Optionally, the P-type impurity comprises boron or aluminum, and the implant dose comprises 1012～1015Per cm2The implantation energy is 10Kev to 120 Kev.
Wherein, when the P-type impurity is boron or aluminum, the implantation dosage is 1012～1015The doping uniformity and the thickness of the formed P-type doping layer are optimal when the injection energy is 10 Kev-120 Kev per cm2, the limitation of the reduction of the size of the groove and the thickness of the medium layer in the groove is avoided, the breakdown voltage of the source and the drain of the device can be greatly improved, and the performance of the device is further improved.
Fig. 8 is a cross-sectional view of a structure corresponding to a gate trench formed on an N-epitaxial layer according to an embodiment of the present invention, fig. 9 is a cross-sectional view of a structure corresponding to a third oxide layer formed on a surface of the gate trench provided according to an embodiment of the present invention, fig. 10 is a cross-sectional view of a structure corresponding to a shield trench formed by etching a bottom of the gate trench provided according to an embodiment of the present invention, and referring to fig. 8-10, optionally, before forming the shield trench on the N-epitaxial layer, the method further includes:
forming a gate trench 50 in the N-epitaxial layer 20;
forming a third oxide layer 503 on the surface of the gate trench 50, wherein the third oxide layer 503 covers the sidewall of the gate trench 50 and the surface of the N-epitaxial layer 20 away from the N + substrate 10;
forming a shield trench 30 in the N-epitaxial layer 20, including:
etching the bottom of the gate trench 50 to form a shielding trench 30;
after the high-temperature annealing treatment is carried out to form the P-type doped layer, the method further comprises the following steps: removing the third oxide layer 503;
after forming the first oxide layer and the shield polysilicon in the shield trench, the method further comprises:
forming a second oxide layer and a polysilicon grid electrode in the grid groove, wherein the second oxide layer is arranged between the grid groove and the polysilicon grid electrode;
doping one side of the N-epitaxial layer, which is far away from the substrate, to form an N + source region and a P-well region, wherein the N + source region is arranged on one side of the P-well region, which is far away from the N + substrate;
forming a dielectric layer on one side of the N-epitaxial layer far away from the P-well region;
forming a source electrode metal layer on one side of the dielectric layer far away from the N-epitaxial layer, wherein the source electrode metal layer is respectively connected with the P-well region and the N + source region;
and forming a drain metal layer on one side of the N + substrate far away from the N-epitaxial layer.
Specifically, referring to fig. 8, photolithography and dry etching are performed in the N-epitaxial layer 20 to form a gate trench 50; referring to fig. 9, a third oxide layer 503 is formed on the surface of the gate trench 50 by thermal growth, photolithography and dry etching are performed to remove the third oxide layer 503 at the bottom of the gate trench 50 and to retain the third oxide layer 503 at the sidewall and top of the gate trench 50, where the thickness of the third oxide layer 503 may be set to be
Referring to fig. 10, in the N-epitaxial layer 20, the bottom of the gate trench 50 is subjected to photolithography and dry etching to form a shielding trench 30, the N-epitaxial layer 20 at the bottom and the sidewall of the shielding trench 30 is subjected to ion implantation to form a relatively thin P-type doped layer, and a high-temperature annealing process is performed to form a P-type doped layer with a suitable thickness; and finally, removing the third oxide layer 503 on the side wall and the top of the gate trench 50, where the removing method may be wet etching.
The subsequent process steps are the same as those of a conventional SGT MOSFET device, and finally, the complete device structure provided by the embodiment of the invention is formed. The second oxide layer is grown by a high-density plasma chemical vapor deposition method and a thermal oxidation method or alternately, the material of the polysilicon gate can be polysilicon, and the forming method can be chemical vapor deposition and the like. The process of forming the polysilicon gate is to deposit a polysilicon layer, carry out planarization and graphical processing on the deposited polysilicon layer, and remove the redundant polysilicon layer on the surface to form the polysilicon gate. And doping the side of the N-epitaxial layer far away from the substrate by adopting an ion implantation process to form an N + source region and a P-well region. Wherein, the N + source region is heavily doped, and the P-well region is lightly doped.
Optionally, the temperature of the high-temperature annealing treatment includes 800 ℃ to 1000 ℃.
The annealing process mainly refers to a heat treatment process in which the material is exposed to a high temperature for a long time and then slowly cooled. The main purposes are to relieve stress, increase material ductility and toughness, create special microstructures, etc. When the temperature of the high-temperature annealing treatment is 800-1000 ℃, the thickness of the formed P-type doped layer is optimal, and the P-type doped layer has strong charge balance capability.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A shielded gate trench MOSFET comprising:
an N + substrate;
the N-epitaxial layer is arranged on one side of the N + substrate;
a shielding groove and a P-type doping layer are arranged in the N-epitaxial layer, and a first oxide layer and shielding polycrystalline silicon are arranged in the shielding groove; the P-type doped layer is a film layer formed by doping N-epitaxial layers positioned at the bottom and the side wall of the shielding groove, and the first oxidation layer is arranged between the shielding groove and the shielding polycrystalline silicon.
2. The shielded gate trench MOSFET of claim 1 further comprising:
the drain electrode metal layer is arranged on one side of the N + substrate, which is far away from the N-epitaxial layer;
the N + source region and the P-well region are arranged on one side, far away from the N + substrate, of the N-epitaxial layer, and the N + source region is arranged on one side, far away from the N + substrate, of the P-well region; the P-well region is provided with a grid groove which penetrates through the N + source region and the P-well region and extends into the N-epitaxial layer; a second oxide layer and a polysilicon gate are arranged in the gate trench, and the second oxide layer is arranged between the gate trench and the polysilicon gate;
the semiconductor device comprises a dielectric layer arranged on one side of the N-epitaxial layer, which is far away from the P-well region, and a source electrode metal layer arranged on one side of the dielectric layer, which is far away from the N-epitaxial layer, wherein the source electrode metal layer is respectively connected with the P-well region and the N + source region.
3. The shielded gate trench MOSFET of claim 1, wherein the gate trench width comprises 0.5-2.5 um, the shielded trench width comprises 0.4-2.4 um, the gate trench depth comprises 0.6-1.5 um, the shielded trench depth comprises 1-6 um, and the thickness of the P-type doped layer comprises 0.1-0.5 um.
4. The shielded gate trench MOSFET of claim 1 wherein the dopant material of the P-type doped layer comprises boron or aluminum.
5. A method for manufacturing a shielded gate trench MOSFET is characterized by comprising the following steps:
providing an N + substrate;
forming an N-epitaxial layer on one side of the N + substrate;
forming a shielding groove in the N-epitaxial layer, and doping the N-epitaxial layer positioned at the bottom and the side wall of the shielding groove to form a P-type doped layer;
forming a first oxide layer and shielding polysilicon in the shielding groove; wherein the first oxide layer is disposed between the shield trench and the shield polysilicon gate.
6. The method of claim 5, wherein forming a shield trench and a P-type doped layer in the shield trench in the N-epi layer comprises:
forming a shielding groove on the N-epitaxial layer;
injecting P-type impurities into the side wall and the bottom of the shielding groove along the first direction, the second direction and the third direction respectively; wherein the first direction, the second direction, and the third direction are different;
and carrying out high-temperature annealing treatment to form a P-type doped layer.
7. The method of claim 6, wherein an angle between the first direction and the second direction and a normal of the N-epitaxial layer is greater than 0 ° and less than or equal to 30 °, and the third direction is parallel to the normal of the N-epitaxial layer.
8. The method of claim 6, wherein the P-type impurity comprises boron or aluminum, and the implantation dose comprises 1012～1015Per cm2The implantation energy is 10Kev to 120 Kev.
9. The method of claim 6, further comprising, before forming the N-epi layer with the shield trench:
forming a gate trench in the N-epitaxial layer;
forming a third oxide layer on the surface of the gate trench, wherein the third oxide layer covers the side wall of the gate trench and the surface of the N-epitaxial layer far away from the N + substrate;
forming a shielding groove on the N-epitaxial layer, wherein the shielding groove comprises:
etching the bottom of the gate trench to form the shielding trench;
after the high-temperature annealing treatment is carried out to form the P-type doped layer, the method further comprises the following steps: removing the third oxide layer;
after forming the first oxide layer and the shield polysilicon in the shield trench, the method further comprises:
forming a second oxide layer and a polysilicon gate in the gate trench, wherein the second oxide layer is arranged between the gate trench and the polysilicon gate;
doping one side of the N-epitaxial layer, which is far away from the substrate, to form an N + source region and a P-well region, wherein the N + source region is arranged on one side of the P-well region, which is far away from the N + substrate;
forming a dielectric layer on one side of the N-epitaxial layer far away from the P-well region;
forming a source metal layer on one side of the dielectric layer far away from the N-epitaxial layer, wherein the source metal layer is respectively connected with the P-well region and the N + source region;
and forming a drain metal layer on one side of the N + substrate far away from the N-epitaxial layer.
10. The method of claim 6, wherein the high temperature annealing process temperature comprises 800 ℃ to 1000 ℃.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
| CN116110944A (en) * | 2023-04-12 | 2023-05-12 | 江苏应能微电子股份有限公司 | Shielded gate trench MOSFET device based on Resurf effect and preparation method thereof |
| CN116799070A (en) * | 2023-08-28 | 2023-09-22 | 江苏应能微电子股份有限公司 | Split gate trench MOS device with triple resurf structure and process |
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2022
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
| CN116110944A (en) * | 2023-04-12 | 2023-05-12 | 江苏应能微电子股份有限公司 | Shielded gate trench MOSFET device based on Resurf effect and preparation method thereof |
| CN116799070A (en) * | 2023-08-28 | 2023-09-22 | 江苏应能微电子股份有限公司 | Split gate trench MOS device with triple resurf structure and process |
| CN116799070B (en) * | 2023-08-28 | 2023-11-17 | 江苏应能微电子股份有限公司 | Split gate trench MOS device with triple resurf structure and process |
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