CN115347038A - Semiconductor device structure and preparation method thereof - Google Patents

Semiconductor device structure and preparation method thereof Download PDF

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Publication number
CN115347038A
CN115347038A CN202211030210.6A CN202211030210A CN115347038A CN 115347038 A CN115347038 A CN 115347038A CN 202211030210 A CN202211030210 A CN 202211030210A CN 115347038 A CN115347038 A CN 115347038A
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substrate
grid
layer
conductivity type
gate
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Chinese (zh)
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叶彪
韩廷瑜
王东
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

Abstract

The invention relates to a semiconductor device structure and a preparation method thereof, wherein the semiconductor device structure comprises: the substrate is provided with a grid groove; the liner layer is at least positioned on the side wall and the bottom of the grid groove; the shielding grid electrode is positioned on the side wall of the liner layer facing the inside of the grid groove, a gap is formed between the side walls of the shielding grid electrode facing the inside of the grid groove, and the upper surface of the shielding grid electrode is lower than the top of the grid groove; the insulating medium layer is positioned in the gap, fills the gap and covers the upper surface of the shielding grid; the polysilicon gate is positioned in the gate groove and positioned on the upper surface of the insulating medium layer; the source regions are positioned on two opposite sides of the grid groove and electrically connected with the shielding grid; the source electrode is positioned on the upper surface of the substrate and is in contact with the source region; and the drain electrode is positioned on the lower surface of the substrate. By adopting the semiconductor device structure and the preparation method thereof, the capacitance and the switching loss of the source electrode and the drain electrode can be reduced.

Description

Semiconductor device structure and preparation method thereof
Technical Field
The present disclosure relates to integrated circuit technologies, and in particular, to a semiconductor device structure and a method for fabricating the same.
Background
With the development of Semiconductor technology, power Semiconductor devices are receiving more and more attention, wherein a novel power Semiconductor device, namely a Shielded Gate Trench (SGT) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), is used as a core power control component of a switching device, and is applied to a motor driving system, an inverter system and a power management system in the fields of new energy electric vehicles, novel photovoltaic power generation, energy-saving household appliances and the like, the share of the middle and low voltage power Semiconductor market is gradually increased, and the performance and the reliability directly determine the energy conversion efficiency of the system and the reliability of the system.
However, due to the structural particularity, the closer distance between the source field plate and the drain field plate of the SGT MOSFET results in a larger source-drain capacitance, thereby increasing the switching loss.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a semiconductor device structure and a method for fabricating the same, which can reduce the capacitance of the source and the drain and reduce the switching loss.
In order to achieve the above object, in one aspect, the present invention provides a semiconductor device structure comprising:
a substrate having a gate trench therein;
the liner layer is at least positioned on the side wall and the bottom of the grid groove;
the shielding grid electrode is positioned on the side wall of the lining layer facing the inside of the grid groove, and a gap is formed between the side walls of the shielding grid electrode facing the inside of the grid groove; the upper surface of the shielding grid is lower than the top of the grid groove;
the insulating medium layer is filled in the gap and covers the upper surface of the shielding grid;
the polysilicon grid is positioned in the grid groove and positioned on the upper surface of the insulating medium layer;
the source regions are positioned in the substrate and positioned on two opposite sides of the grid groove; the source region is electrically connected with the shielding grid;
the source electrode is positioned on the upper surface of the substrate and is in contact with the source region;
and the drain electrode is positioned on the lower surface of the substrate.
In one embodiment, a doped substrate of a first conductivity type; the drain electrode is positioned on the lower surface of the doped substrate of the first conduction type; the epitaxial layer is positioned on the upper surface of the doped substrate, and a drift region of a first conduction type is formed in the epitaxial layer; a body region of a second conductivity type located within the drift region of the first conductivity type; the source region is located on the body region of the second conductivity type.
In one embodiment, the doped substrate of the first conductivity type comprises a silicon substrate, and the pad layer comprises a silicon oxide layer; the shield grid comprises a polysilicon shield grid; the insulating medium layer comprises a silicon oxide layer.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.
In one embodiment, the thickness of the shielding grid is 1/4-1/3 of the width of the grid groove.
The invention also provides a preparation method of the semiconductor device structure, which comprises the following steps:
providing a substrate, and forming a gate trench in the substrate;
forming a liner layer on the side wall and the bottom of the gate trench;
forming a shielding grid on the side wall of the liner layer facing the inside of the grid groove, and forming an insulating medium layer; gaps are formed between the side walls of the shielding grids facing the grid grooves; the upper surface of the shielding grid is lower than the top of the grid groove; the insulating medium layer fills the gap and covers the upper surface of the shielding grid;
forming a polysilicon gate in the gate trench;
forming source regions in the substrate, wherein the source regions are positioned on two opposite sides of the grid groove and are electrically connected with the shielding grid;
forming a source electrode on the upper surface of the substrate, wherein the source electrode is in contact with the source region;
and forming a drain electrode on the lower surface of the substrate.
In one embodiment, the providing a substrate, and the forming a gate trench in the substrate includes: providing a doped substrate of a first conductivity type; forming an epitaxial layer on the upper surface of the doped substrate of the first conductivity type; and forming the gate trench in the drift region of the first conductivity type.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.
In one embodiment, the forming a shield gate on a sidewall of the gate trench and forming an insulating dielectric layer includes: forming a shielding grid material layer on the surface of the liner layer; removing the shielding grid electrode material layer positioned on the upper surface of the liner layer and at the bottom of the grid electrode groove, etching back the shielding grid electrode material layer positioned in the grid electrode groove, and keeping the upper surface of the shielding grid electrode material layer lower than the top of the grid electrode groove; forming an insulating medium material layer, wherein the insulating medium material layer fills the gate groove and covers the surface of the liner layer; and removing the insulating dielectric material layer on the substrate, etching back the insulating dielectric material layer in the gate trench and retaining the shielding gate material layer to obtain the insulating dielectric layer and the shielding gate.
In one embodiment, the thickness of the shielding grid is 1/4-1/3 of the width of the grid groove.
According to the semiconductor device structure and the preparation method thereof, in the semiconductor device structure, the shielding grid electrode has the gap and has the smaller cross section area, so that the capacitance between the source electrode and the drain electrode in the semiconductor device structure can be obviously reduced, the switching loss is further reduced, and the efficiency of the semiconductor device structure is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of an SGT MOSFET;
fig. 2 is a schematic structural diagram of a semiconductor device structure provided in an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device structure according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of step S301 in a method for manufacturing a semiconductor device structure according to an embodiment of the present application;
fig. 5 is a schematic flowchart of step S303 in a method for manufacturing a semiconductor device structure according to an embodiment of the present application;
fig. 6 to fig. 13 are schematic cross-sectional structural views of structures obtained in steps of a method for manufacturing a semiconductor device structure according to an embodiment of the present application.
Description of reference numerals: 101-source electrode, 102-P type body region, 103-polysilicon gate electrode, 104-shield gate electrode, 105-N type drift region, 106-N + substrate, 107-drain electrode, 108-source region, 109-covering dielectric layer, 201-substrate, 202-liner layer, 203-shield gate electrode, 2031-shield gate electrode material layer, 204-insulating dielectric layer, 2041-insulating dielectric material layer, 205-polysilicon gate electrode, 206-source region, 207-source electrode, 208-drain electrode, 2011-doping base of first conductive type, 2012-epitaxial layer, 209-body region of second conductive type, 210-covering dielectric layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It should be understood that, in addition, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
When an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In some embodiments, the SGT MOSFET is used as a novel power semiconductor device, and the lateral depletion between trenches is enhanced by using the isolated polysilicon as a field plate, so that the doping concentration of the epitaxial layer can be increased, the on-resistance can be reduced, and the "silicon limit" can be broken. Referring to fig. 1, fig. 1 is a schematic structural diagram of an SGT MOSFET, as shown in fig. 1, the SGT MOSFET includes a source 101, a P-type body 102, a polysilicon gate 103, a shielding gate 104, an N-type drift region 105, an N + substrate 106, a drain 107, a source region 108, and a capping dielectric layer 109. The source 101 and the drain 107 are close to each other, and due to the structural particularity, a large source-drain capacitance is generated, and the switching loss is increased.
Based on the structure, the semiconductor device structure and the preparation method thereof are provided, wherein the capacitance of a source electrode and a drain electrode can be reduced, and the switching loss can be reduced.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor device structure according to an embodiment of the present disclosure, the semiconductor device structure includes a substrate 201, a liner layer 202, a shield gate 203, an insulating dielectric layer 204, a polysilicon gate 205, a source region 206, a source 207, and a drain 208.
A substrate 201, wherein the substrate 201 has a gate trench (not labeled), and the gate trench can be formed by etching the substrate 201 by using a plasma dry etching process; a pad layer 202, wherein the pad layer 202 is at least located on the sidewall and the bottom of the gate trench, wherein the pad layer 202 may include a field oxide layer, and the field oxide layer may include a silicon oxide layer or a silicon oxynitride layer; a shield gate 203, wherein the shield gate 203 is positioned on the sidewall of the gate liner layer 20 facing into the gate trench, and a gap is formed between the sidewalls of the shield gate 203 facing into the gate trench; the upper surface of shield gate 203 is lower than the top of the gate trench; an insulating dielectric layer 204 filling the gap and covering the upper surface of the shield gate 203; a polysilicon gate 205, wherein the polysilicon layer 205 is positioned in the gate trench and positioned on the upper surface of the insulating medium layer 204; a source region 206, wherein the source region 206 is positioned in the substrate 201 and positioned at two opposite sides of the gate trench; source region 206 is electrically connected to shield gate 203, and specifically, source region 206 may be electrically connected to shield gate 203 via a conductive plug; a source electrode 207 positioned on the upper surface of the substrate 201 and contacting the source region 206, wherein the source electrode 207 connects the semiconductor device structure with an external circuit; and a drain 208 and a drain region 208 are positioned on the lower surface of the substrate 201, and the drain 208 connects the semiconductor device structure with an external circuit and forms a transistor structure with the source 207 and the polysilicon gate 205.
In an alternative example, shield gates 203 are uniform in thickness, and shield gates 203 have a thickness less than half the width of the gate trenches.
In another alternative example, the thickness of the shield gate 203 on one sidewall of the gate liner layer 20 facing into the gate trench may be greater than the thickness of the shield gate 203 on the other sidewall of the gate liner layer 20 facing into the gate trench.
In one embodiment, the substrate 201 may include: a doped substrate 2011 of the first conductivity type; the drain 208 is located on the lower surface of the doped substrate 2011 of the first conductivity type; the epitaxial layer 2012 is located on an upper surface of the doped substrate 2011 of the first conductivity type, a drift region (not labeled) of the first conductivity type is formed in the epitaxial layer 2012, and the epitaxial layer 2012 may be a homogeneous epitaxial layer in which a silicon material is grown on the doped substrate 2011 of the first conductivity type, or may be a hetero-epitaxial layer in which a silicon carbide material is grown on the doped substrate 2011 of the first conductivity type; a body region 209 of the second conductivity type, the body region 209 of the second conductivity type being located within the drift region of the first conductivity type; source region 206 is located on body region 209 of the second conductivity type.
In one embodiment, the doped substrate 2011 of the first conductivity type may include a silicon substrate, and the pad layer 202 may include a silicon oxide layer; shield gate 203 may comprise a polysilicon shield gate; the insulating dielectric layer 204 may include a silicon oxide layer.
Specifically, the source region 206 is formed by implanting dopant ions into the substrate 201 using an ion implantation process.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
In one embodiment, shield gate 203 may have a thickness of, but not limited to, 1/4 to 1/3 of the width of the gate trench.
Referring to fig. 3 in conjunction with fig. 2, fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device structure according to an embodiment of the present disclosure, where the method for manufacturing the semiconductor device structure includes:
step S301, providing a substrate, and forming a gate trench in the substrate;
step S302, forming a liner layer on the side wall and the bottom of the gate trench;
step S303, forming a shielding grid on the side wall of the liner layer facing the inside of the grid groove and forming an insulating medium layer; a gap is reserved between the side walls of the shielding grid facing the inside of the grid groove; the upper surface of the shielding grid is lower than the top of the grid groove; the insulating medium layer fills the gap and covers the upper surface of the shielding grid;
step S304, forming a polysilicon gate in the gate groove;
step S305, forming source regions in the substrate, wherein the source regions are positioned at two opposite sides of the grid groove and are electrically connected with the shielding grid;
step S306, forming a source electrode on the upper surface of the substrate, wherein the source electrode is contacted with the source region;
in step S307, a drain is formed on the lower surface of the substrate.
Specifically, the steps of the method for fabricating the semiconductor device structure are set forth in detail below.
Step S301, a substrate is provided, and a gate trench is formed in the substrate.
Specifically, as shown in fig. 4, step S301 may include the following steps:
s3011, a doped substrate 2011 of the first conductivity type is provided, as shown in fig. 6.
Specifically, implanting ions of a first conductivity type into a silicon substrate or a substrate of a compound material (e.g., a substrate of a material such as gallium arsenide, gallium nitride, and silicon carbide) forms a doped substrate 1011 of the first conductivity type,
in step S3012, an epitaxial layer 2012 is formed on the upper surface of the doped substrate 2011 of the first conductivity type, as shown in fig. 6.
The epitaxial layer 2012 may be a homoepitaxial layer (e.g., a silicon material grown on a silicon substrate) or a heteroepitaxial layer (e.g., a silicon carbide material grown on a silicon substrate).
In step S3013, a drift region (not shown) of the first conductivity type is formed in the epitaxial layer 2012.
In step S3014, a gate trench is formed in the drift region of the first conductivity type.
Specifically, the gate trench may be formed using, but not limited to, a dry etching process.
And forming a gate trench between the body regions of the second conductor type.
In step S302, a liner layer 202 is formed on the sidewalls and bottom of the gate trench, as shown in fig. 6.
Specifically, the liner layer 202 may be formed on the sidewall and bottom of the gate trench by, but not limited to, chemical Vapor Deposition (CVD), and the liner layer 202 may be a field oxide layer, wherein the field oxide layer may include a silicon oxide layer or a silicon oxynitride layer. For example, the liner layer 202 is formed by growing a silicon dioxide layer in a high temperature furnace.
In step S303, referring to fig. 6 to 9, a shield gate 203 is formed on the surface of the liner layer 202 on the sidewall of the upper gate trench, and an insulating dielectric layer 204 is formed.
Specifically, as shown in fig. 5 to 9, step S303 may include the following steps:
in step 3031, a shielding gate material layer 2031 is formed on the surface of the liner layer 202, as shown in fig. 6.
In particular, in connection with fig. 2, the shield gate material layer 2031 may be formed using, but not limited to, a deposition process.
Step S3032 is to remove the shielding gate material layer 2031 on the top surface of the liner layer 202 and at the bottom of the gate trench, and etch back the shielding gate material layer 2031 in the gate trench, leaving the top surface of the shielding gate material layer 2031 lower than the top of the gate trench, as shown in fig. 7.
Specifically, referring to fig. 7, the shielding gate material layer 2031 on the upper surface of the substrate 201 and at the bottom of the gate trench may be removed by an etching process, and the structure after the etching is shown in fig. 7.
In step S3033, an insulating dielectric material layer 2041 is formed, as shown in fig. 8.
The insulating dielectric material layer 2041 fills the gate trench and covers the surface of the pad layer 202.
Specifically, the insulating dielectric material layer 2041 may be deposited by, but not limited to, performing a process to fill the gate trench with the insulating dielectric material layer 2041 and cover the surface of the pad layer 202.
Step S3034 is performed to remove the insulating dielectric material layer 2041 located on the substrate 201, and etch back the insulating dielectric material layer 2041 located in the gate trench and the shield gate material layer 2031 to obtain the insulating dielectric layer 204 and the shield gate 203, as shown in fig. 9.
As an example, the thickness of shield gate 203 may be less than half the width of the gate trench such that there is a gap within shield gate 203; the upper surface of shield gate 203 is lower than the top of the gate trench; an insulating dielectric layer 204 fills the gap and covers the upper surface of the shield gate 203.
In step S304, a polysilicon gate 205 is formed in the gate trench, as shown in fig. 10.
Specifically, a polysilicon layer may be formed in the gate trench and on the liner layer 202; the polysilicon layer on the pad layer 202 and the pad layer 202 on the substrate 201 are then removed, resulting in the structure shown in fig. 10.
Step S305, forming a source region 206 in the substrate 201, as shown in fig. 11.
Specifically, referring to fig. 11, a source region 206 is formed in the substrate 201. Source regions 206 are located on opposite sides of the gate trench and are electrically connected to shield gate 203. Specifically, before forming the source region 206, an interconnection via exposing the shield gate 203 may be formed in the substrate 201, and then a conductive plug may be formed in the interconnection via, where the conductive plug contacts the shield gate 203; after forming source regions 206, source regions 206 are in contact with shield gates 203 via conductive plugs.
Specifically, the drift region of the first conductivity type is subjected to ion implantation of the second conductivity type to form an ion implantation region of the second conductivity type, which is the source region 206.
In one example, prior to forming source regions 206 in substrate 201, forming body regions 209 of a second conductivity type in substrate 201 is also included, as shown in fig. 11.
Specifically, ions of the second conductivity type are implanted into the drift region of the first conductivity type, thereby forming a body region 209 of the second conductivity type within the drift region of the first conductivity type.
In step S306, a source 207 is formed on the upper surface of the substrate 201.
Wherein source 207 is in contact with source region 206 as shown in fig. 12.
Specifically, referring to fig. 12, an electrode is drawn from the source region 206 as a source 207, and the semiconductor device structure is connected to an external circuit through the source 207.
It should be noted that, after the step S306, a capping dielectric layer 210 is further formed on the substrate 201, and the capping dielectric layer 210 covers the source 207.
Specifically, the capping dielectric layer 210 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like; the blanket dielectric layer 210 serves as a protective layer for the source 207.
In step S307, a drain 208 is formed on the lower surface of the substrate 201, as shown in fig. 13.
Specifically, referring to fig. 13, an electrode is extracted from a doped substrate 2011 doped with the first conductive type to serve as a drain 208, and the semiconductor device structure is connected to the outside through the drain 208.
The source 207 and the drain 208 may include, but are not limited to, metal electrodes.
As can be known from the semiconductor device structure and the manufacturing method thereof, in the semiconductor device structure, the thickness of the shielding gate 203 is smaller than half of the width of the gate trench, a gap is formed in the shielding gate 203, and the shielding gate 203 has a smaller cross-sectional area, so that the capacitance between the source 207 and the drain 208 in the semiconductor device structure can be significantly reduced, and further, the switching loss is reduced, thereby improving the efficiency of the semiconductor device structure.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A semiconductor device structure, comprising:
a substrate having a gate trench therein;
the liner layer is at least positioned on the side wall and the bottom of the grid groove;
a shield gate on sidewalls of the liner layer facing into the gate trench with a gap therebetween; the upper surface of the shielding grid is lower than the top of the grid groove;
the insulating medium layer is filled in the gap and covers the upper surface of the shielding grid;
the polysilicon grid is positioned in the grid groove and positioned on the upper surface of the insulating medium layer;
the source regions are positioned in the substrate and positioned on two opposite sides of the grid groove; the source region is electrically connected with the shielding grid;
the source electrode is positioned on the upper surface of the substrate and is in contact with the source region;
and the drain electrode is positioned on the lower surface of the substrate.
2. The semiconductor device structure of claim 1, wherein the substrate comprises:
a doped substrate of a first conductivity type; the drain electrode is positioned on the lower surface of the doped substrate of the first conduction type;
the epitaxial layer is positioned on the upper surface of the doped substrate, and a drift region of a first conduction type is formed in the epitaxial layer;
a body region of a second conductivity type located within the drift region of the first conductivity type;
the source region is located on the body region of the second conductivity type.
3. The semiconductor device structure of claim 2, wherein the doped substrate of the first conductivity type comprises a silicon substrate, and the liner layer comprises a silicon oxide layer; the shield grid comprises a polysilicon shield grid; the insulating medium layer comprises a silicon oxide layer.
4. The semiconductor device structure of claim 2, wherein the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.
5. The semiconductor device structure of any one of claims 1 to 4, wherein the shield gate has a thickness of 1/4 to 1/3 of the gate trench width.
6. A method for fabricating a semiconductor device structure, comprising:
providing a substrate, and forming a gate trench in the substrate;
forming a liner layer on the side wall and the bottom of the gate groove;
forming a shielding grid on the side wall of the liner layer facing the inside of the grid groove, and forming an insulating medium layer; the shielding grid is provided with a gap towards the side wall in the grid groove; the upper surface of the shielding grid is lower than the top of the grid groove; the insulating medium layer fills the gap and covers the upper surface of the shielding grid;
forming a polysilicon gate in the gate trench;
forming source regions in the substrate, wherein the source regions are positioned on two opposite sides of the grid groove and are electrically connected with the shielding grid;
forming a source electrode on the upper surface of the substrate, wherein the source electrode is in contact with the source region;
and forming a drain electrode on the lower surface of the substrate.
7. The method of claim 6, wherein the providing a substrate and forming a gate trench in the substrate comprises:
providing a doped substrate of a first conductivity type;
generating an epitaxial layer on the upper surface of the doped substrate of the first conductivity type;
a drift region of a first conductive type is formed in the epitaxial layer;
and forming the gate trench in the drift region of the first conductivity type.
8. The method of claim 7, wherein the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.
9. The method of claim 6, wherein forming a shield gate on the sidewall of the gate trench and forming an insulating dielectric layer comprises:
forming a shielding grid material layer on the surface of the liner layer;
removing the shielding grid electrode material layer positioned on the upper surface of the liner layer and at the bottom of the grid electrode groove, etching back the shielding grid electrode material layer positioned in the grid electrode groove, and keeping the upper surface of the shielding grid electrode material layer lower than the top of the grid electrode groove;
forming an insulating medium material layer, wherein the insulating medium material layer fills the gate groove and covers the surface of the liner layer;
and removing the insulating dielectric material layer on the substrate, etching back the insulating dielectric material layer in the gate trench and reserving the shielding gate material layer to obtain the insulating dielectric layer and the shielding gate.
10. The method for manufacturing a semiconductor device structure according to any one of claims 6 to 9, wherein the thickness of the shield gate is 1/4 to 1/3 of the width of the gate trench.
CN202211030210.6A 2022-08-26 2022-08-26 Semiconductor device structure and preparation method thereof Pending CN115347038A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497567A (en) * 2023-12-27 2024-02-02 天狼芯半导体(成都)有限公司 SGTMOS device, preparation method thereof and chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497567A (en) * 2023-12-27 2024-02-02 天狼芯半导体(成都)有限公司 SGTMOS device, preparation method thereof and chip
CN117497567B (en) * 2023-12-27 2024-04-19 天狼芯半导体(成都)有限公司 SGTMOS device, preparation method thereof and chip

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