CN114068680A - Split-gate MOS device and preparation method thereof - Google Patents

Split-gate MOS device and preparation method thereof Download PDF

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CN114068680A
CN114068680A CN202111551968.XA CN202111551968A CN114068680A CN 114068680 A CN114068680 A CN 114068680A CN 202111551968 A CN202111551968 A CN 202111551968A CN 114068680 A CN114068680 A CN 114068680A
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epitaxial layer
layer
doping concentration
gate
conductivity type
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毛昊源
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Wuxi Jierui Microelectronics Co ltd
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Wuxi Jierui Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The invention relates to the technical field of semiconductors and discloses a split-gate MOS device and a preparation method thereof, wherein the split-gate MOS device comprises a substrate, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer of a first conduction type are sequentially arranged on the substrate from bottom to top, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, the doping concentration of the second epitaxial layer is greater than that of the third epitaxial layer, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer form a drift region of the split-gate MOS device, the doping concentration of the second epitaxial layer is respectively greater than that of the first epitaxial layer and that of the third epitaxial layer, the second epitaxial layer with high doping concentration on the first side can enhance the electric field modulation effect of the drift region, and the withstand voltage of the split-gate MOS device is increased; the second aspect can avoid electric field lines from accumulating on two sides of the bottom of the groove, and prevent the split gate MOS device from being broken down on two sides of the bottom of the groove in advance when the split gate MOS device is in voltage resistance; the third aspect reduces the on-resistance of the device.

Description

Split-gate MOS device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a split gate MOS device and a preparation method thereof.
Background
In the conventional trench MOSFET structure, the gate and drain regions are separated only by the gate oxide, so the conventional trench MOSFET has a limited application due to high switching loss caused by high gate-drain capacitance.
In the development of MOSFETs, Split Gate (SGT) devices reduce switching losses by adding a source electrode between the gate and drain. The trench of the split-gate structure has two parts: the upper electrode is the control gate electrode and the lower electrode is the shielded gate source electrode, connected to the source electrode by a separate contact, corresponding to a field plate extending into the device to balance the charge in the drift region. Most of the existing split gate devices are formed by growing one or two epitaxial layers on a substrate and then manufacturing MOS devices on one or two epitaxial layers, although performance parameters of the existing split gate devices are improved compared with those of the existing traditional groove type MOSFET, parameters of the devices such as voltage resistance, breakdown resistance and integral on resistance can not meet the use requirements of some occasions.
Disclosure of Invention
In view of the defects of the background art, the invention provides a split-gate MOS device and a preparation method thereof, which are used for improving the voltage endurance and breakdown prevention of the split-gate MOS device and reducing the on-resistance of the split-gate MOS device.
In order to solve the technical problem, a first aspect of the present invention provides a split-gate MOS device, which includes a substrate, where a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer of a first conductivity type are sequentially disposed on the substrate from bottom to top, a doping concentration of the second epitaxial layer is greater than a doping concentration of the first epitaxial layer, and a doping concentration of the second epitaxial layer is greater than a doping concentration of the third epitaxial layer.
In one embodiment of the first aspect of the present invention, the doping concentration of the first epitaxial layer is greater than the doping concentration of the third epitaxial layer.
In a certain implementation manner of the first aspect of the present invention, a first graded layer of the first conductivity type is disposed between the first epitaxial layer and the second epitaxial layer, a doping concentration distribution of the first graded layer is gradually decreased from the bottom of the second epitaxial layer to the top of the first epitaxial layer, a second graded layer of the first conductivity type is disposed between the second epitaxial layer and the third epitaxial layer, and a doping concentration distribution of the second graded layer is gradually increased from the bottom of the third epitaxial layer to the top of the second epitaxial layer.
In one embodiment of the first aspect of the present invention, a doping concentration of a bottom portion of the first graded layer is greater than a doping concentration of the first epitaxial layer, and a doping concentration of a top portion of the first graded layer is less than a doping concentration of the second epitaxial layer; the doping concentration of the bottom of the second gradient layer is slightly lower than that of the second epitaxial layer, and the doping concentration of the top of the second gradient layer is greater than that of the third epitaxial layer.
In a certain implementation manner of the first aspect of the present invention, a body region of the second conductivity type is disposed on the third epitaxial layer, a trench is formed downward at the top of the body region, and the bottom of the trench extends downward into the first epitaxial layer; a gate oxide layer is arranged in the groove, the top of the gate oxide layer is flush with the top of the body region, and a shielding gate source electrode and a control gate electrode are arranged in the gate oxide layer; a first conductive type source region and a second conductive type source region are arranged at the top of the body region at two sides of the groove; the field oxide layer is arranged on the body region and the gate oxide layer, the insulating medium layer is arranged on the field oxide layer, the metal layer is arranged on the insulating medium layer, and the contact hole penetrates through the field oxide layer and the insulating medium layer to enable the first conduction type source region to be electrically connected with the metal layer.
In one embodiment of the first aspect of the present invention, the control gate electrode includes a left control gate electrode and a right control gate electrode, and the left control gate electrode and the right control gate electrode are respectively located on both sides of the shielding gate source electrode.
In one embodiment of the first aspect of the present invention, when the first conductivity type is P-type, the second conductivity type is N-type; when the first conductive type is an N type, the second conductive type is a P type.
In a second aspect, the present invention further provides a method for manufacturing a split-gate MOS device, including the following steps:
s1: selecting a substrate, and growing a first epitaxial layer with a first conductivity type and a first doping concentration on the substrate;
s2: forming a first graded layer of the first conductivity type with doping concentration increasing non-uniformly from bottom to top on the upper surface of the first epitaxial layer by one or more times of first conductivity type impurity injection and annealing;
s3: growing a second epitaxial layer of the first conductivity type and with a doping concentration of a second doping concentration on the first graded layer;
s4: forming a second gradient layer of the first conductive type with the doping concentration decreasing from bottom to top in a non-uniform mode by implanting small-dose impurities of the second conductive type into the upper surface of the second epitaxial layer for one time or multiple times and annealing;
s5, growing a third epitaxial layer of the first conductivity type and with a third doping concentration on the second gradient layer, wherein the second doping concentration is greater than the first doping concentration, and the first doping concentration is greater than the third doping concentration;
s6: forming a body region of the second conductivity type on the upper surface of the third epitaxial layer by implanting impurities of the second conductivity type and annealing;
s7: etching a trench down through an etching process over the body region of the second conductivity type, the bottom of the trench extending down into the first epitaxial layer;
s8: depositing a gate oxide layer on the inner wall of the trench and the surface of the body region of the second conductivity type;
s9: depositing polycrystalline silicon in a shielding gate trench area between the gate oxide layers in the trench to manufacture a shielding gate source electrode;
s10, etching the source electrode back to enable the top of the source electrode to be below the upper surface of the second conduction type body region, and growing an oxide layer to protect the shielding gate source electrode; then etching to remove the oxide layer above the body region of the second conductivity type and forming a left control gate groove and a right control gate groove by dry etching, wherein the left control gate groove and the right control gate groove are respectively arranged at the left side and the right side of the source electrode of the shielding gate, and the bottoms of the left control gate groove and the right control gate groove are flush with the lower surface of the body region of the second conductivity type;
s11: depositing polycrystalline silicon in the left control gate groove and the right control gate groove to form a left control gate electrode and a right control gate electrode; then growing a field oxide layer on the surfaces of the second conductive type body region and the groove;
s12: forming a first conductive type source region and a second conductive type source region on the body regions at two sides of the groove respectively in an injection mode;
s13: growing an insulating medium layer on the field oxide layer;
s14: and etching contact holes downwards in the insulating medium layer and in the regions corresponding to the first conductive source regions on the two sides of the groove respectively, and depositing metal layers in the contact holes and on the insulating medium layer.
In one embodiment of the second aspect of the present invention, the impurity concentration profile of the first graded layer is controlled by one or more implantations, the impurity concentration profile of the first graded layer gradually decreasing from the bottom of the second epitaxial layer to the top of the first epitaxial layer; and controlling the impurity concentration distribution of the second gradient layer by one or more times of injection, wherein the impurity concentration distribution of the second gradient layer is gradually increased from the bottom of the third epitaxial layer to the top of the second epitaxial layer.
In one embodiment of the second aspect of the present invention, in step S7, after the trench is etched, an oxide layer is formed on the inner wall surface of the trench by a thermal oxidation process, and then the oxide layer is etched to smooth the bottom corner of the trench.
In one embodiment of the second aspect of the present invention, the doping concentration of the bottom of the first graded layer is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the top of the first graded layer is less than the doping concentration of the second epitaxial layer; the doping concentration of the bottom of the second gradient layer is slightly lower than that of the second epitaxial layer, and the doping concentration of the top of the second gradient layer is greater than that of the third epitaxial layer.
Compared with the prior art, the invention has the beneficial effects that: in the structure of the split-gate MOS device, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer form a drift region of the split-gate MOS device, and the second epitaxial layer with high doping concentration on the first side can enhance the electric field modulation effect of the drift region and increase the withstand voltage of the split-gate MOS device by setting the doping concentration of the second epitaxial layer to be greater than that of the first epitaxial layer and setting the doping concentration of the first epitaxial layer to be greater than that of the third epitaxial layer; the second aspect can avoid electric field lines from accumulating on two sides of the bottom of the groove, so that breakdown of the split gate MOS device on two sides of the bottom of the groove in advance is prevented when the split gate MOS device is in voltage resistance, and the reliability of the device is improved; the third aspect reduces the overall resistivity of the drift region.
In addition, the first gradient layer and the second gradient layer can enhance the electric field modulation of the drift region, further enable the field intensity of the drift region to be uniformly distributed, and further reduce the on-resistance of the device.
In addition, because the concentration of the third epitaxial layer is low, an obvious concentration step can be formed with the second epitaxial layer, and the electric field modulation capability of the second epitaxial layer is enhanced; meanwhile, the third epitaxial layer is connected with the body region of the device, and due to the problems of inevitable surface impurity pollution, polycrystalline silicon gate backfill quality and the like in the process, the MOSFET with the traditional structure is easy to break down at the position, and the third epitaxial layer with lower doping concentration can effectively avoid the point, and the junction terminal design at the edge of the device is effectively simplified.
The last experiments show that the on-resistance of the device of the invention can be reduced by 30-50% compared with the traditional structure under the same BV, and the figure of merit FOM (Ron QCD) can be reduced by about 30%.
Drawings
FIG. 1 is a schematic structural diagram of a first epitaxial layer formed on a substrate according to an embodiment;
FIG. 2 is a schematic structural diagram illustrating a first graded layer formed on the structure of FIG. 1 in accordance with an embodiment;
FIG. 3 is a schematic diagram illustrating a second epitaxial layer formed on the structure of FIG. 2 according to an exemplary embodiment;
FIG. 4 is a schematic structural diagram illustrating a second graded layer formed on the structure of FIG. 3 in accordance with an embodiment;
FIG. 5 is a schematic structural diagram illustrating a third epitaxial layer formed on the structure of FIG. 4 in accordance with an embodiment;
FIG. 6 is a schematic diagram illustrating the fabrication of a body region over the structure of FIG. 5 in accordance with an embodiment;
FIG. 7 is a schematic diagram illustrating a trench formed in the structure of FIG. 6 according to an embodiment;
FIG. 8 is a schematic structural diagram of depositing a gate oxide layer on the structure of FIG. 7 in an embodiment;
FIG. 9 is a schematic diagram illustrating a source electrode fabricated on the structure of FIG. 8 in accordance with an embodiment;
FIG. 10 is a schematic diagram of an embodiment of a structure for forming left and right control gate electrode trenches on the structure of FIG. 9;
FIG. 11 is a schematic structural diagram of a left control gate electrode and a right control gate electrode fabricated on the structure of FIG. 10 in an embodiment;
fig. 12 is a schematic structural diagram illustrating the fabrication of first to fourth source regions on the structure of fig. 11 in accordance with an embodiment;
FIG. 13 is a schematic diagram illustrating an embodiment of a dielectric layer formed on the structure of FIG. 12;
FIG. 14 is a schematic diagram illustrating a metal layer formed on the structure of FIG. 13 according to an embodiment;
FIG. 15 is a schematic structural diagram of a split-gate MOS device without a graded layer in an embodiment;
fig. 16 is a schematic doping concentration diagram of the first epitaxial layer, the first graded layer, the second epitaxial layer, the second graded layer and the third epitaxial layer in the embodiment;
fig. 17 is a diagram illustrating the electric field distribution of the drift region of the split-gate MOS device with the second structure in the embodiment and the conventional single-layer epitaxial and double-layer epitaxial split-gate MOS devices.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in fig. 15, a split-gate MOS device includes a substrate 1, a first epitaxial layer 2, a second epitaxial layer 4, and a third epitaxial layer 6 of a first conductivity type are sequentially disposed on the substrate 1 from bottom to top, a doping concentration of the second epitaxial layer 4 is greater than a doping concentration of the first epitaxial layer 2, and a doping concentration of the second epitaxial layer 4 is greater than a doping concentration of the third epitaxial layer 6.
Specifically, in the present embodiment, the doping concentration of the first epitaxial layer 2 is greater than the doping concentration of the third epitaxial layer 6.
In fig. 15, a body region 7 of the second conductivity type is disposed on the third epitaxial layer 6, a trench 8 is disposed downward at the top of the body region 7, and the bottom of the trench 8 extends downward into the first epitaxial layer 2; a gate oxide layer 9 is arranged in the trench 8, the top of the gate oxide layer 9 is flush with the top of the body region 7, a shielding gate source electrode 11 and a control gate electrode are arranged in the gate oxide layer 9, and the gate oxide layer 9 is used for isolating and protecting the control gate electrode and the shielding gate source electrode; a first conductive type source region and a second conductive type source region are arranged on the top of the body region 7 at two sides of the trench 8, and in fig. 15, the first conductive type source region comprises a source region 16 and a source region 18, and the second conductive type source region comprises a source region 17 and a source region 19; the body region 7 and the gate oxide layer 9 are provided with field oxide layers 22, the field oxide layers 22 are provided with insulating dielectric layers 20, the insulating dielectric layers 20 are provided with metal layers 21, and contact holes penetrate through the field oxide layers 22 and the insulating dielectric layers 20 to enable the first conduction type source regions to be electrically connected with the metal layers 21.
Specifically, in fig. 15, the control gate electrodes include a left control gate electrode 14 and a right control gate electrode 15, and the left control gate electrode 14 and the right control gate electrode 15 are respectively on both sides of the shield gate source electrode 11.
Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type; different types of shielding grid power MOSFET devices can be obtained by selecting different conductive types; when the first conduction type is an N type and the second conduction type is a P type, the obtained shielding gate power MOSFET device is an N type device; when the first conductivity type is P type and the second conductivity type is N type, the obtained shielding gate power MOSFET device is a P type device.
Illustratively, the specification parameters of the present invention are that the thickness of the first epitaxial layer 2 is 3um, the thickness of the second epitaxial layer 4 is 1.5um, and the thickness of the third epitaxial layer 6 is 2 um.
In the second structure of the split-gate MOS device in this embodiment, a first graded layer 3 of the first conductivity type is disposed between the first epitaxial layer 2 and the second epitaxial layer 4, the doping concentration distribution of the first graded layer 3 gradually decreases from the bottom of the second epitaxial layer 4 to the top of the first epitaxial layer 2, a second graded layer 5 of the first conductivity type is disposed between the second epitaxial layer 4 and the third epitaxial layer 6, the doping concentration distribution of the second graded layer 5 gradually increases from the bottom of the third epitaxial layer 6 to the top of the second epitaxial layer 4, and a schematic structural diagram of the split-gate device of the second structure is shown in fig. 14.
In one embodiment, the doping concentration of the bottom of the first graded layer 3 is higher than that of the first epitaxial layer 2, and the doping concentration of the top of the first graded layer 3 is lower than that of the second epitaxial layer 4; the doping concentration of the bottom of the second graded layer 5 is less than that of the second epitaxial layer, and the doping concentration of the top of the second graded layer 5 is greater than that of the third epitaxial layer 6. Fig. 16 shows a schematic diagram of the doping concentration variation of the first epitaxial layer 2, the first graded layer 3, the second epitaxial layer 4, the second graded layer 5 and the third epitaxial layer 6, in fig. 16, L1 corresponds to the first epitaxial layer 2, a1 corresponds to the first graded layer 3, L2 corresponds to the second epitaxial layer 4, a2 corresponds to the second graded layer 5, and L3 corresponds to the third epitaxial layer 6.
Illustratively, in the split-gate MOS device of the second structure, the thickness of the first epitaxial layer 2 is 3um, the thickness of the first graded layer 3 is 1um, the thickness of the second epitaxial layer 4 is 1.5um, the thickness of the second graded layer 5 is 1um, the thickness of the third epitaxial layer 6 is 2um, the doping concentration of the first epitaxial layer 2 is 7e15cm ^ -3, the doping concentration of the second epitaxial layer 4 is 4e16cm ^ -3, the doping thickness of the third epitaxial layer 6 is 5e15cm ^ -3, the doping concentration of the first graded layer 3 is non-uniformly increased between 7e15cm ^ -3 and 4e16cm ^ -3 from bottom to top, and the doping concentration of the second graded layer 5 is non-uniformly decreased between 4e16cm ^ -3 and 5e15cm ^ -3 from bottom to top.
The first epitaxial layer 2, the first graded layer 3, the second epitaxial layer 4, the second graded layer 5 and the third epitaxial layer 6 are used as drift regions of the split-gate device. When the split-gate MOS device is actually manufactured, the doping concentration of the second epitaxial layer 4 is respectively greater than the doping concentration of the first epitaxial layer 2 and the doping concentration of the third epitaxial layer 6, so that the electric field modulation effect of the drift region can be enhanced. As shown in fig. 17, compared with the drift region formed by the conventional single-layer epitaxy or double-layer epitaxy, the MOSFET having the second epitaxial layer 4 doped with high concentration may form a peak of electric field strength at the boundary between the second epitaxial layer 4 and the third epitaxial layer 6, that is, the abscissa in fig. 17 forms a peak of electric field strength in the interval corresponding to 3um to 4.5um, so that the electric field lines in the drift region inside the entire device are distributed more uniformly, and the EF integral of the largest area along the depth direction of the cell can be obtained.
For the split-gate MOS device in the present invention, the electric field modulation level of the second epitaxial layer 4 in the drift region is gradually increased and reaches an optimal level as the doping concentration is increased. Too high doping can break the charge balance of the drift region resulting in a sharp BV drop for split gate MOS devices. The optimum doping concentration of the second epitaxial layer 4 can thus be modulated according to the thickness of the second epitaxial layer 4 and the BV requirements of the split-gate MOS device, but it is noted that it is necessary to have the doping concentration of the second epitaxial layer 4 greater than the doping concentration of the first epitaxial layer 2 and the doping concentration of the third epitaxial layer 6, respectively, preferably the doping concentration of the first epitaxial layer 2 is greater than the doping concentration of the third epitaxial layer 6.
In addition, the doping concentration of the second epitaxial layer 4 is larger than that of the first epitaxial layer 2, so that electric field lines can be prevented from being accumulated on two sides of the bottom of the groove 8, the split gate MOS device can be prevented from being broken down on two sides of the bottom of the groove in advance when the split gate MOS device is resistant to voltage, the reliability of the device is improved, and the appearance difficulty of the groove caused by the micro reduction of the size of the shielding gate in the process is reduced.
In addition, the second epitaxial layer 4 doped with high concentration also reduces the overall resistivity of the drift region of the device, so that the on-resistance of the device can be effectively reduced. In addition, the resistivity of the first epitaxial layer 2 can be adjusted more flexibly by setting the doping concentration of the second epitaxial layer 4, and the on-resistance of the device is further reduced.
The doping concentration of the third epitaxial layer 6 is relatively lowest, and an obvious concentration step is formed with the second epitaxial layer 4, so that the electric field modulation capability of the second epitaxial layer 4 is enhanced. The third epitaxial layer 6 is connected with the body region 7 of the device, and due to the problems of inevitable surface impurity pollution, polycrystalline silicon gate backfill quality and the like in the process, the MOSFET with the traditional structure is easy to break down at the position, and the third epitaxial layer 6 with lower doping concentration can effectively avoid the point and effectively simplify the junction terminal design at the edge of the device.
In addition, the first gradient layer 3 with the gradually changed doping concentration is arranged between the first epitaxial layer 2 and the second epitaxial layer 4, and the second gradient layer 5 with the gradually changed doping concentration is arranged between the second epitaxial layer 4 and the third epitaxial layer 6, so that the electric field distribution in the drift region can be better modulated, the electric field intensity of the electric field in the drift region along the longitudinal distribution of the trench 8 is more even, and meanwhile, the overall resistivity of the device in the drift region can be further reduced due to the introduction of the first gradient layer 3 and the second gradient layer 5.
According to TCAD simulation, the on-resistance of the invention can be reduced by 30-50% compared with the on-resistance of the traditional structure under the same BV, and the figure of merit FOM (Ron QCD) can be reduced by about 30%.
For the split-gate MOS device in fig. 15, the thicknesses and doping concentrations of the first epitaxial layer 2, the second epitaxial layer 4 and the third epitaxial layer 6 may be referred to parameters in the split-gate MOS device of the second structure.
In a certain embodiment, in order to obtain a split-gate MOS device with a target breakdown voltage value or a target on-resistance, the thicknesses and doping concentrations of the first epitaxial layer 2, the first graded layer 3, the second epitaxial layer 4, the second graded layer 5, and the third epitaxial layer 6 may be adjusted according to design requirements, but the doping concentration of the second epitaxial layer 4 needs to be greater than the doping concentration of the first epitaxial layer 2, and the doping concentration of the first epitaxial layer 2 needs to be greater than the doping concentration of the third epitaxial layer 6.
As shown in fig. 16, a method for manufacturing a split-gate MOS device includes the following steps:
s1: selecting a substrate 1, and growing a first epitaxial layer 2 with a first conductivity type and a first doping concentration on the substrate 1; the schematic structural diagram of the device after step S1 is executed is shown in fig. 1;
in practical fabrication, the first doping concentration can be 7e15cm ^ -3, and the thickness of the first epitaxial layer 2 is 4 um; in practical use, the first epitaxial layer 2 can be grown on the substrate 1 in an epitaxial mode, and in order to ensure the flatness of the surface of the first epitaxial layer 2, the top surface of the first epitaxial layer 2 can be subjected to CMP (chemical mechanical polishing) planarization after the growth of the first epitaxial layer 2 is finished;
s2: forming a first graded layer 3 of the first conductivity type with doping concentration increasing non-uniformly from bottom to top on the upper surface of the first epitaxial layer 2 by one or more times of first conductivity type impurity injection and annealing; the schematic structural diagram of the device after step S2 is executed is shown in fig. 2;
in actual manufacturing, by implanting impurities multiple times and adjusting the dose and energy of each implantation, the concentration of each depth of the first graded layer 3 can be controlled, the concentration gradient of the first graded layer 3 can be adjusted better, and in addition, by implanting multiple times, the doping concentration of the upper surface of the first graded layer 3 can be made to approach the doping concentration of the second epitaxial layer manufactured in step S3; in addition, the thickness of the first graded layer 3 can be controlled by controlling the annealing time, wherein the thickness of the first graded layer 3 can be 1 um;
in this embodiment, the impurity distribution of post-implantation annealing is gaussian distribution, and the impurity concentration distribution of the first graded layer 3 formed by one or more times of implantation is the final impurity distribution formed by superimposing the gaussian distributions of different peak values regulated and controlled according to the adjustment of the implantation dose and the implantation times. That is to say the impurity profile of the first graded layer 3 is controllably adjustable.
S3: growing a second epitaxial layer 4 of the first conductivity type and having a doping concentration of a second doping concentration on the first graded layer 3; fig. 3 is a schematic structural diagram of the device after step S3 is executed;
in actual fabrication, the second doping concentration may be 4e16cm ^ -3, and the thickness of the second epitaxial layer 4 may be 2.5 um; in actual manufacturing, the second epitaxial layer 4 can be grown on the first graded layer 3 in an epitaxial mode, and in order to ensure the flatness of the surface of the second epitaxial layer 4, the top surface of the second epitaxial layer 4 can be subjected to CMP planarization after the growth of the second epitaxial layer 4 is completed;
s4: forming a second graded layer 5 of the first conductivity type with the doping concentration decreasing non-uniformly from bottom to top on the upper surface of the second epitaxial layer 4 by one or more times of injecting impurities of the second conductivity type and annealing; fig. 4 shows a schematic structural diagram of the device after step S4 is executed;
in actual manufacturing, by implanting impurities multiple times and adjusting the dose and energy of each implantation, the concentration of each depth of the second graded layer 5 can be controlled, the concentration gradient of the second graded layer 5 can be adjusted better, and in addition, by implanting multiple times, the doping concentration of the upper surface of the second graded layer 5 can be made to approach the doping concentration of the third epitaxial layer 6 manufactured in step S5; in addition, the thickness of the second graded layer 5 can be controlled by controlling the annealing time, wherein the thickness of the second graded layer 5 can be 1 um;
in this embodiment, the impurity distribution of post-implantation annealing is gaussian distribution, and the impurity concentration distribution of the second graded layer 5 formed by one or more times of implantation is the final impurity distribution formed by superimposing the gaussian distributions of different peak values regulated and controlled according to the adjustment of the implantation dose and the implantation times. That is to say the impurity profile of the second graded layer 5 is controllably adjustable.
S5, growing a third epitaxial layer 6 with the first conductivity type and the third doping concentration on the second gradient layer 5, wherein the second doping concentration is greater than the first doping concentration, and the first doping concentration is greater than the third doping concentration; fig. 5 shows a schematic structural diagram of the device after step S5 is executed;
in actual manufacturing, the third doping concentration can be 5e15cm ^ -3, and the thickness of the third epitaxial layer 6 can be 3 um; in actual manufacturing, the third epitaxial layer 6 can be grown on the second graded layer 5 in an epitaxial mode, and in order to ensure the flatness of the surface of the third epitaxial layer 6, after the growth of the third epitaxial layer 6 is finished, the top surface of the third epitaxial layer 6 can be subjected to CMP (chemical mechanical polishing) planarization treatment;
s6: forming a body region 7 of the second conductivity type on the upper surface of the third epitaxial layer 6 by implanting impurities of the second conductivity type and annealing; fig. 5 shows a schematic structural diagram of the device after step S6 is executed;
in actual fabrication, the thickness of body region 7 may be 1um, and the concentration of body region 7 may be 1.6e18cm ^ -3;
s7: etching a trench 8 down through an etching process over the body region 7 of the second conductivity type, the bottom of the trench 8 extending down into the first epitaxial layer 2; the schematic structure diagram after step S7 is shown in fig. 7;
in actual fabrication, a trench 8 may be etched down over the body region 7 using dry etching; in addition, after the groove 8 is etched, an oxide layer is formed on the inner wall surface of the groove 8 through a thermal oxidation process, and then the oxide layer is etched to enable the bottom corner of the groove 8 to be smooth;
s8: depositing a gate oxide layer 9 on the inner walls of the trenches 8 and the surface of the body region 7 of the second conductivity type; the schematic structural diagram of the device after step S8 is executed is shown in fig. 8, and as can be obtained from fig. 8, a shielding gate trench 10 is present between the gate oxide layers 9 on the inner wall of the trench 8;
s9: depositing polysilicon in the shield gate trench 10 between the gate oxide layers 9 in the trench 8 to manufacture a shield gate source electrode 11; fig. 9 shows a schematic structural diagram of the device after step S9 is executed;
s10, etching back the shield gate source electrode 11 to make the top of the shield gate source electrode 11 under the upper surface of the body region 7 of the second conduction type, and growing an oxide layer to protect the shield gate source electrode 11; then etching to remove an oxide layer above the body region 7 of the second conductivity type and forming a left control gate trench 12 and a right control gate trench 13 through dry etching, wherein the left control gate trench 12 and the right control gate trench 13 are respectively arranged at the left side and the right side of the shielding gate source electrode 11, and the bottoms of the left control gate trench 12 and the right control gate trench 13 are flush with the lower surface of the body region 7 of the second conductivity type; fig. 10 shows a schematic structural diagram of the device after step S10 is executed;
in step S10, in order to ensure the shape and quality of the filling of the shield gate source electrode 11, the shield gate source electrode 11 needs to be etched back first, after the back etching of the shield gate source electrode 11 is completed, the left control gate electrode 14 and the right control gate electrode 15 need to be fabricated in the gate oxide layer 9, so that the left control gate trench 12 and the right control gate trench 13 need to be etched in the gate oxide layer 9, and in order to protect the shield gate source electrode 11 when the left control gate trench 12 and the right control gate trench 13 are etched, an oxide layer needs to be grown below the upper surface of the body region 7 of the second conductivity type; after the oxide layer grows, defining the positions of the left control gate trench 12 and the right control gate trench 13 through exposure and development processes, and etching the left control gate trench 12 and the right control gate trench 13 in the gate oxide layer 9 through an etching process;
s11: depositing polysilicon in the left control gate trench 12 and the right control gate trench 13 to form a left control gate electrode 14 and a right control gate electrode 15; then growing a field oxide layer on the surfaces of the body region 7 of the second conduction type and the trench 8; fig. 11 shows a schematic structural diagram of the device after step S11 is executed;
s12: forming a first conductive type source region and a second conductive type source region on the body regions at two sides of the trench 8 respectively in an injection mode; a schematic structural diagram of a device which performs step S12 is shown in fig. 12; in fig. 12, the first conductive-type source region includes a source region 16 and a source region 18, and the second conductive-type source region includes a source region 17 and a source region 19;
s13: growing an insulating dielectric layer 20 on the field oxide layer 22; fig. 13 shows a schematic structural diagram of the device after step S13 is executed;
s14: firstly, etching contact holes downwards in the insulating medium layer 20 and the areas corresponding to the first conductive type source regions on the two sides of the groove 8 respectively, and then depositing a metal layer 21 in the contact holes and on the insulating medium layer 20; fig. 14 shows a schematic structural diagram of the device after step S14 is executed; the split gate MOS device in fig. 14 is with a first graded layer 3 and a second graded layer 5; when the first graded layer 3 and the second graded layer 5 are not required for the split-gate MOS device, the steps S2 and S4 in the above steps S1 to S14 may be omitted.
In the preparation method of the present invention, when step S2 is executed, the doping concentration of the bottom of the first graded layer 3 is greater than the doping concentration of the first epitaxial layer 2, and the doping concentration of the top of the first graded layer 3 is less than the doping concentration of the second epitaxial layer 4; in step S4, the doping concentration of the bottom of the second graded layer 5 is less than the doping concentration of the second epitaxial layer 4, and the doping concentration of the top of the second graded layer 5 is greater than the doping concentration of the bottom of the third epitaxial layer 4.
In the preparation method of the invention, when the first conductive type is P type, the second conductive type is N type, and the split gate MOS device of the invention is NMOS; when the first conductivity type is N-type and the second conductivity type is P-type, the split-gate MOS device of the present invention is PMOS.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims (10)

1. The utility model provides a split gate MOS device, its characterized in that includes the substrate, from up being equipped with first epitaxial layer, second epitaxial layer and the third epitaxial layer of first conductivity type down on the substrate in proper order, the doping concentration of second epitaxial layer is greater than the doping concentration of first epitaxial layer, the doping concentration of second epitaxial layer is greater than the doping concentration of third epitaxial layer.
2. The split-gate MOS device of claim 1, wherein the first epitaxial layer has a doping concentration greater than the doping concentration of the third epitaxial layer.
3. The split-gate MOS device of claim 2, wherein a first graded layer with a gradually changing first conductivity type impurity concentration is disposed between the first epitaxial layer and the second epitaxial layer, the first graded layer has a doping concentration distribution that gradually decreases from the bottom of the second epitaxial layer to the top of the first epitaxial layer, a second graded layer with a gradually changing first conductivity type impurity concentration is disposed between the second epitaxial layer and the third epitaxial layer, and the second graded layer has a doping concentration distribution that gradually increases from the bottom of the third epitaxial layer to the top of the second epitaxial layer.
4. The split-gate MOS device as claimed in claim 1 or 3, wherein a body region of the second conductivity type is provided on the third epitaxial layer, a trench is provided downward at a top of the body region, and a bottom of the trench extends downward into the first epitaxial layer; a gate oxide layer is arranged in the groove, the top of the gate oxide layer is flush with the top of the body region, and a shielding gate source electrode and a control gate electrode are arranged in the gate oxide layer; a first conductive type source region and a second conductive type source region are arranged at the top of the body region at two sides of the groove; the field oxide layer is arranged on the body region and the gate oxide layer, the insulating medium layer is arranged on the field oxide layer, the metal layer is arranged on the insulating medium layer, and the contact hole penetrates through the field oxide layer and the insulating medium layer to enable the first conduction type source region to be electrically connected with the metal layer.
5. The split-gate MOS device of claim 4, wherein the control gate electrode comprises a left control gate electrode and a right control gate electrode, the left control gate electrode and the right control gate electrode being on respective sides of the shield gate source electrode.
6. The split-gate MOS device of claim 4, wherein when the first conductivity type is P-type, the second conductivity type is N-type; when the first conductive type is an N type, the second conductive type is a P type.
7. A preparation method of a split gate MOS device is characterized by comprising the following steps:
s1: selecting a substrate, and growing a first epitaxial layer with a first conductivity type and a first doping concentration on the substrate;
s2: forming a first graded layer of the first conductivity type with doping concentration increasing non-uniformly from bottom to top on the upper surface of the first epitaxial layer by one or more times of first conductivity type impurity injection and annealing;
s3: growing a second epitaxial layer of the first conductivity type and with a doping concentration of a second doping concentration on the first graded layer;
s4: forming a second gradient layer of the first conductive type with the doping concentration decreasing from bottom to top in a non-uniform mode by implanting small-dose impurities of the second conductive type into the upper surface of the second epitaxial layer for one time or multiple times and annealing;
s5, growing a third epitaxial layer of the first conductivity type and with a third doping concentration on the second gradient layer, wherein the second doping concentration is greater than the first doping concentration, and the first doping concentration is greater than the third doping concentration;
s6: forming a body region of the second conductivity type on the upper surface of the third epitaxial layer by implanting impurities of the second conductivity type and annealing;
s7: etching a trench down through an etching process over the body region of the second conductivity type, the bottom of the trench extending down into the first epitaxial layer;
s8: depositing a gate oxide layer on the inner wall of the trench and the surface of the body region of the second conductivity type;
s9: depositing polycrystalline silicon in a shielding gate trench area between the gate oxide layers in the trench to manufacture a shielding gate source electrode;
s10, etching back the shielding grid source electrode to enable the top of the shielding grid source electrode to grow an oxide layer below the upper surface of the second conductive type body region to protect the shielding grid source electrode; then etching to remove the oxide layer above the body region of the second conductivity type and forming a left control gate groove and a right control gate groove by dry etching, wherein the left control gate groove and the right control gate groove are respectively arranged at the left side and the right side of the source electrode of the shielding gate, and the bottoms of the left control gate groove and the right control gate groove are flush with the lower surface of the body region of the second conductivity type;
s11: depositing polycrystalline silicon in the left control gate groove and the right control gate groove to form a left control gate electrode and a right control gate electrode; then growing a field oxide layer on the surfaces of the second conductive type body region and the groove;
s12: forming a first conductive type source region and a second conductive type source region on the body regions at two sides of the groove respectively in an injection mode;
s13: growing an insulating medium layer on the field oxide layer;
s14: and etching contact holes downwards in the insulating medium layer and in the regions corresponding to the first conductive source regions on the two sides of the groove respectively, and depositing metal layers in the contact holes and on the insulating medium layer.
8. The method according to claim 7, wherein the impurity concentration profile of the first graded layer is controlled by one or more implantations, and the impurity concentration profile of the first graded layer gradually decreases from the bottom of the second epitaxial layer to the top of the first epitaxial layer; and controlling the impurity concentration distribution of the second gradient layer by one or more times of injection, wherein the impurity concentration distribution of the second gradient layer is gradually increased from the bottom of the third epitaxial layer to the top of the second epitaxial layer.
9. The method of claim 7, wherein in step S7, after the trench is etched, an oxide layer is formed on an inner wall surface of the trench by a thermal oxidation process, and then the oxide layer is etched to smooth a bottom corner of the trench.
10. The method for manufacturing a split-gate MOS device according to claim 7 or 8, wherein a doping concentration of a bottom portion of the first graded layer is greater than a doping concentration of the first epitaxial layer, and a doping concentration of a top portion of the first graded layer is less than a doping concentration of the second epitaxial layer; the doping concentration of the bottom of the second gradient layer is slightly lower than that of the second epitaxial layer, and the doping concentration of the top of the second gradient layer is greater than that of the third epitaxial layer.
CN202111551968.XA 2021-12-17 2021-12-17 Split-gate MOS device and preparation method thereof Pending CN114068680A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114582960A (en) * 2022-05-09 2022-06-03 南京微盟电子有限公司 Multi-time epitaxial shielded gate power device and manufacturing method thereof
CN114597130A (en) * 2022-04-02 2022-06-07 致瞻科技(上海)有限公司 Silicon carbide MOSFET device based on split gate and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114597130A (en) * 2022-04-02 2022-06-07 致瞻科技(上海)有限公司 Silicon carbide MOSFET device based on split gate and manufacturing method thereof
CN114597130B (en) * 2022-04-02 2022-12-27 致瞻科技(上海)有限公司 Silicon carbide MOSFET device based on split gate and manufacturing method thereof
CN114582960A (en) * 2022-05-09 2022-06-03 南京微盟电子有限公司 Multi-time epitaxial shielded gate power device and manufacturing method thereof
CN114582960B (en) * 2022-05-09 2022-07-26 南京微盟电子有限公司 Multi-time epitaxial shielded gate power device and manufacturing method thereof

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