CN111987166B - Method for manufacturing lateral double-diffused transistor - Google Patents
Method for manufacturing lateral double-diffused transistor Download PDFInfo
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- CN111987166B CN111987166B CN202010926432.0A CN202010926432A CN111987166B CN 111987166 B CN111987166 B CN 111987166B CN 202010926432 A CN202010926432 A CN 202010926432A CN 111987166 B CN111987166 B CN 111987166B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 238000002513 implantation Methods 0.000 claims description 95
- 238000005468 ion implantation Methods 0.000 claims description 78
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims 2
- 238000009826 distribution Methods 0.000 abstract description 16
- 230000008569 process Effects 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 description 11
- 230000005684 electric field Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- -1 HfSiN Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 235000014036 Castanea Nutrition 0.000 description 1
- 241001070941 Castanea Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003217 Ni3Si Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention relates to the technical field of semiconductor power devices, and provides a manufacturing method of a transverse double-diffusion transistor. The breakdown voltage of the device is improved, sufficient impurity doping concentration is guaranteed, so that the device has smaller on-resistance, the performance of the formed device is improved, a specially-made mask with a specific window design is prevented from being used for forming a linear variable doping drift region in the prior art, the manufacturing cost is saved, the linear distribution of the doping concentration of the drift region can be controlled by controlling the ion injection times and angles through a process, and the applicability of the manufacturing method is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a manufacturing method of a transverse double-diffusion transistor.
Background
An integrated high voltage Laterally Diffused Metal Oxide Semiconductor (LDMOS) device refers to a high voltage MOS having a lateral channel structure and a drift region, and the drain, gate and source of such a device are all located on the surface of a chip, which is the most critical integrated device in a lateral high voltage BCD (bipolar, Complementary Metal Oxide Semiconductor (CMOS) and DMOS) platform. In a High Voltage Interface Communications (HVIC), a High voltage LDMOS is generally used as a switching device, and for the switching device, how to achieve a High off-voltage resistance and a low on-resistance that meet application requirements is an ultimate goal of device structure optimization. On the premise of satisfying high blocking withstand voltage, a lower on-resistance means that a more efficient planar area utilization rate of the device can be obtained, which in turn means an improvement in performance and a reduction in cost.
However, there is an irreconcilable conflict between the two parameters of the blocking voltage resistance and the on-resistance. In general, a lightly doped and long drift region structure is required for realizing the high-voltage-withstanding LDMOS, and the lightly doped and long drift region can cause high drift region resistance, so that the on-state on-resistance is difficult to reduce. Currently, most of the LDMOS adopts an LDMOS structure with a Reduced surface field (resurf) technology and combines a field plate to realize compromise and optimization of high blocking withstand voltage and on-resistance.
In addition, in an article published in the journal of solid state electronics by chen ji in 1992, it is proposed to use a Variable Lateral Doping (VLD) structure to change the surface electric field distribution of the device, and theoretically calculate that the Doping concentration of the laterally varying drift region optimizes the relationship between the breakdown voltage and the specific on-resistance of the planar junction of the device. The VLD technology obtains a uniform surface electric field by optimizing the distribution of the drift region dopant amount or the linear variation of the concentration, but because the existing method for realizing the lateral variation doping in the process is to make a mask into a specific window and inject a certain dopant amount into the window to form the linear distribution of surface ions, the key point of the technology lies in the manufacture of the mask, thereby causing the application difficulty of the VLD technology.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a method for manufacturing a lateral double-diffused transistor, which can improve the performance of a formed device and save the manufacturing cost.
The invention provides a method for manufacturing a transverse double-diffused transistor, which comprises the following steps:
forming a drift region of a first doping type in an implantation region and an overlapping region between the implantation regions on the substrate by utilizing multiple times of ion implantation, wherein the doping concentration of the drift region is gradually reduced and changed towards two ends along the channel direction by the center of the overlapping region;
sequentially forming a gate oxide layer and a polysilicon layer on the substrate, and etching to form a gate structure arranged at intervals, wherein the gate structure defines a plurality of source regions and the drift region;
sequentially performing ion implantation on each source region to form a well region of a second doping type, wherein each gate structure is positioned between the well region and the drift region and is in contact with the well region and the drift region which are adjacent to the gate structure;
sequentially performing ion implantation in each well region to form at least one N-type region and one P-type region, and forming an N-type region in the central region of the overlapped region in the drift region by using ion implantation;
metal contacts are respectively formed on the source region, the grid structure and the drift region to correspondingly lead out a source electrode, a grid electrode and a drain electrode,
the transverse double-diffused transistor is formed in a structure that the central axis of the drift region is symmetrical left and right.
Preferably, before forming the drift region of the first doping type in the implantation region and the overlap region between the implantation regions on the substrate by using multiple ion implantations, the manufacturing method further comprises:
an epitaxial layer of a first doping type is formed on a substrate, and the drift region is formed on the epitaxial layer.
Preferably, the forming a drift region of the first doping type in the implantation region and the overlap region between the implantation regions on the substrate by multiple ion implantations includes:
performing self-aligned implantation in the vertical direction by using a patterned mask plate to form a first doping implantation region on the epitaxial layer;
multiplexing the patterned mask plate in the ion implantation for even times after the self-aligned implantation, and forming an overlapping region overlapped with the first doping implantation region in the first doping implantation region by adopting oblique implantation at a first angle;
multiplexing the patterned mask plate in each odd-numbered ion implantation after the even-numbered ion implantation, and performing oblique implantation at a second angle in the first doping implantation area to form an overlapped area overlapped with the first doping implantation area, so that the concentration of the first doping implantation area after the overlapping is symmetrically distributed by the central axis of the first doping implantation area;
the first doping injection region and the overlapping region overlapped with the first doping injection region form the drift region, and the doping concentration of the drift region is gradually reduced from the center of the overlapping region to two ends along the channel direction.
Preferably, the first angle used in the ion implantation of even number after the self-aligned implantation and the second angle used in the ion implantation of next odd number after the even number are complementary or equal, wherein the first angle and the second angle are both the included angle between the oblique ion implantation direction and the horizontal right direction.
Preferably, in the ion implantation of even number after the self-aligned implantation, the first angle used is changed in a gradient manner with the implantation sequence, and in the ion implantation of odd number after the self-aligned implantation, the second angle used is changed in a gradient manner with the implantation sequence.
Preferably, the forming of the gate structure spaced apart by etching, the gate structure defining a plurality of source regions and the drift region, includes:
sequentially etching the polysilicon layer and the gate oxide layer at the same position to form a first gate structure and a second gate structure arranged at intervals by superposing the polysilicon layer and the gate oxide layer in the reserved region,
the drift region is arranged between the first gate structure and the second gate structure, a first source region is defined on one side of the first gate structure far away from the drift region, and a second source region is defined on one side of the second gate structure far away from the drift region.
Preferably, the sequentially performing ion implantation in each of the aforementioned well regions to form at least one N-type region and one P-type region comprises:
sequentially performing ion implantation in the first source region to form a first P-type region and a first N-type region;
and sequentially performing ion implantation in the second source region to form a second P-type region and a second N-type region.
Preferably, the forming of metal contacts in the source region, the gate structure, and the drift region respectively to correspond to the extraction source electrode, the gate electrode, and the drain electrode includes:
respectively forming metal contacts on the first P-type region and the first N-type region and the second P-type region and the second N-type region, electrically connecting the metal contacts together, and correspondingly leading out the metal contacts to a source electrode;
respectively forming metal contacts on the upper surfaces of the first grid structure and the second grid structure, electrically connecting the metal contacts together, and correspondingly leading out the metal contacts to the grid electrodes;
and forming a metal contact on the N-type region formed in the central region of the overlapping region in the drift region, and correspondingly leading out the metal contact to the drain electrode.
Preferably, the substrate is a substrate of a second doping type.
Preferably, the first doping type is N-type, and the second doping type is P-type;
alternatively, the first doping type is P-type, and the second doping type is N-type.
The invention has the beneficial effects that: the invention provides a manufacturing method of a transverse double-diffusion transistor, which utilizes multiple times of ion implantation (oblique angle implantation) to form a drift region of a first doping type in an implantation region and an overlapping region between the implantation regions on a substrate, wherein the doping concentration of the drift region is distributed in a gradient manner (linear variable doping concentration) from the center of the overlapping region to two ends along a channel direction, so that a new electric field peak value is introduced into the surface of the drift region by the structure, the surface electric field distribution of the drift region is improved, and the formed transverse double-diffusion transistor is in a structure in which the central axis of the drift region is in bilateral symmetry. The breakdown voltage of the device is improved, and the sufficient N-type impurity doping concentration is ensured, so that the device is ensured to have smaller on-resistance, the formation of a linear variable doping drift region by utilizing a specially-made mask plate with a specific window design in the prior art is avoided, the manufacturing cost is saved, and the applicability of the process of the linear variable doping drift region is improved.
Meanwhile, the manufacturing method of the transverse double-diffusion transistor can control the linear distribution of the doping concentration of the drift region (the concentration of the drift region is gradually increased from the source end to the drain end) by controlling the frequency and the angle of ion implantation through a process, so that the structure ensures the requirement of the withstand voltage of the device, the surface doping concentration of the drift region is higher, the reduction of the on-resistance is facilitated, the breakdown voltage and the on-resistance of the device are simultaneously optimized, the electric field on the channel side of the device is reduced, the hot carrier effect is effectively inhibited, and the reliability of the device is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic cross-sectional view of a lateral double diffused transistor device according to an embodiment of the present invention;
fig. 2 is a flow chart illustrating a method of fabricating a lateral double diffused transistor device according to an embodiment of the present invention;
fig. 3 shows a flow diagram of sub-steps in a method of manufacturing the lateral double diffused transistor device shown in fig. 2 in forming an N-type drift region;
fig. 4 a-4 k illustrate schematic cross-sectional views of the method of fabricating the lateral double diffused transistor device shown in fig. 2, respectively, at various stages of forming the structure.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor, electrode layer may be formed of various conductive materials such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 is a schematic cross-sectional view of a lateral double diffused transistor device according to an embodiment of the present invention, which is an N-type lateral double diffused transistor as an example.
Referring to fig. 1, an embodiment of the present invention provides a lateral double-diffused transistor (LDMOS) device 100, where the LDMOS device 100 includes, in order from a P-type substrate 101 to the top: an N-type epitaxial layer 102, an N-type drift region 103 formed by multiple ion implantations at an implantation region on the N-type epitaxial layer 102 and an overlap region between the implantation regions, a plurality of P-type well regions arranged at intervals along a channel direction, and a plurality of gate structures (not shown) located between the P-type well regions at a substrate surface, wherein the plurality of P-type well regions at least include from left to right: the first P-well region 104 and the second P-well region 105, and the plurality of gate structures at least include, from left to right: a first gate structure and a second gate structure, each gate structure comprising a gate oxide layer 130 and a polysilicon layer 120 sequentially stacked on the substrate surface, wherein a first P-type region 106 and a first N-type region 107 are formed in the first P-type well region 104, a second N-type region 110 and a second P-type region 109 are formed in the second P-type well region 105, the doping concentration of the N-type drift region 103 varies in a gradient manner (linearly varying doping concentration) from the center of the overlap region to both ends along the channel direction, the first gate structure is located between the first P-type well region 104 and the N-type drift region 103 and is in contact with the adjacent regions of the first P-type well region 104 and the N-type drift region 103, the second gate structure is located between the N-type drift region 103 and the second P-type well region 105 and is in contact with the adjacent regions of the second P-type well region 105 and the N-type drift region 103, and a third N-type region 108 is formed in the central region of the overlap region 103, the LDMOS device 100 is a high-voltage power device having a left-right symmetric structure with respect to the central axis of the N-type drift region 103 (third N-type region 108).
In the present embodiment, the first P-type well region 104 and the second P-type well region 105 are drawn out by metal contact forming electrodes and are commonly connected to the source electrode S; the upper surface of each gate structure (polysilicon layer 17) is led out by a metal contact forming electrode and is commonly connected to a gate electrode G; and the N-type drift region 103 is led out by a metal contact forming electrode and connected to the drain electrode D, thereby forming the electrode relationship of the LDMOS device 100, more specifically, the first P-type well region 104 is electrically connected together by a metal contact formed on the surface of the first P-type region 106 and the first N-type region 107, the second P-type well region 105 is electrically connected together by a metal contact formed on the surface of the second N-type region 110 and the second P-type region 109, and then the metal contacts in the well regions are electrically connected together and commonly connected to the source electrode S; the N-type drift region 103 is connected to the drain electrode D through a metal contact electrode lead formed on the surface of the third N-type region 108.
According to the LDMOS device 100 provided by the embodiment of the invention, the linear distribution of the lateral doping concentration of the drift region (the concentration of the drift region gradually increases from the source end to the drain end) can be controlled by controlling the ion implantation energy and angle through the ion implantation process, so that a new electric field peak value is introduced on the surface of the drift region by the structure, the electric field distribution on the surface of the drift region is improved, and the breakdown voltage (withstand voltage) of the device is increased.
In addition, according to the technical scheme, the transverse linear variable-doping N-type drift region is formed by implanting ions with multiple oblique angles into the implantation region on the N-type epitaxial layer and the overlapping region between the implantation regions, the contradictory relation between high withstand voltage and on-resistance is relieved by the transverse linear distribution of the doping concentration of the N-type drift region, the surface doping concentration of the drift region is guaranteed to be higher, the current density of the drift region is increased, the resistance of the parasitic drift region is reduced, namely the on-resistance is reduced, the breakdown voltage and the on-resistance of the device are simultaneously optimized, the channel side electric field of the device is reduced, the hot carrier effect is effectively inhibited, and the reliability of the device is improved.
Fig. 2 is a flow chart illustrating a method for manufacturing a lateral double diffused transistor device according to an embodiment of the present invention, and here, an N-type lateral double diffused transistor is also taken as an example.
Referring to fig. 2, an embodiment of the present invention further provides a method for manufacturing a lateral double-diffused transistor device, which includes:
step S110: an N-type epitaxial layer is formed on a P-type substrate.
In step S110, an epitaxial layer 102 based on group IV elements is deposited on a P-type substrate 101 (e.g., a silicon substrate) by, for example, Chemical Vapor Deposition (CVD), the epitaxial layer having N-type impurities (e.g., phosphorus ions, arsenic ions), and the cross-section of the structure is shown in fig. 4a, but of course, the process of depositing the epitaxial layer includes, but is not limited to, CVD, and the N-type epitaxial layer 102 can also be formed by other known techniques.
Step S120: and forming an N-type drift region in an overlap region between an implantation region and an implantation region on the N-type epitaxial layer by utilizing multiple times of ion implantation.
In step S120, the doping concentration of the N-type drift region 103 is formed to be gradient from the center of the overlap region to the two ends along the channel direction, and specifically, as shown in fig. 3, the step of forming the N-type drift region 103 with a variable doping concentration includes:
substep S121: and performing self-aligned implantation in the vertical direction by using the patterned mask plate to form a first doping implantation region on the N-type epitaxial layer.
In sub-step S121, a self-aligned ion implantation in a vertical direction is performed on the N-type epitaxial layer 102 through the sidewalls of the patterned reticle 140 to form a first doped implantation region 1031, as shown in fig. 4 b.
Substep S122: and multiplexing the patterned mask plate in the ion implantation for even times after the self-aligned implantation, and forming an overlapping region overlapped with the first doping implantation region in the first doping implantation region by adopting oblique implantation at a first angle.
In sub-step S122, on the basis of the first doping implantation region 1031, the patterned mask 140 is reused to form a second doping implantation region on the N-type epitaxial layer 102 by using a first angled oblique implantation in an even number of ion implantations after the self-aligned implantation, as shown in fig. 4c, the second doping implantation region has an overlap region with at least a portion of the first doping implantation region 1031, the two ion implantations superimposed in the overlap region (darker region) result in a higher concentration of dopant ions than in the other region (lighter region) of the first dopant implantation region 1031, the ion concentration levels in this figure 4c and in the subsequent ion implantation cumulative overlap area diagram are simply indicated by the shades of color, however, the concentration gradient is not limited to the only one shown in the figure, and may be other expressions that can be easily conceived by a person having ordinary skill in the art, and is not limited thereto.
Substep S123: and multiplexing the patterned mask plate, and performing oblique implantation at a second angle in each odd-numbered ion implantation after each even-numbered ion implantation to form an overlapping region overlapped with the first doping implantation region.
In the sub-step S123, on the basis of the first doping implantation region 1031, the patterned mask 140 is multiplexed to perform the complementary implantation on the overlapped region overlapped with the first doping implantation region 1031 by using the oblique implantation with the second angle in each odd-numbered ion implantation after the even-numbered implantation, as shown in fig. 4d, so that the concentration of the first doping implantation region 1031 is symmetrically distributed around the central axis of the first doping implantation region 1031.
Further, the first angle used in the even-numbered ion implantation and the second angle used in the next odd-numbered ion implantation are complementary or equal to each other. In this embodiment, taking an angle formed by a direction of ion oblique implantation and a channel direction along the horizontal direction as an example, the first angle adopted in the ion implantation of the even number of times is an obtuse angle, and is complementary to the second angle which is adopted in the ion implantation of the next odd number of times after the even number of times and is an acute angle, and conditions such as energy, dose, implantation depth and the like of the two adjacent times of implantation except for the angle are controlled to be the same, so as to ensure that the concentration, diffusion rate and the like of the implanted ions are basically consistent, and the linear variable doping concentration distribution of the N-type drift region 103 of the final device is a symmetrical structure, so as to ensure the performance stability of the device.
In addition, the adjacent even number of ion implantation energies can be controlled through the oblique angle ion implantation process, so that the depths of the second doping implantation regions formed by ion diffusion corresponding to each even number of implantation are the same or are changed in a gradient manner, and the linear distribution of the transverse doping concentration of the drift region can be designed and adjusted according to the balance relationship between the actual withstand voltage requirement and the on-resistance without limitation, so that good device performance can be obtained.
Substep S124: repeating the substep S122 to the substep S123, sequentially forming a plurality of overlapped regions overlapped with the first doped implantation region, so that the concentration of the first doped implantation region after overlapping is symmetrically distributed around the central axis of the first doped implantation region.
In sub-step S124, the sub-steps S122 to S123 are repeated, as shown in fig. 4e to 4h, and in the ion implantation of the even number of times, the first angle used in the ion implantation is changed in a gradient manner according to the implantation sequence, specifically, for example, the first angle of the second oblique ion implantation (as shown in fig. 4 c) is greater than the first angle of the fourth oblique ion implantation (as shown in fig. 4 e), and the first angle of the fourth oblique ion implantation is greater than the first angle of the sixth oblique ion implantation (as shown in fig. 4 g), and similarly, for example, the second angle of the third oblique ion implantation (as shown in fig. 4 d) is greater than the second angle of the fifth oblique ion implantation (as shown in fig. 4 f), and the second angle of the fifth oblique ion implantation is greater than the second angle of the seventh oblique ion implantation (as shown in fig. 4 h), thereby forming a plurality of overlapping regions 1031 overlapping the first doped implantation region, the concentration of the first doped implantation region 1031 after ion doping superposition is distributed symmetrically with the central axis of the first doped implantation region 1031.
According to the related technology, the distribution of the implanted ions in the channel is directly influenced by the size of the implantation angle, when the implantation angle is increased, the distribution of the implanted ions in the vertical direction is relatively more concentrated, and meanwhile, the implanted ions are closer to the surface of the channel, so that the doping concentration of the upper layer of the channel is improved, and meanwhile, the mutual approaching of source drain depletion regions is more effectively inhibited by the improvement of the doping concentration. Thereby reducing the Drain Induced Barrier Lowering (DIBL) effect; and as the injection angle is reduced, the injected chestnuts are distributed deeper and wider and are closer to the bottom of the channel.
Substep S125: the first doping injection region and a plurality of overlapping regions overlapped with the first doping injection region form the N-type drift region, and the doping concentration of the N-type drift region is gradually reduced from the center of the overlapping regions to two ends along the channel direction.
In the sub-step S125, the first doping implantation region and the overlapping regions formed by multiple oblique implantations and overlapping with the first doping implantation region 1031 form the N-type drift region 103, as shown in fig. 4i to 4k, the linearly-varied doping concentration distribution of the N-type drift region 103 of the last device is a symmetric structure, and specifically, the doping concentration of the N-type drift region 103 is distributed in a gradient decreasing manner from the center of the overlapping region (or the center of the first doping implantation region) to both ends along the channel direction, so as to ensure the requirement of the device withstand voltage, and ensure sufficient N-type impurity doping concentration, thereby ensuring that the device has a smaller on-resistance.
In the embodiment, the same patterned mask is used for multiple times of ion implantation, and a specific design window is not needed to match with the performance requirement of the device, so that the process limitation and the process error are reduced, the formation of the linear variable doping drift region by using a specially-made mask with a specific window design in the prior art is avoided, the manufacturing cost is saved, and the applicability of the process of the linear variable doping drift region is improved.
In addition, the linear distribution of the doping concentration of the N-type drift region 103 (gradually decreasing from the center of the N-type drift region 103 to the two ends) is realized by angle conversion of odd-numbered (or even-numbered) oblique injection, and in practical application, the voltage resistance requirement of a finished device can be met by controlling the injection times and the injection angles of the odd-numbered (or even-numbered) oblique injection.
Step S130: and sequentially forming a gate oxide layer and a polysilicon layer on the P-type substrate, and etching to form gate structures arranged at intervals.
In step S130, a gate oxide layer 130 and a polysilicon layer 120 are sequentially formed on a P-type substrate 101, and the polysilicon layer 120 and the gate oxide layer 130 at the same position are sequentially etched, so that the polysilicon layer 120 and the gate oxide layer 130 in the reserved region are stacked to form a first gate structure and a second gate structure arranged at an interval, the N-type drift region 103 is formed between the first gate structure and the second gate structure, a first source region is defined on a side of the first gate structure away from the N-type drift region 103, and a second source region is defined on a side of the second gate structure away from the N-type drift region 103, as shown in fig. 4 i.
Step S140: and sequentially performing ion implantation on each source region to form a P-type well region, wherein each gate structure is positioned between the well region and the N-type drift region and is in contact with the well region and the N-type drift region adjacent to the gate structure.
In step S140, a first P-type well region 104 is formed by ion implantation in the first source region, and a second P-type well region 105 is formed by ion implantation in the second source region, the first gate structure is located between the first P-type well region 104 and the N-type drift region 103 and is in contact with a region adjacent to the first P-type well region 104 and the N-type drift region 103, and the second gate structure is located between the N-type drift region 103 and the second P-type well region 105 and is in contact with a region adjacent to the second P-type well region 105 and the N-type drift region 103, as shown in fig. 4 j.
Step S150: and sequentially carrying out ion implantation in each well region to form at least one N-type region and one P-type region, and forming an N-type region in the central region of the overlapped region in the N-type drift region by using ion implantation.
In step S150, ion implantation is sequentially performed in the first P-well region 104 to form a first P-region 106 and a first N-region 107, ion implantation is sequentially performed in the second P-well region 105 to form a second N-region 110 and a second P-region 109, and ion implantation is performed in the central region of the overlapping region in the N-drift region 103 to form a third N-region 108, as shown in fig. 4 k.
Step S160: and respectively forming metal contacts corresponding to the lead-out source electrode, the grid electrode and the drain electrode in the source region, the grid structure and the N-type drift region.
In step S160, metal contacts are formed on the first P-type region 106 and the first N-type region 107, and the second P-type region 109 and the second N-type region 110, respectively, and are electrically connected together, so as to be correspondingly led out to the source electrode S; respectively forming metal contacts on the upper surfaces of the first grid structure and the second grid structure, electrically connecting the metal contacts together, and correspondingly leading out the metal contacts to a grid electrode G; and forming a metal contact on a third N-type region 108 formed in the central region of the overlapping region in the aforementioned N-type drift region 103 to correspondingly lead out to the drain electrode D, as shown in fig. 4k and fig. 1, so as to form the electrode relationship of the LDMOS device 100, wherein the formed LDMOS device is a high-voltage power device in a left-right symmetric structure with the central axis of the third N-type region 108.
In summary, in the method for manufacturing a lateral double-diffused transistor according to the embodiment of the present invention, multiple ion implantations (oblique angle implantations) are used to form an N-type drift region in the implantation region and the overlap region between the implantation regions on the substrate, and the doping concentration of the N-type drift region is distributed in a gradient manner (linearly changing the doping concentration) from the center of the overlap region to the two ends along the channel direction, so that the breakdown voltage of the device is increased, and the sufficient impurity doping concentration is ensured, thereby ensuring that the device has a smaller on-resistance, and improving the performance of the formed device.
Meanwhile, in the embodiment, the same patterned mask is only used by multiple times of ion implantation, and a specific design window is not needed to match with the performance requirement of the device, so that the process limitation and the process error are reduced, the problem that a special mask with a specific window design is used for forming a linear variable doping drift region in the prior art is avoided, the manufacturing cost is saved, and the linear distribution of the doping concentration of the drift region can be controlled by controlling the times and the angle of the ion implantation through the process, so that the applicability of the manufacturing method is improved.
It should be noted that, in the above embodiments, the N-type LDMOS device is taken as an example, but the same is also applicable to the P-type LDMOS device, and meanwhile, the types and positions of the N-type region and the P-type region in each P-type well region are not fixed, as long as each P-type well region is ensured to include at least one N-type region and one P-type region, which is not limited herein.
Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments not explicitly described, or to another embodiment described.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientations or positional relationships, are used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications are intended to be within the scope of the present invention.
Claims (8)
1. A method of fabricating a lateral double diffused transistor, comprising:
forming a drift region of a first doping type in an implantation region and an overlapping region between the implantation regions on a substrate by utilizing multiple times of ion implantation, wherein the doping concentration of the drift region is gradually reduced and changed towards two ends along the channel direction by the center of the overlapping region;
sequentially forming a gate oxide layer and a polysilicon layer on the substrate, and etching to form gate structures arranged at intervals, wherein the gate structures define a plurality of source regions and drift regions;
sequentially performing ion implantation on each source region to form a well region of a second doping type, wherein each gate structure is positioned between the well region and the drift region and is in contact with the well region and the drift region adjacent to the gate structure;
sequentially performing ion implantation in each well region to form at least one N-type region and one P-type region, and forming one N-type region in the central region of the overlapping region in the drift region by using ion implantation;
respectively forming metal contacts corresponding to an extraction source electrode, a grid electrode and a drain electrode in the source region, the grid structure and the drift region,
the transverse double-diffused transistor is formed in a structure which is symmetrical left and right on the central axis of the drift region,
wherein the multiple ion implantations include a self-aligned implantation, an even number of ion implantations after the self-aligned implantation, and an odd number of ion implantations after each even number;
a first angle employed in an even number of ion implantations following said self-aligned implantation is complementary to a second angle employed in a next odd number of ion implantations of the even number,
the first angle and the second angle are included angles between the oblique ion implantation direction and the horizontal right direction, the first angle adopted in the even-number ion implantation after the self-alignment implantation is gradually decreased along with the implantation sequence, and the second angle adopted in the odd-number ion implantation after the self-alignment implantation is gradually increased along with the implantation sequence.
2. The method of claim 1, wherein prior to forming the drift region of the first doping type in the implanted region and the overlap region between the implanted regions on the substrate using a plurality of ion implantations, the method further comprises:
an epitaxial layer of a first doping type is formed on the substrate, and the drift region is formed on the epitaxial layer.
3. The method of claim 2, wherein forming the drift region of the first doping type in the implant region and the overlap region between the implant regions on the substrate by multiple ion implantations comprises:
performing self-aligned implantation in the vertical direction by using a patterned mask plate, and forming a first doping implantation region on the epitaxial layer;
multiplexing the patterned mask plate in the ion implantation for even times after the self-alignment implantation, and forming an overlapping region overlapped with the first doping implantation region in the first doping implantation region by adopting oblique implantation at a first angle;
multiplexing the patterned mask plate in each odd-numbered ion implantation after the even-numbered times, and performing oblique implantation at a second angle in the first doping implantation area to form an overlapping area overlapped with the first doping implantation area, so that the concentration of the first doping implantation area after the overlapping is symmetrically distributed by the central axis of the first doping implantation area;
the first doping injection region and the overlapping region overlapped with the first doping injection region form the drift region, and the doping concentration of the drift region changes in a gradient and descending manner from the center of the overlapping region to two ends along the channel direction.
4. The method of manufacturing according to claim 2, wherein the forming of the spaced apart gate structures by etching, the gate structures defining a plurality of source regions and the drift region, comprises:
sequentially etching the polysilicon layer and the gate oxide layer at the same position to superpose the polysilicon layer and the gate oxide layer in the reserved region to form a first gate structure and a second gate structure arranged at intervals,
the drift region is arranged between the first gate structure and the second gate structure, a first source region is defined on one side, far away from the drift region, of the first gate structure, and a second source region is defined on one side, far away from the drift region, of the second gate structure.
5. The method of claim 4, wherein sequentially performing ion implantation in each well region to form at least one N-type region and one P-type region comprises:
sequentially performing ion implantation in the first source region to form a first P-type region and a first N-type region;
and sequentially performing ion implantation in the second source region to form a second P-type region and a second N-type region.
6. The method of manufacturing according to claim 5, wherein forming metal contacts in the source region, the gate structure, and the drift region to respectively correspond to a lead-out source electrode, a gate electrode, and a drain electrode comprises:
respectively forming metal contacts on the first P-type region and the first N-type region, and on the second P-type region and the second N-type region, electrically connecting the metal contacts together, and correspondingly leading out the metal contacts to a source electrode;
respectively forming metal contacts on the upper surfaces of the first grid structure and the second grid structure, electrically connecting the metal contacts together, and correspondingly leading out the metal contacts to the grid electrodes;
and forming a metal contact on an N-type region formed in the central region of the overlapping region in the drift region, and correspondingly leading out the metal contact to a drain electrode.
7. The method of manufacturing according to claim 2, wherein the substrate is a substrate of a second doping type.
8. The method of manufacturing according to claim 7, wherein the first doping type is N-type and the second doping type is P-type;
or, the first doping type is P-type, and the second doping type is N-type.
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| CN114639607B (en) * | 2022-03-16 | 2023-05-26 | 江苏东海半导体股份有限公司 | Forming method of MOS device |
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| CN116364553A (en) * | 2023-06-02 | 2023-06-30 | 华南理工大学 | Method for manufacturing semiconductor device and semiconductor device |
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