CN114639607B - Forming method of MOS device - Google Patents

Forming method of MOS device Download PDF

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CN114639607B
CN114639607B CN202210259306.3A CN202210259306A CN114639607B CN 114639607 B CN114639607 B CN 114639607B CN 202210259306 A CN202210259306 A CN 202210259306A CN 114639607 B CN114639607 B CN 114639607B
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epitaxial layer
forming
epitaxial
groove
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CN114639607A (en
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胡盖
李健
黄传伟
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Jiangsu Donghai Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1604—Amorphous materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses a method for forming a MOS device, which comprises the following steps: forming an epitaxial layer on a substrate, wherein the epitaxial layer has at least two regions with different impurity concentrations; forming a first trench in the epitaxial layer; performing first ion implantation to form an amorphous region in the epitaxial layer at the bottom of the first groove; forming a first dielectric layer on the epitaxial layer and the surface of the first groove; forming a polysilicon layer on the first dielectric layer; flattening and removing the first dielectric layer and the polysilicon layer in other areas outside the first groove; performing second ion implantation to form a first doped region in the epitaxial layer at two sides of the trench gate; performing ion implantation for the third time to form a heavily doped region in the first doped region; forming a second dielectric layer on the epitaxial layer, the first dielectric layer and the polysilicon layer; forming a second groove in the epitaxial layer at two sides of the groove gate, wherein the bottom of the second groove is lower than the bottom of the first doping region, and the bottom of the second groove is higher than the bottom of the epitaxial layer; and forming a metal layer on the surfaces of the epitaxial layer and the second dielectric layer.

Description

Forming method of MOS device
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a forming method of a MOS device.
Background
Metal-oxide-semiconductor field effect transistor (MOSFET), referred to herein simply as "MOS") devices, are electronic devices that are used in analog and digital circuits.
Among them, the trench type MOS (trench MOS) device has lower on-resistance and gate leakage charge density, thereby having lower on-and switching loss, and faster switching speed, and is generally used as a power device (also referred to as an "electronic power device") in the fields of consumer electronics, new energy automobiles, servers, control devices, and the like. In general, trench MOS devices are typically formed in an epitaxial layer formed on a silicon substrate, and leakage current is easily formed in a corner region at the bottom of a trench gate, resulting in a lower breakdown voltage of the device and poor reliability.
Disclosure of Invention
The application provides a method for forming a MOS device, which can solve the problems of lower breakdown voltage and poor reliability of the device formed by the method for forming the MOS device provided in the related technology, and comprises the following steps:
forming an epitaxial layer on a substrate, wherein a first type of impurity is doped in the epitaxial layer, the impurity concentration of at least two regions in the epitaxial layer is different, the substrate comprises a cell region and a terminal region in a top view, the cell region is a region for forming the MOS device, and the terminal region is a region for forming a terminal structure;
forming a first groove in the epitaxial layer of the cell region;
performing first ion implantation to form an amorphous region in the epitaxial layer at the bottom of the first groove;
forming a first dielectric layer on the epitaxial layer and the surface of the first groove;
forming a polysilicon layer on the first dielectric layer;
flattening, namely removing the first dielectric layer and the polysilicon layer in other areas outside the first groove, wherein the first dielectric layer in the first groove forms a gate first dielectric layer of the MOS device, and the polysilicon layer in the first groove forms a groove gate of the MOS device;
performing second ion implantation, and forming a first doped region in the epitaxial layer at two sides of the trench gate, wherein the impurity doped in the first doped region is a second type impurity;
performing third ion implantation to form a heavily doped region in the first doped region, wherein the impurity doped in the heavily doped region is the first type of impurity, and the impurity concentration of the heavily doped region is greater than that of the epitaxial layer and the first doped region;
forming a second dielectric layer on the epitaxial layer, the first dielectric layer and the polysilicon layer;
forming a second groove in the epitaxial layer at two sides of the groove gate, wherein the bottom of the second groove is lower than the bottom of the first doping region, and the bottom of the second groove is higher than the bottom of the epitaxial layer;
and forming a metal layer on the surfaces of the epitaxial layer and the second dielectric layer.
In some embodiments, the epitaxial layer comprises at least two sub-epitaxial layers from bottom to top, and the impurity concentrations of two adjacent sub-epitaxial layers are different;
the forming an epitaxial layer on a substrate includes:
growing a first sub-epitaxial layer on the substrate, and performing epitaxial layer ion implantation;
growing a second sub-epitaxial layer on the first sub-epitaxial layer, and performing epitaxial layer ion implantation;
repeating the steps until the sum of the thicknesses of the sub-epitaxial layers reaches a target thickness;
the ion implantation doses of the epitaxial layers of two adjacent sub-epitaxial layers are different.
In some embodiments, the energy of each of the epitaxial layer ion implants is such that the impurity does not penetrate its corresponding sub-epitaxial layer.
In some embodiments, the epitaxial layer comprises at least two regions of different impurity concentrations from lateral directions;
the forming an epitaxial layer on a substrate includes:
growing an epitaxial layer on the substrate;
forming a hard mask layer on the epitaxial layer to expose a target area;
performing at least one epitaxial layer ion implantation;
and removing the hard mask layer.
In some embodiments, the hard mask layer is a silicon nitride layer or a silicon oxide layer.
In some embodiments, the first trench has a width greater than 0.7 microns.
In some embodiments, the first trench has a depth of less than 1.2 microns.
In some embodiments, the impurity incorporated in the first ion implantation is elemental hydrogen.
In some embodiments, the first dielectric layer is a silicon oxide layer;
and forming a first dielectric layer on the epitaxial layer and the surface of the first groove, wherein the first dielectric layer comprises the following components:
and forming silicon oxide on the epitaxial layer and the surface of the first groove to form the first dielectric layer through a thermal oxidation process or sequentially through a thermal oxidation process and a CVD process.
In some embodiments, the second dielectric layer is a silicon oxide layer;
and forming a second dielectric layer on the epitaxial layer, the first dielectric layer and the polysilicon layer, wherein the second dielectric layer comprises:
and depositing a silicon oxide layer on the epitaxial layer, the first dielectric layer and the polycrystalline silicon layer through a CVD process to form the second dielectric layer.
The technical scheme of the application at least comprises the following advantages:
according to the method, in the manufacturing process of the groove type MOS device, the area with at least two different impurity concentrations is formed in the epitaxial layer, so that the scattering rate of leakage current from the bottom corner of the groove gate is improved, and the breakdown voltage of the device is further improved; meanwhile, by forming the amorphous region at the bottom of the trench gate, the thickness of the insulating layer at the bottom of the trench gate is increased, leakage current is further reduced, breakdown voltage of the device is further improved, and reliability of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for forming a MOS device according to an exemplary embodiment of the present application;
fig. 2 to 11 are schematic diagrams illustrating formation of a MOS device according to an exemplary embodiment of the present application;
fig. 12 is a flowchart of a method for forming an epitaxial layer of a MOS device according to an exemplary embodiment of the present application;
fig. 13 to 14 are schematic views illustrating formation of epitaxial layers of a MOS device according to an exemplary embodiment of the present application;
fig. 15 is a flowchart of a method for forming an epitaxial layer of a MOS device according to an exemplary embodiment of the present application;
fig. 16 is a schematic diagram illustrating formation of an epitaxial layer of a MOS device according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a flowchart of a method for forming a MOS device according to an exemplary embodiment of the present application is shown, and as shown in fig. 1, the method includes:
step S1, an epitaxial layer is formed on a substrate, a first type of impurity is doped in the epitaxial layer, the impurity concentration of at least two areas in the epitaxial layer is different, the substrate comprises a cell area and a terminal area in a overlooking view, the cell area is an area for forming a MOS device, and the terminal area is an area for forming a terminal structure.
Referring to fig. 2, a schematic cross-sectional view of an epitaxial layer formed in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Illustratively, as shown in fig. 2, the substrate 110 includes a cell region and a terminal region (not shown in fig. 1) from a top view, and a cross-sectional view of the cell region is described below as an example: the epitaxial layer 111 is formed on the substrate 110, wherein the first type of impurity is doped in the epitaxial layer 111, and the impurity concentrations of at least two regions are different, so that impurity regions with uneven distribution are formed due to the fact that the impurity concentrations of at least two regions are different, and after the MOS device is formed through the subsequent steps, the scattering rate of leakage current from the bottom corner of the trench gate is improved, and the breakdown voltage of the device is further improved.
Step S2, forming a first groove in the epitaxial layer of the cell area.
Referring to fig. 3, a schematic cross-sectional view of a first trench formed in an epitaxial layer of a cellular region in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Illustratively, as shown in FIG. 3, step S2 includes, but is not limited to: a photoresist (not shown in fig. 3) is covered on the epitaxial layer 111 by a photolithography process, a target region (the target region in this step is a region corresponding to the first trench 201) is exposed, etching is performed to a target depth in the epitaxial layer 111, the first trench 201 is formed (the bottom of the first trench 201 is higher than the bottom of the epitaxial layer 111), and the photoresist is removed (the photoresist may be removed by an ashing (ashing) process).
In some embodiments, the width W of the first trench 201 is greater than 0.7 micrometers (μm); in some embodiments, the depth H of the first trench 201 is less than 1.2 microns. The applicant found that by adjusting the dimensions of the trenches of the trench MOS device, other electrical parameters of the MOS device can be improved, and when the width W of the first trench 201 is greater than 0.7 microns, the channel concentration is greater when the device is in operation; when the depth H of the first trench 201 is less than 1.2 micrometers, the breakdown voltage may be further improved.
And S3, performing first ion implantation to form an amorphous region in the epitaxial layer at the bottom of the first groove.
Referring to fig. 4, a schematic cross-sectional view of performing a first ion implantation in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Illustratively, as shown in fig. 4, by first ion implantation, an amorphous region (not shown in fig. 4) is formed in the epitaxial layer 111 at the bottom of the first trench 201, increasing the thickness of the insulating layer at the bottom of the MOS device formed by the subsequent steps, reducing leakage current, and increasing the breakdown voltage of the device. In some embodiments, the impurity incorporated in the first ion implantation is elemental hydrogen (H).
And S4, forming a first dielectric layer on the epitaxial layer and the surface of the first groove.
Referring to fig. 5, a schematic cross-sectional view of a first dielectric layer formed on the surface of an epitaxial layer and a first trench in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Illustratively, as shown in FIG. 5, the first dielectric layer 122 comprises silicon oxide (e.g., silicon dioxide (SiO) 2 ) A layer), a silicon oxide may be formed on the epitaxial layer 111 and the surface of the first trench 201 by a thermal oxidation (thermal oxidation) process to form the first dielectric layer 121. Since the amorphous region is formed in the epitaxial layer 111 at the bottom of the first trench 201 in step S3, the insulating layer at the bottom of the first trench is increased(sum of thicknesses of the first dielectric layer 121 and the amorphous region).
In some embodiments, the first dielectric layer 121 may be formed by sequentially performing a thermal oxidation process and a chemical vapor deposition (chemical vapor deposition, CVD) process (e.g., a high-density plasma chemical vapor deposition (high density plasma chemical vapor deposition, HDP CVD) process and/or a sub-atmospheric chemical vapor deposition (sub atmospheric pressure chemical vapor deposition, SA CVD) process) to form silicon oxide on the surface of the epitaxial layer 111 and the first trench 201, and the thickness of the silicon oxide layer at the bottom of the first trench 201 may be made greater than the thickness of the silicon oxide layer at the side wall by controlling the reaction parameters in the CVD process, thereby further increasing the thickness of the insulating layer at the bottom of the trench.
In this embodiment of the present application, the thickness of the insulating layer at the bottom of the first trench may be controlled to be 1.5 to 2 times the thickness of the insulating layer on the sidewall thereof, so as to achieve a better effect.
And S5, forming a polysilicon layer on the first dielectric layer.
Referring to fig. 6, a schematic cross-sectional view of forming a polysilicon layer on a first dielectric layer in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Illustratively, as shown in fig. 6, the polysilicon layer 130 may be deposited on the first dielectric layer 121 by a CVD process (e.g., a plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PE CVD) process may be employed), the polysilicon layer 130 filling the first trench 201.
And S6, flattening, namely removing the first dielectric layer and the polysilicon layer in other areas outside the first groove, wherein the first dielectric layer in the first groove forms a gate first dielectric layer of the MOS device, and the polysilicon layer in the first groove forms a groove gate of the MOS device.
Referring to fig. 7, a schematic cross-sectional view of a method for forming a MOS device according to an exemplary embodiment of the present application is shown, where planarization is performed after a polysilicon layer is formed. Illustratively, as shown in fig. 7, the planarization may be performed by a chemical mechanical polishing (chemical mechanical planarization, CMP) process, removing the first dielectric layer 121 and the polysilicon layer 130 in other areas outside the first trench 202.
And S7, performing second ion implantation, and forming a first doped region in the epitaxial layer at the two sides of the trench gate, wherein the impurity doped in the first doped region is a second type impurity.
And S8, performing third ion implantation to form a heavy doped region in the first doped region, wherein the impurity doped in the heavy doped region is of a first type, and the impurity concentration of the heavy doped region is greater than that of the epitaxial layer and the first doped region.
Referring to fig. 8, a schematic cross-sectional view of a MOS device after performing a second ion implantation and a third ion implantation in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. As shown in fig. 8, the epitaxial layer 111 on both sides of the trench gate is formed with a first doped region 112 after the second ion implantation, and a heavily doped region 113 is formed in the first doped region 111 after the second ion implantation.
And S9, forming a second dielectric layer on the epitaxial layer, the first dielectric layer and the polysilicon layer.
Referring to fig. 9, a schematic cross-sectional view of forming a second dielectric layer on an epitaxial layer, a first dielectric layer, and a polysilicon layer in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Illustratively, as shown in fig. 9, the second dielectric layer 140 includes a silicon oxide (e.g., silicon dioxide) layer, which may be deposited by a CVD process (e.g., may be by an HDP CVD process and/or an SA CVD process) over the epitaxial layer 111, the first dielectric layer 121, and the polysilicon layer 130 to form the second dielectric layer 140.
And S10, forming a second groove in the epitaxial layer at the two sides of the groove gate, wherein the bottom of the second groove is lower than the bottom of the first doped region, and the bottom of the second groove is higher than the bottom of the epitaxial layer.
Referring to fig. 10, a schematic cross-sectional view of forming a second trench in an epitaxial layer on both sides of a trench gate in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. Exemplary, as shown in fig. 10, step S10 includes, but is not limited to: a photoresist (not shown in fig. 10) is covered on the second dielectric layer 140 by a photolithography process, a target region (the target region in this step is a region corresponding to the second trench 202) is exposed, etching is performed to a target depth in the epitaxial layer 111, the second trench 202 is formed (the bottom of the second trench 202 is lower than the bottom of the first doped region 112, and the bottom of the second trench 202 is higher than the bottom of the epitaxial layer 111), and the photoresist is removed (the photoresist may be removed by an ashing process).
And S11, forming a metal layer on the surfaces of the epitaxial layer and the second dielectric layer.
Referring to fig. 11, a schematic cross-sectional view of a metal layer formed on the surface of an epitaxial layer and a second dielectric layer in a method for forming a MOS device according to an exemplary embodiment of the present application is shown. For example, as shown in fig. 11, if the metal layer 150 includes tungsten (W), the metal layer 150 may be formed by depositing tungsten using a CVD process; if the metal layer 150 comprises aluminum (Al), the metal layer 150 may be formed by depositing aluminum using a physical vapor deposition (physical vapor deposition, PVD) process; if the metal layer 150 includes copper (Cu), the metal layer 150 may be formed by electroplating copper using an electroplating process. After forming the metal layer 150, a planarization process (e.g., planarization by a CMP process) may be performed.
In summary, in the embodiment of the present application, during the manufacturing process of the trench MOS device, by forming a region including at least two regions with different impurity concentrations in the epitaxial layer, the scattering rate of the leakage current from the bottom corner of the trench gate is improved, and the breakdown voltage of the device is further improved; meanwhile, by forming the amorphous region at the bottom of the trench gate, the thickness of the insulating layer at the bottom of the trench gate is increased, leakage current is further reduced, breakdown voltage of the device is further improved, and reliability of the device is improved.
In the embodiment of the present application, the epitaxial layer 111 in which at least two regions having different impurity concentrations are present may be formed in two ways, and the following methods may be referred to:
referring to fig. 12, a flowchart illustrating a method for forming an epitaxial layer of a MOS device according to an exemplary embodiment of the present application may be an alternative implementation manner of step S1 in the embodiment of fig. 1, and as shown in fig. 12, the method includes:
step S111, a first sub-epitaxial layer is grown on the substrate, and epitaxial layer ion implantation is performed.
In this embodiment, the epitaxial layer 111 includes at least two sub-epitaxial layers from bottom to top, and the impurity concentrations of the adjacent two sub-epitaxial layers are different.
As shown in fig. 13, after the first sub-epitaxial layer 1111 is formed on the substrate 110 by growth through an epitaxial growth process, epitaxial layer ion implantation may be performed, and the impurity doped in the ion implantation is a first type impurity.
And step S112, growing a second sub-epitaxial layer on the first sub-epitaxial layer, and performing epitaxial layer ion implantation.
As shown in fig. 14, after the second sub-epitaxial layer 1111 is formed on the substrate 110 by growth through an epitaxial growth process, epitaxial layer ion implantation may be performed, and the impurity doped in the ion implantation is a first type impurity.
And step S113, repeating the steps until the sum of the thicknesses of the sub-epitaxial layers reaches the target thickness.
For example, the thickness of the first sub-epitaxial layer is h1, the thickness of the second sub-epitaxial layer is h2, and if the target thickness h=h1+h2, the second sub-epitaxial layer is grown, and then the epitaxial layer is not grown continuously. In the multi-time growth of the sub-epitaxial layers and the ion implantation of the epitaxial layers, the ion implantation doses of the epitaxial layers of the adjacent two sub-epitaxial layers are different, so that different impurity concentrations are formed.
In some embodiments, the energy of each epitaxial layer ion implantation does not allow impurities to penetrate its corresponding sub-epitaxial layer, so that each epitaxial layer ion implantation does not affect the next layer; in some embodiments, the epitaxial layer 111 includes at least three sub-epitaxial layers from bottom to top, and the impurity concentrations of the uppermost sub-epitaxial layer and the lowermost sub-epitaxial layer are greater than those of the other sub-epitaxial layers, thereby forming a higher upper and lower impurity concentration profile with a lower intermediate impurity concentration profile that can increase the breakdown voltage of the device with minimal impact on other electrical parameters.
Referring to fig. 15, a flowchart illustrating a method for forming an epitaxial layer of a MOS device according to an exemplary embodiment of the present application may be an alternative implementation manner of step S1 in the embodiment of fig. 1, as shown in fig. 15, where the method includes:
step S121, an epitaxial layer is grown on the substrate.
In step S122, a hard mask layer is formed on the epitaxial layer, exposing the target region.
Step S123, performing at least one epitaxial layer ion implantation.
In step S124, the hard mask layer is removed.
Referring to fig. 16, a schematic cross-sectional view of ion implantation after forming a hard mask layer on an epitaxial layer in a method for forming an epitaxial layer of a MOS device according to an exemplary embodiment of the present application is shown. Exemplary, as shown in fig. 16:
in some embodiments, the hard mask layer 300 is a photoresist, and the photoresist may be covered on the epitaxial layer 111 by a photolithography process, exposing a target region (in this step, the target region is a region with a higher impurity concentration in the epitaxial layer), performing at least one epitaxial layer ion implantation, and removing the photoresist (which may be removed by an ashing process). The ion implantation energy can pass through the photoresist, but the ion implantation is blocked by the photoresist, so that the impurity concentration of the area under the photoresist is lower, the impurity concentration of the exposed area is higher, and the difference of the impurity concentrations in the transverse direction is realized.
In some embodiments, the hard mask layer 300 is a dielectric layer (e.g., a silicon nitride (such as silicon nitride (SiN)) layer or a silicon oxide (such as silicon dioxide) layer), the dielectric layer may be formed by a CVD process, a target region (in this step, a region having a higher impurity concentration in the epitaxial layer) may be exposed by a photolithography and etching process, at least one epitaxial layer ion implantation may be performed, and the dielectric layer may be removed (e.g., by a dry etching process or a wet etching process (e.g., a wet etching process may be performed by phosphoric acid if the dielectric layer is a silicon nitride layer)). The energy of the ion implantation can pass through the layer, but the ion implantation is blocked by the dielectric layer, so that the impurity concentration of the area below the dielectric layer is lower, the impurity concentration of the exposed area is higher, and the difference of the impurity concentrations in the transverse direction is realized.
In the embodiment of the present application, when the first type impurity is an N (negative) type impurity, the second type impurity is a P (positive) type impurity; when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (3)

1. The method for forming the MOS device is characterized by comprising the following steps of:
growing a first sub-epitaxial layer on a substrate, and performing epitaxial layer ion implantation;
growing a second sub-epitaxial layer on the first sub-epitaxial layer, and performing epitaxial layer ion implantation, wherein the energy of each epitaxial layer ion implantation cannot enable impurities to permeate the corresponding sub-epitaxial layer, and the doses of epitaxial layer ion implantation of two adjacent sub-epitaxial layers are different;
repeating the steps until the sum of the thicknesses of the sub-epitaxial layers reaches a target thickness, forming an epitaxial layer, wherein the epitaxial layer is doped with first type impurities, the epitaxial layer comprises at least three sub-epitaxial layers from bottom to top, the impurity concentrations of two adjacent sub-epitaxial layers are different, the impurity concentration of the sub-epitaxial layer of the uppermost layer and the impurity concentration of the sub-epitaxial layer of the lowermost layer are greater than those of the sub-epitaxial layers of other layers, and the substrate comprises a cell region and a terminal region from the top view, wherein the cell region is a region for forming the MOS device, and the terminal region is a region for forming a terminal structure;
forming a first groove in the epitaxial layer of the cell region, wherein the width of the first groove is larger than 0.7 micron, and the depth of the first groove is smaller than 1.2 microns;
performing first ion implantation to form an amorphous region in the epitaxial layer at the bottom of the first groove;
forming a first dielectric layer on the epitaxial layer and the surface of the first groove by sequentially forming a silicon oxide layer through a thermal oxidation process and a CVD process, wherein the thickness of an insulating layer at the bottom of the first groove is 1.5-2 times that of an insulating layer on the side wall of the first groove by controlling reaction parameters in the CVD process, and the CVD process comprises an HDP CVD process and/or an SA CVD process;
forming a polysilicon layer on the first dielectric layer;
flattening, namely removing the first dielectric layer and the polysilicon layer in other areas outside the first groove, wherein the first dielectric layer in the first groove forms a gate first dielectric layer of the MOS device, and the polysilicon layer in the first groove forms a groove gate of the MOS device;
performing second ion implantation, and forming a first doped region in the epitaxial layer at two sides of the trench gate, wherein the impurity doped in the first doped region is a second type impurity;
performing third ion implantation to form a heavily doped region in the first doped region, wherein the impurity doped in the heavily doped region is the first type of impurity, and the impurity concentration of the heavily doped region is greater than that of the epitaxial layer and the first doped region;
forming a second dielectric layer on the epitaxial layer, the first dielectric layer and the polysilicon layer;
forming a second groove in the epitaxial layer at two sides of the groove gate, wherein the bottom of the second groove is lower than the bottom of the first doping region, and the bottom of the second groove is higher than the bottom of the epitaxial layer;
and forming a metal layer on the surfaces of the epitaxial layer and the second dielectric layer.
2. The method of claim 1, wherein the impurity incorporated in the first ion implantation is elemental hydrogen.
3. The method of claim 1, wherein the second dielectric layer is a silicon oxide layer;
and forming a second dielectric layer on the epitaxial layer, the first dielectric layer and the polysilicon layer, wherein the second dielectric layer comprises:
and depositing a silicon oxide layer on the epitaxial layer, the first dielectric layer and the polycrystalline silicon layer through a CVD process to form the second dielectric layer.
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