CN112614895A - Structure and method of VDMOS (vertical double-diffused metal oxide semiconductor) with multilayer epitaxial super-junction structure - Google Patents
Structure and method of VDMOS (vertical double-diffused metal oxide semiconductor) with multilayer epitaxial super-junction structure Download PDFInfo
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Abstract
The invention provides a structure of a VDMOS (vertical double-diffused metal oxide semiconductor) with a multilayer epitaxial super-junction structure and a method thereof, wherein a drain electrode is arranged above the drain electrode, an n-type drift region is arranged above the substrate, a p-type block is arranged inside the n-type drift region, a p-type well is arranged above the p-type block, an n + type source region and a p + type short-circuit region are arranged inside the p-type well, a grid oxide layer is arranged on the top of the p-type well, a transverse p-type block vertical to the direction of a strip-shaped polycrystalline layer is arranged in the n-type drift region, the p-type block region of a main bearing layer is vertical to the extension direction of the p-type well, the length of the p-type block is not a factor for limiting the size of a single cell, the size of the single cell is completely determined by the interval length between the polycrystalline layer and the polycrystalline layer, and the propulsion process steps after the primary etching, the three-time propulsion of the original manufacturing process flow is integrated into one-time propulsion, so that the process time and the cost are greatly saved.
Description
Technical Field
The invention relates to the technical field of VDMOS, in particular to a structure of a VDMOS with a multilayer epitaxial super junction structure and a method thereof.
Background
At present, novel power electronic devices in China mainly comprise VDMOS and IGBT devices, the conduction loss is obviously increased due to large conduction resistance of a conventional VDMOS under a high-voltage and high-current application scene, the conduction resistance can be greatly reduced under the condition of ensuring voltage by virtue of a unique charge balance structure of a VDMOS with a super-junction structure, so that the conduction loss is improved, a multilayer epitaxial super-junction VDMOS process is easy to realize and stable in process compared with a deep-trench super-junction structure, and the process is pursued by various manufacturers, so that how to reduce the unit cell size and the process cost become the direction of the progress of the multilayer epitaxial super-junction technology.
Disclosure of Invention
The embodiment of the invention provides a structure of a VDMOS (vertical double-diffused metal oxide semiconductor) with a multilayer epitaxial super-junction structure and a method thereof.A transverse p-type block perpendicular to the direction of a strip-shaped polycrystalline layer is arranged in an n-type drift region, and the p-type block region of a main bearing layer is perpendicular to the extending direction of a p-type well, so that the length of the p-type block does not become a factor for limiting the size of a single cell, the size of the single cell is completely determined by the interval length between the polycrystalline layer and the polycrystalline layer, and meanwhile, after the pushing process steps after the primary etching, the secondary etching and the tertiary etching of the original process are integrated into the third etching, the three pushing of the original manufacturing process flow is integrated into one pushing.
In view of the above problems, the technical solution proposed by the present invention is:
the utility model provides a structure of super junction structure VDMOS is extended to multilayer, includes the drain electrode, the top of drain electrode is provided with the substrate, the top of substrate is provided with n type drift region, the inside in n type drift region is provided with p type piece, the top of p type piece is provided with p type well, the inside of p type well is provided with n + type source region and p + type short circuit district, the top of p type well is provided with the grid oxide layer, the top that has the grid oxide layer is provided with the grid polycrystal layer, the top on grid polycrystal layer is provided with the source electrode oxide layer, the top facility of source electrode oxide layer has source electrode metal.
In order to better realize the technical scheme of the invention, the following technical measures are also adopted.
Further, the n-type drift region is formed through five times of epitaxial processes.
Furthermore, the number of the p-type blocks is at least more than one, and the p-type blocks are longitudinally and uniformly arranged in the n-type drift region.
Further, the n-type drift region is generated on the surface of the substrate through a chemical vapor deposition method.
A method for a VDMOS with a multilayer epitaxial super junction structure comprises the following steps:
s1, setting a doped region for the first time, and growing an n-type drift region on the surface of the substrate by a chemical vapor deposition method;
s2, carrying out first photoetching, and photoetching a first layer of p-type block injection window at the top of the n-type drift region through a photoetching process; injecting the mixture into the n-type drift region by an ion injection method to form a first layer of p-type blocks; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a first layer of n-type block;
s3, setting a doped region for the second time, and growing an n-type drift region on the surface of the substrate by a chemical vapor deposition method; photoetching for the second time, wherein a second layer of p-type block injection window is photoetched at the top of the n-type drift region through a photoetching process; implanting the p-type drift region into the n-type drift region by an ion implantation method to form a second layer of p-type blocks; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a second layer of n-type blocks;
s4, setting a doping area for the third time, growing an n-type drift area on the surface of the substrate by a chemical vapor deposition method, photoetching for the third time, and photoetching a third layer of p-type block injection window on the top of the n-type drift area by a photoetching process; injecting the mixture into the n-type drift region by an ion injection method to form a third layer of p-type block; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a third layer of n-type block;
s5, setting a doping area for the fourth time, growing an n-type drift area on the surface of the substrate by a chemical vapor deposition method, photoetching for the fourth time, and photoetching a fourth layer of p-type block injection window on the top of the n-type drift area by a photoetching process; implanting the n-type drift region by an ion implantation method to form a fourth layer of p-type block; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a fourth layer of n-type blocks;
s6, arranging a doped region for the fifth time, and growing an n-type drift region on the surface of the substrate by a chemical vapor deposition method;
s7, etching for the first time, growing a 12000A initial oxide layer through high-temperature oxidation, and etching a p-type guard ring injection window on the top of the n-type drift region through an etching process; p-type ion implantation;
s8, etching for the second time, and etching an n-type injection window through the top of the n-type drift region of the etching process; injecting n-type ions, growing a gate oxide layer at high temperature of 1100 ℃, and depositing a polycrystalline layer by chemical vapor deposition;
s9, etching a p-type well injection window on the polycrystalline layer through an etching process for the third time, and injecting p-type ions;
s10, performing high-temperature propulsion at 1150 ℃, wherein the p-type block is connected with the p-type guard ring and the p-type trap;
s11, etching for the fourth time, namely etching an n + type source electrode injection window through an etching process, injecting n + ions, and depositing an oxide layer through chemical vapor deposition;
s12, etching for the fifth time, etching a source contact hole through an etching process, injecting p + ions, and annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃; depositing Ti + TiN, and quickly annealing at low temperature;
s13, arranging a contact window, removing the back of the substrate, arranging a metal material layer and forming a drain electrode; and respectively arranging a source metal and a source oxide layer on the top of the structure finished part to form a source electrode and a grid electrode.
Furthermore, only one high-temperature advance is needed after the first etching, the second etching and the third etching are completed.
Compared with the prior art, the invention has the beneficial effects that:
1. when the n-type drift region and the p-type block bear reverse voltage from a source electrode to a drain electrode, the n-type drift region and the p-type block are mutually exhausted due to a charge balance principle to form a space charge region for bearing the reverse voltage, so that the resistivity of the n-type drift region and the substrate 2 can be reduced, and the lower resistivity of the n-type drift region and the substrate has smaller on-resistance in the on state, and the on-loss is reduced.
2. The transverse p-type block perpendicular to the direction of the strip-shaped polycrystalline layer is arranged in the n-type drift region, the p-type block region of the main pressure bearing layer is perpendicular to the extending direction of the p-type well, the length of the p-type block does not become a factor for limiting the size of a single cell, the size of the single cell is completely determined by the interval length between the polycrystalline layer and the polycrystalline layer, and meanwhile, after the propulsion process steps after the primary etching, the secondary etching and the tertiary etching of the original process are integrated into the third etching, the three propulsion of the original manufacturing process is integrated into one propulsion, so that the process time and the cost are greatly saved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
FIG. 1 is a first structural diagram of step S1 according to the embodiment of the present invention;
FIG. 2 is a first structural diagram of step S2 according to the embodiment of the present invention;
FIG. 3 is a first structural diagram of step S3 according to the embodiment of the present invention;
FIG. 4 is a first structural diagram of step S4 according to the embodiment of the present invention;
FIG. 5 is a first structural diagram of step S5 according to the embodiment of the present invention;
FIG. 6 is a first structural diagram of step S6 according to the embodiment of the present invention;
FIG. 7 is a first structural diagram of step S7 according to the embodiment of the present invention;
FIG. 8 is a first structural diagram of step S8 according to the embodiment of the present invention;
FIG. 9 is a first structural diagram of step S9 according to the embodiment of the present invention;
FIG. 10 is a first structural diagram of step S10 according to the embodiment of the present invention;
FIG. 11 is a first structural diagram of step S11 according to the embodiment of the present invention;
FIG. 12 is a first structural diagram of step S12 according to the embodiment of the present invention;
FIG. 13 is a first structural diagram of step S13 according to the embodiment of the present invention;
FIG. 14 is a cross-sectional view of FIG. 13;
fig. 15 is a schematic flow chart of a method for a multilayer epitaxial super junction structure VDMOS according to an embodiment of the present invention.
Reference numerals: 1-a drain electrode; 2-a substrate; a 3-n type buffer region; a 4-p type block; a 5-p type well; 6-a gate oxide layer; 7-a gate poly layer; 8-source oxide layer; 9-source metal; a 10-n + type source region; 11-p + type short-circuit region.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Referring to the attached drawings 1-14, the structure of the VDMOS with the multi-layer epitaxial super-junction structure comprises a drain electrode 1, a substrate 2 is arranged above the drain electrode 1, an n-type drift region 3 is arranged above the substrate 2, the n-type drift region 3 is formed through five times of epitaxial processes, the n-type drift region 3 is generated on the surface of the substrate 2 through a chemical vapor deposition method, a p-type block 4 is arranged inside the n-type drift region 3, the number of the p-type blocks 4 is at least more than one and is longitudinally and uniformly arranged inside the n-type drift region 3, a p-type well 5 is arranged above the p-type block 4, an n + type source region 10 and a p + type short-circuit region 11 are arranged inside the p-type well 5, a gate oxide layer 6 is arranged on the top of the p-type well 5, a gate polycrystal layer 7 is arranged above the gate oxide layer 6, a source oxide layer 8 is arranged above the gate polycrystal layer 7, a source metal 9 is provided above the source oxide layer 8.
The embodiment of the invention is also realized by the following technical scheme.
Referring to fig. 1-15, the invention also provides a method for a multilayer epitaxial super junction structure VDMOS, which comprises the following steps:
s1, setting a doped region for the first time, and growing an n-type drift region on the surface of the substrate 2 by a chemical vapor deposition method;
s2, carrying out first photoetching, and photoetching a first layer of p-type block 4 injection window at the top of the n-type drift region through a photoetching process; implanting the n-type drift region 3 by an ion implantation method to form a first layer of p-type blocks 4; removing the injection window of the p-type block 4, and injecting the p-type block into the n-type drift region 3 by an ion injection method to form a first layer of n-type blocks;
s3, setting a doping area for the second time, growing an n-type drift area on the surface of the substrate 2 by a chemical vapor deposition method, photoetching for the second time, and photoetching a second layer p-type block 4 injection window on the top of the n-type drift area by a photoetching process; implanting the second layer p-type block 4 into the n-type drift region 3 by an ion implantation method; removing the injection window of the p-type block 4, and injecting the p-type block into the n-type drift region 3 by an ion injection method to form a second layer of n-type blocks;
s4, setting a doping area for the third time, growing an n-type drift area on the surface of the substrate 2 by a chemical vapor deposition method, photoetching for the third time, and photoetching a third layer of p-type block 4 injection window on the top of the n-type drift area by a photoetching process; implanting the third layer of p-type block 4 into the n-type drift region 3 by an ion implantation method; removing the injection window of the p-type block 4, and injecting the p-type block into the n-type drift region 3 by an ion injection method to form a third layer of n-type block;
s5, setting a doping area for the fourth time, growing an n-type drift area on the surface of the substrate 2 by a chemical vapor deposition method, photoetching for the fourth time, and photoetching an injection window of a fourth layer of p-type blocks 4 on the top of the n-type drift area by a photoetching process; implanting the p-type drift region 3 by ion implantation to form a fourth layer p-type block 4; removing the injection window of the p-type block 4, and injecting the p-type block into the n-type drift region 3 by an ion injection method to form a fourth layer of n-type blocks;
s6, arranging a doped region for the fifth time, and growing an n-type drift region on the surface of the substrate 2 by a chemical vapor deposition method;
s7, etching for the first time, growing a 12000A initial oxide layer through high-temperature oxidation, and etching a p-type guard ring injection window on the top of the n-type drift region through an etching process; p-type ion implantation;
s8, etching for the second time, and etching an n-type injection window through the top of the n-type drift region of the etching process; injecting n-type ions, growing a gate oxide layer at high temperature of 1100 ℃, and depositing a polycrystalline layer by chemical vapor deposition;
s9, etching for the third time to form a p-type well 5 injection window on the polycrystalline layer through the etching process, and injecting p-type ions;
s10, high-temperature propelling is carried out at 1150 ℃, the p-type block 4 is connected with the p-type protection ring and the p-type well 5, and only one high-temperature propelling is needed after the first etching, the second etching and the third etching are completed;
s11, etching for the fourth time, namely etching an n + type source electrode injection window through an etching process, injecting n + ions, and depositing an oxide layer through chemical vapor deposition;
s12, etching for the fifth time, etching a source contact hole through an etching process, injecting p + ions, and annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃; depositing Ti + TiN, and quickly annealing at low temperature;
s13, a contact window is arranged, and a metal material layer is arranged on the back of the substrate 2 to form a drain electrode 1; and respectively arranging a source metal 9 and a source oxide layer 8 on the top of the structure finished part to form a source electrode and a grid electrode.
Specifically, when the n-type drift region 3 and the p-type block 4 bear reverse voltage from a source electrode to a drain electrode 1, the n-type drift region 3 and the p-type block 4 are mutually exhausted due to a charge balance principle to form a space charge region for bearing the reverse voltage, so that the resistivity of the n-type drift region 3 and the substrate 2 can be reduced, the lower resistivity of the n-type drift region 3 and the substrate 2 has smaller on-resistance and reduced on-loss when in an on state, the p-type block 4 region of a main bearing layer is vertical to the extending direction of the p-type well 5 by arranging the transverse p-type block 4 which is vertical to the direction of a strip-shaped polycrystalline layer in the n-type drift region 3, so that the length of the p-type block 4 is not a factor for limiting the size of a single cell, the size of the single cell is completely determined by the interval length of the polycrystalline layer and the polycrystalline layer, and the propulsion process steps after the primary, the three-time propulsion of the original manufacturing process flow is integrated into one-time propulsion, so that the process time and the cost are greatly saved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. The utility model provides a structure of super junction structure VDMOS is extended to multilayer, its characterized in that, includes the drain electrode, the top of drain electrode is provided with the substrate, the top of substrate is provided with n type drift region, the inside in n type drift region is provided with p type piece, the top of p type piece is provided with p type well, the inside in p type well is provided with n + type source region and p + type short circuit district, the top of p type well is provided with the grid oxide layer, the top that has the grid oxide layer is provided with the grid polycrystal layer, the top on grid polycrystal layer is provided with the source oxidation layer, the top facility of source oxidation layer has source metal.
2. The structure of the multilayer epitaxial superjunction structure VDMOS of claim 1, wherein: the n-type drift region is formed by five epitaxial processes.
3. The structure of the multilayer epitaxial superjunction structure VDMOS of claim 1, wherein: the number of the p-type blocks is at least more than one, and the p-type blocks are uniformly arranged in the n-type drift region in the longitudinal direction.
4. The structure of the multilayer epitaxial superjunction structure VDMOS of claim 1, wherein: the n-type drift region is generated on the surface of the substrate through a chemical vapor deposition method.
5. A method of applying a multilayer epitaxial superjunction structure VDMOS as claimed in claims 1-4, characterized in that: the method comprises the following steps:
s1, setting a doped region for the first time, and growing an n-type drift region on the surface of the substrate by a chemical vapor deposition method;
s2, carrying out first photoetching, and photoetching a first layer of p-type block injection window at the top of the n-type drift region through a photoetching process; injecting the mixture into the n-type drift region by an ion injection method to form a first layer of p-type blocks; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a first layer of n-type block;
s3, setting a doped region for the second time, and growing an n-type drift region on the surface of the substrate by a chemical vapor deposition method; photoetching for the second time, wherein a second layer of p-type block injection window is photoetched at the top of the n-type drift region through a photoetching process; implanting the p-type drift region into the n-type drift region by an ion implantation method to form a second layer of p-type blocks; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a second layer of n-type blocks;
s4, setting a doping area for the third time, growing an n-type drift area on the surface of the substrate by a chemical vapor deposition method, photoetching for the third time, and photoetching a third layer of p-type block injection window on the top of the n-type drift area by a photoetching process; injecting the mixture into the n-type drift region by an ion injection method to form a third layer of p-type block; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a third layer of n-type block;
s5, setting a doping area for the fourth time, growing an n-type drift area on the surface of the substrate by a chemical vapor deposition method, photoetching for the fourth time, and photoetching a fourth layer of p-type block injection window on the top of the n-type drift area by a photoetching process; implanting the n-type drift region by an ion implantation method to form a fourth layer of p-type block; removing the injection window of the p-type block, and injecting the p-type block into the n-type drift region by an ion injection method to form a fourth layer of n-type blocks;
s6, arranging a doped region for the fifth time, and growing an n-type drift region on the surface of the substrate by a chemical vapor deposition method;
s7, etching for the first time, growing a 12000A initial oxide layer through high-temperature oxidation, and etching a p-type guard ring injection window on the top of the n-type drift region through an etching process; p-type ion implantation;
s8, etching for the second time, and etching an n-type injection window through the top of the n-type drift region of the etching process; injecting n-type ions, growing a gate oxide layer at high temperature of 1100 ℃, and depositing a polycrystalline layer by chemical vapor deposition;
s9, etching a p-type well injection window on the polycrystalline layer through an etching process for the third time, and injecting p-type ions;
s10, performing high-temperature propulsion at 1150 ℃, wherein the p-type block is connected with the p-type guard ring and the p-type trap;
s11, etching for the fourth time, namely etching an n + type source electrode injection window through an etching process, injecting n + ions, and depositing an oxide layer through chemical vapor deposition;
s12, etching for the fifth time, etching a source contact hole through an etching process, injecting p + ions, and annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃; depositing Ti + TiN, and quickly annealing at low temperature;
s13, arranging a contact window, removing the back of the substrate, arranging a metal material layer and forming a drain electrode; and respectively arranging a source metal and a source oxide layer on the top of the structure finished part to form a source electrode and a grid electrode.
6. The structure of the multilayer epitaxial superjunction structure VDMOS of claim 5, wherein: and only one high-temperature propulsion is needed after the first etching, the second etching and the third etching are completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110033982.4A CN112614895A (en) | 2021-01-12 | 2021-01-12 | Structure and method of VDMOS (vertical double-diffused metal oxide semiconductor) with multilayer epitaxial super-junction structure |
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