CN215771157U - Terminal structure of high reliability - Google Patents

Abstract

The utility model provides a high-reliability terminal structure, and relates to the technical field of terminal structures. The semiconductor device comprises a substrate, a drain electrode, an n-type buffer area, a P-type trap, a gate oxide layer and a polycrystalline layer, wherein the P-type trap is arranged regularly inside the n-type buffer area, the gate oxide layer and the polycrystalline layer are arranged above the P-type trap, an n + -type source and a P + -type short-circuit area are arranged inside the P-type trap of the BODY I area and the P-type trap of the BODY II area, source metal electrodes are arranged above the P-type trap of the BODY I area and the P-type trap of the BODY II area, gate metal electrodes are arranged above the P-type trap of the BODY II area and the P-type trap of the RING I area, floating metal electrodes of the RING II area are arranged above the RING II area, and terminal metal electrodes are arranged above the terminal P-type trap. According to the utility model, the BODY I region, the BODY II region, the RING I region and the RING II region are arranged in the drift region and are separated from each other, so that high-temperature reverse bias leakage is effectively reduced.

Description

Terminal structure of high reliability

Technical Field

The utility model relates to the technical field of terminal structures, in particular to a high-reliability terminal structure.

Background

The power electronic device is also called a power semiconductor device and is mainly used for electronic devices with high power in the aspects of electric energy conversion and control circuits of power equipment. On one hand, the power semiconductor device is influenced by power in the working process, heat is generated, the temperature of the device is increased, and the heat is mainly generated at a junction and can cause breakdown leakage. On the other hand, currently, the requirements of the application of the novel power electronic devices in China mainly include a power transistor with acoustic effect (VDMOS) and an insulated gate transistor (IGBT), and the requirements of the application of the electronic devices of automobiles are continuously improved, so that the reliability requirements of the corresponding electronic devices of automobiles are also continuously improved, more and more manufacturers improve and tighten the standard of a high temperature reverse bias experiment (HTRB), and more severe tests are provided for the terminal design of the device products.

SUMMERY OF THE UTILITY MODEL

The utility model provides a high-reliability terminal structure, which can effectively reduce high-temperature reverse bias leakage by arranging the RINGI area and separating the BODYI area, the BODYII area, the RINGI area and the RINGII area.

The specific technical scheme is that the terminal structure of high reliability, including the substrate, the substrate below is provided with the drain electrode, the top is provided with n type buffer, the inside p type trap that is provided with the rule and arranges of n type buffer, p type trap includes: a BODYI region P well, a BODYII region P well, a RINGI region P well, a RINGII region P well and a terminal end P well, a gate oxide layer and a polycrystalline layer are arranged above the P-type well, a PSG protective layer is arranged above the P-type well in the RING I region, the BODYI area P trap and the BODYII area P trap are internally provided with an n + -type source electrode and a P + -type short-circuit area, a source electrode is arranged above the BODYI area P trap and the BODYII area P trap, a grid electrode is arranged above the BODYII area P trap and the RINGI area P trap, the n-type buffer area sequentially comprises a BODYI area, a BODYII area, a RINGI area and a RINGII area from left to right, the BODYI region is formed by BODY injection and JFET injection, the BODY II region is formed by BODY injection, the RINGI area is formed by RING injection and BODY injection, the RINGII area is formed by RING injection, the RINGII area floating metal electrode is arranged above the RINGII area, and the terminal end metal electrode is arranged above the terminal end P well.

Further, the p-type wells are laterally regularly arranged inside the n-type buffer region.

Further, the p + type short-circuit region is located in the middle of the n + type source stage.

Compared with the prior art, the utility model has the beneficial effects that: the special terminal isolation structure enables the device to have small reverse leakage under high reverse voltage, can effectively reduce leakage current under HTRB, improves the high-temperature reliability of products, and does not increase the original photoetching layer number or the cost.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the utility model and, together with the description, serve to explain the utility model and not to limit the utility model. In the drawings:

fig. 1 is a schematic structural diagram of the implementation of step S1 disclosed in the embodiment of the present invention;

FIG. 2 is a schematic diagram of a corresponding structure implemented in step S2 according to the embodiment of the present invention;

FIG. 3 is a schematic diagram of a corresponding structure implemented in step S3 according to the embodiment of the present invention;

FIG. 4 is a schematic diagram of the corresponding structure implemented in steps S4, S5, and S6 according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of a corresponding structure implemented in step S7 according to the embodiment of the present invention;

FIG. 6 is a schematic diagram of a corresponding structure implemented in step S8 according to the embodiment of the present invention;

FIG. 7 is a schematic diagram of a BODY region P-well structure according to the present invention.

Wherein: 1. the transistor comprises a drain electrode, 2, a substrate, 3, an n-type buffer region, 4, a RING II region P well, 5, a RING I region P well, 6, a BODY II region P well, 7, a BODY I region P well, 8, a terminal end P well, 9, a gate oxide layer, 10, a polycrystalline layer, 11, a PSG protective layer, 12, a RING II region floating metal electrode, 13, a source metal electrode, 14, a gate metal electrode, 15, a terminal end metal electrode, 16, an initial oxide layer, 17, an n + type source, 18 and a P + type short-circuit region.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.

In the description of the present invention, it should be noted that the terms "inner", "outer", "left" and "right" are used for indicating the orientation or positional relationship based on the positional relationship shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present invention.

The utility model is described below with reference to figures 1-7:

example (b): the utility model provides a high reliability's terminal structure, includes substrate 2, substrate 2 below is provided with drain electrode 1, the top is provided with n type buffer 3, the inside p type trap that sets up regularly arranging of n type buffer 3, the p type trap includes: a BODY I region P well 7, a BODY II region P well 6, a RING I region P well 5, a RING II region P well 4 and a terminal end P well 8, wherein a gate oxide layer 9 and a polycrystalline layer 10 are arranged above the P-type well, a PSG protective layer 11 is arranged above the RING I region P well 5, an n + -type source 17 and a P + -type short-circuit region 18 are arranged in the BODY I region P well 7 and the BODY II region P well 6, source metal electrodes 13 are arranged above the BODY I region P well 7 and the BODY II region P well 6, gate metal electrodes 14 are arranged above the BODY II region P well 6 and the RING I region P well 5, the n-type buffer region 3 is a BODY I region, a BODY II region, a RING I region and a RING II region in sequence from left to right, the BODY I region is formed by BODY injection and JFET injection, the RING I region is formed by RING injection and RING injection, the RING II region is formed by RING injection, a RING II region floating metal electrode 12 is disposed above the RING II region, and a terminal end metal electrode 15 is disposed above the terminal end P-well 8.

Further, the p-type wells are laterally regularly arranged inside the n-type buffer region 3.

Further, the p + -type short-circuiting region 18 is located in the middle of the n + -type source stage 17.

The manufacturing method of the trench IGBT structure described in the application comprises the following steps:

s1, setting a doped region, growing the n-type buffer region 3 on the surface of the substrate 2 by a chemical vapor deposition method,

s2, carrying out first photoetching, etching a P-type guard RING injection window on the top of the n-type buffer region 3 on the 12000A initial oxidation layer 16 grown on the n-type buffer region 3 at a high temperature through photoetching and etching processes, injecting P-type ions into the n-type buffer region 3 through an ion injection method, annealing to form a RING II region P well 4,

s3, carrying out second photoetching, photoetching and etching the left side of the top of the N-type buffer area 3 to form a first layer of N-type well injection window, annealing to form an N-type well, injecting N-type ions into the N-type buffer area 3 to form an N-type well, wherein the N-type ions can diffuse to increase the concentration in the N-type buffer area 3 to form a homogeneous structure, a new junction can not be generated, a new heat accumulation part can not be generated, the N-type well is not shown in the figure,

s4, growing the gate oxide layer 9 above the n-type buffer region 3 at a high temperature of 1100 ℃, depositing the polycrystalline layer 10 by chemical vapor deposition,

s5, carrying out third photoetching, etching a P-type well injection window on the polycrystalline layer 10 through photoetching and etching processes, carrying out P-type ion injection, carrying out high-temperature annealing to form the BODY I region P well 7, the BODY II region P well 6 and the RING I region P well 5,

s6, performing fourth photoetching, respectively photoetching n + type source injection windows on the upper side parts of the BODY I region P well 7 and the BODY II region P well 6 through a photoetching process, performing n + ion injection to form the n + type source 17, performing chemical vapor deposition on an oxide layer,

s7, fifth photoetching, photoetching and etching a source contact hole in the middle of the n + type source electrode 17 through photoetching and etching processes, injecting p + ions, annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃ to form the p + type short circuit region 18,

and S8, setting a contact window, removing the metal material layer arranged on the back of the substrate 2 to form the drain electrode 1, respectively arranging a metal layer and an oxidation layer on the top of the structure finished part, and respectively forming a PSG protective layer 11, a RING II area floating metal electrode 12, a source metal electrode 13, a grid metal electrode 14 and a terminal end metal electrode 15 on the metal layer arranged on the oxidation layer.

The unique terminal design in this application, BODY I district, BODY II district, RING I district and RING II district structure separation, wherein, BODY I district is injected into with the JFET by BODY and is formed, BODY II district is injected into and is formed by BODY, RING I district is injected into and is formed by RING, RING II district is injected into and is formed by RING, adjacent each interval has the transition nature on the material, the P trap border department PN junction of each district, and heat-conduction is good, and this special "terminal isolation" structure makes the device have less reverse electric leakage under high reverse voltage, can effectually reduce HTRB (high temperature reverse bias) lower leakage current, improves product high temperature reliability, and the manufacturing method that adopts does not increase original photoetching number of piles, also does not increase the cost.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any person skilled in the art may modify or modify the technical details disclosed above into equivalent embodiments with equivalent variations. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.

Claims (3)

1. The utility model provides a high reliability's terminal structure, its characterized in that includes substrate (2), substrate (2) below is provided with drain electrode (1), the top is provided with n type buffer (3), n type buffer (3) inside is provided with the p type trap that the rule was arranged, the p type trap includes: the semiconductor device comprises a BODY I region P well (7), a BODY II region P well (6), a RING I region P well (5), a RING II region P well (4) and a terminal tail end P well (8), wherein a gate oxide layer (9) and a polycrystalline layer (10) are arranged above the P-type well, a PSG protective layer (11) is arranged above the RING I region P well (5), an n + -type source (17) and a P + -type short-circuit region (18) are arranged in the BODY I region P well (7) and the BODY II region P well (6), a source metal electrode (13) is arranged above the BODY I region P well (7) and the BODY II region P well (6), a gate metal electrode (14) is arranged above the BODY II region P well (6) and the RING I region P well (5),

the n-type buffer area (3) is sequentially provided with a BODY I area, a BODY II area, a RING I area and a RING II area from left to right, the BODY I area is formed by BODY injection and JFET injection, the BODY II area is formed by BODY injection, the RING I area is formed by RING injection and BODY injection, the RING II area is formed by RING injection, a RING II area floating metal electrode (12) is arranged above the RING II area, and a terminal end metal electrode (15) is arranged above the terminal end P well (8).

2. A highly reliable termination structure according to claim 1, characterized in that said p-type wells are laterally regularly arranged inside said n-type buffer (3).

3. A highly reliable termination structure according to claim 1, characterized in that said p + -type short-circuiting region (18) is located in the middle of said n + -type source (17).

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