CN111081759B - Enhanced silicon carbide MOSFET device and manufacturing method thereof - Google Patents

Enhanced silicon carbide MOSFET device and manufacturing method thereof Download PDF

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CN111081759B
CN111081759B CN201911258411.XA CN201911258411A CN111081759B CN 111081759 B CN111081759 B CN 111081759B CN 201911258411 A CN201911258411 A CN 201911258411A CN 111081759 B CN111081759 B CN 111081759B
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吴苏州
李晓云
杨高洁
叶怀宇
张国旗
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Southwest University of Science and Technology
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Shenzhen Third Generation Semiconductor Research Institute
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Abstract

The invention discloses an enhanced silicon carbide MOSFET device, which sequentially comprises the following components from bottom to top: the device comprises a back metal, an N + type heavily doped SiC substrate, an N-epitaxial layer, an insulating medium layer and a front metal. The Schottky diode is integrated into the MOSFET device, and the area of the Schottky barrier metal layer is flexibly increased or decreased to adjust and adapt the current and the specification of the MOSFET and the Schottky diode, so that the switching speed of the MOSFET is increased, the switching loss is reduced, the performance and the reliability of the device can be greatly improved, and the application cost of the device is reduced. The design of the groove type SiC MOSFET is adopted, and a conductive channel is changed from the traditional horizontal direction to the vertical direction, so that the JFET effect among the cells of the traditional MOSFET is eliminated, and the current capacity of the device is improved. The gate bottom P region at the bottom of the trench can protect and weaken the electric field at the bottom of the trench, plays a certain role in electrostatic shielding of gate oxide at the bottom of the trench, and improves the reliability of devices. Meanwhile, the device has certain help for resisting the voltage.

Description

Enhanced silicon carbide MOSFET device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor chip manufacturing processes, and particularly relates to an enhanced silicon carbide MOSFET device and a manufacturing method thereof.
Background
The third generation semiconductor material, silicon carbide (SiC), has many characteristics different from the traditional silicon semiconductor material, and the energy band gap of the third generation semiconductor material is 2.8 times of that of silicon, and reaches 3.09 electron volts; the dielectric breakdown field strength is 5.3 times that of silicon and is as high as 3.2MV/cm, and the thermal conductivity is 3.3 times that of silicon and is 49w/cm K. Therefore, the material becomes an ideal semiconductor material in the application occasions of high temperature, high frequency, high power and radiation resistance. Since the silicon carbide power device can remarkably reduce the energy consumption of electronic equipment, the silicon carbide power device is widely applied in the field of new energy.
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a core device of the next generation of high-efficiency power electronic device technology. Compared with a Si-MOSFET, the SiC MOSFET has smaller on-resistance, higher switching voltage, higher application frequency and better temperature performance, and is particularly suitable for power switch application. After years of research in the field of SiC MOSFETs, some prior art has been able to produce SiC MOSFET devices. In many practical application scenarios, the problems of slow switching speed and excessive switching loss of the SiC MOSFET device exist, and the current capability of the device is not reliable enough. Therefore, a solution is proposed in the prior art to operate a SiC MOSFET device with a diode connected in anti-parallel. Therefore, the switching speed of the switching device can be increased, the switching loss is reduced, and the current capability and reliability of the device are improved.
However, the following problems exist in the prior art:
1. in the prior art, the source electrode and the p-well are often electrically connected and short-circuited, and the design mode of the device is actually equivalent to the parallel connection of a reverse bias diode between the source electrode and the channel. Due to the fact that the forbidden band width of the SiC material is high, the starting voltage of the PN diode connected in anti-parallel is very high, and corresponding loss is large.
2. The current driving capability of the device is reduced by the anti-parallel PN diode in the prior art, and the loss is increased at the same time.
Therefore, a solution is needed to increase the switching speed of the device, reduce the switching loss, and improve the current driving capability of the device. The overall reliability of the device is improved.
Disclosure of Invention
Aiming at the problems in the prior art, the invention discloses an enhanced silicon carbide MOSFET and a manufacturing method thereof. The enhancement type silicon carbide MOSFET device adopts a groove type structure, compared with a traditional plane type structure, a conducting channel of the enhancement type silicon carbide MOSFET device is changed into a vertical channel from a horizontal direction, a parasitic JFET (junction field effect transistor) resistance between a primitive cell and a primitive cell changes a Schottky device, and the positive effects of increasing the switching speed, reducing the switching loss and the like are achieved for the silicon carbide MOSFET device. And because of the difference of the structure, the parasitic JFET resistance in the traditional structure does not exist any more, thereby playing the role of reducing the on-resistance of the MOSFET and improving the current capability of the MOSFET.
According to the invention, the enhanced silicon carbide MOSFET device is characterized by comprising the following components in sequence from bottom to top: a back metal formed from a combination of metal Ti, metal Ni, and metal Ag; an N + type heavily doped SiC substrate; the upper surface of the N-epitaxial layer comprises a plurality of P-type body regions which are arranged in parallel at intervals in the horizontal direction, the P-type body regions are formed downwards on the upper surface of the N-epitaxial layer and comprise first ions, and the P-type body regions are connected through Schottky barrier metal layers; a central region of the at least three P-type body region upper surfaces includes an N + source formed downward in the P-type body region upper surface central region, the N + source including second ions; a groove is arranged below the central region of the N + source electrode, and the depth of the groove is deeper than the P-type body region but is not contacted with the N + type heavily doped SiC substrate; the groove comprises a gate bottom P region, the gate bottom P region is arranged at the bottom of the groove and comprises third ions; the trench further includes a polysilicon gate, the polysilicon gate being full of polysiliconA plurality of grooves; the N-epitaxial layer and the groove also comprise gate oxide layers, and the gate oxide layers grow on the inner wall of the groove; the outer side of the N + source electrode on the upper surface of the P type body region also comprises a P type body region contact layer, the P type body region contact layer is formed by downward arrangement on the upper surface of the P type body region, and the P type body region contact layer comprises fourth ions; the P-type body region further comprises a P + buried layer, the P + buried layer is arranged in the center of the P-type body region and outside the groove, and the P + buried layer comprises fifth ions; an ohmic contact metal layer is arranged above the N + source electrode, the P-type body region contact layer and the Schottky barrier metal layer; an insulating dielectric layer made of SiO2Forming; the insulating medium layer is arranged above the polycrystalline silicon grid and the P-type body region contact layer; a front metal consisting of Al and having a thickness of 1-5 μm.
Preferably, the silicon carbide single crystal material used by the silicon carbide substrate can be one of 2H-SiC single crystal and 4H-SiC single crystal, and the doping concentration of the N + type heavily doped SiC substrate is 3 multiplied by 1019-3×1020ion/CM3。
Preferably, the doping concentration of the N-epitaxial layer is 1 × 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doped impurity is nitrogen element.
Preferably, the depth of the P-type body region is 1-3 μm, the first ions are boron ions, the depth of the N + source electrode is 0.2-0.8 μm, and the second ions are phosphorus ions.
Preferably, the third ions, the fourth ions and the fifth ions are boron ions.
Preferably, the doping concentration of the polysilicon is more than 1 × 1020ion/CM3。
Preferably, the thickness of the gate oxide layer is 0.04-0.1 μm.
Preferably, the thickness of the insulating medium layer is
Figure BDA0002310926030000031
The Schottky barrier metal layer is TiMo or TiW, and the Schottky barrier metal layer is made of Ti, Mo or Ti, W, Ti, or Ti, V, or Ti, or a combination thereof, or a combination of a metal or a combination of a metal or a combination of a metal or a combination thereof, or a metal or a combination of a metal or a combination thereof, or a metal orThe thickness of the special base barrier metal layer is
Figure BDA0002310926030000032
The thickness of the ohmic contact metal layer is
Figure BDA0002310926030000033
According to one aspect of the invention, a method of fabricating an enhanced silicon carbide MOSFET device comprises: step 1: selecting an N + type heavily doped SiC substrate, and growing an N-epitaxial layer on the upper surface of the N + type heavily doped SiC substrate; step 2: injecting first ions downwards into the upper surface of the N-epitaxial layer through photoetching and ion injection modes to form at least three P-type body regions which are arranged in parallel at intervals in the horizontal direction, and injecting second ions downwards into central regions of the upper surfaces of the at least three P-type body regions through ion injection modes to form an N + source electrode; and step 3: forming a groove in the central area of the N + source electrode by downward etching in a groove photoetching and groove etching mode, wherein the depth of the groove is 1.2-1.5 times of that of the P-type body area; and 4, step 4: injecting third ions downwards at the bottom of the groove in an ion injection mode to form a grid bottom P region; and 5: growing a first gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a rapid thermal oxidation mode for 5-10 times, stripping the first gate oxide layer by a wet etching mode, and then forming a second gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a furnace tube thermal oxidation mode; step 6: depositing polycrystalline silicon on the upper surface of the N-epitaxial layer and in the groove, and etching the polycrystalline silicon on the upper surface of the N-epitaxial layer through a CMP (chemical mechanical polishing) process; and 7: injecting fourth ions on the upper surface of the N-epitaxial layer below the second gate oxide layer to form a P-type body region contact layer; and 8: growing an insulating medium layer on the upper surface of the second gate oxide layer, wherein the insulating medium layer is made of SiO2Composition is carried out; and step 9: etching the insulating medium layer by photoetching and etching modes to form at least six channels, wherein the channels lead to the upper surface of the P-type body region and the upper surface of the N + source electrode, and the region formed by the at least six channels is a first region; step 10: implanting a fifth ion implantation on the upper surface of the P-type body region to which the channel leadsForming a P + buried layer by ions, wherein the implantation depth of the fifth ions is 0.4-0.6 times of the depth of the P-type body region; step 11: etching through the P-type body region contact layer, the second gate oxide layer and the insulating medium layer above the region between the P-type body regions in a dry etching mode to form a second region, depositing barrier metal on the second region to form a Schottky barrier metal layer, and depositing N-type body region contact layer, the second gate oxide layer and the insulating medium layer after the deposition is finished2Carrying out high-temperature annealing in the atmosphere; step 12: depositing metal titanium on the first area and the second area to form an ohmic contact metal layer; step 13: and growing Al on the ohmic contact metal layer and the insulating medium layer to form front metal.
Preferably, the first ions are boron ions, the implantation times of the first ions are multiple, and the single implantation dosage is 2 × 1013-1×1014ion/CM2Cumulative implant dose of 1X 1014-5×1014ion/CM2The implantation energy is 50Kev-1.5Mev, and the implantation depth is 1 μm-2.5 μm.
Preferably, the second ions are phosphorus ions, and the implantation dose of the second ions is 3 × 1015-2×1016ion/CM2The implantation energy is 150Kev-500Kev, and the implantation depth is 0.3 μm-0.5 μm.
Preferably, the P + source electrode and the P type body region are advanced at high temperature, wherein the temperature of the advanced high temperature is 1700-1900 ℃, and the time of the advanced high temperature is 60-300 min.
Preferably, the depth of the groove is 1-4 μm, the width is 0.4-1 μm, and the bottom of the groove needs to be smoothed after the groove is etched and etched.
Preferably, the third ions are boron ions, and the implantation dose is 1 × 1013-1×1014ion/CM2The implantation energy is 30-80 Kev.
Preferably, the time of the rapid thermal oxidation mode is 30S-2min, and the thickness of the single rapid thermal oxidation is less than
Figure BDA0002310926030000051
Fast accumulationThermal oxidation thickness greater than
Figure BDA0002310926030000052
Preferably, the furnace tube thermal oxidation mode adopts CL-based gas, and the thickness of the second oxide layer formed by the furnace tube thermal oxidation mode is 0.04-0.1 μm.
Preferably, the impurity concentration of the polycrystalline silicon is 1 × 1020ion/CM3Above, the thickness of the polysilicon is
Figure BDA0002310926030000053
Preferably, the fourth ion is implanted at an energy of 50 to 150Kev and at an implant dose of 1X 1013-5×1013ion/CM2。
Preferably, the thickness of the insulating medium layer is
Figure BDA0002310926030000054
Preferably, the implantation energy of the fifth ions is 300-800Kev, and the implantation dose is 2 × 1013-2×1014ion/CM2。
Preferably, after the deposition of the ohmic contact metal layer is finished, high-temperature annealing is carried out, wherein the annealing temperature is 900-1100 ℃.
Has the advantages that:
compared with the prior art, the invention has the main advantages that:
(1) the schottky diode is integrated into the MOSFET device by a unique design. And the current and specification of the MOSFET and the Schottky diode can be adjusted and adapted by flexibly increasing and decreasing the area of the Schottky barrier metal layer. Therefore, the functions of increasing the switching speed of the MOSFET, reducing the switching loss and the like are achieved, the performance and the reliability of the device can be greatly improved, and the application cost of the device is reduced.
(2) The design of the groove type SiC MOSFET is adopted, and a conductive channel is changed from the traditional horizontal direction to the vertical direction, so that the JFET effect among the cells of the traditional MOSFET is eliminated, and the current capacity of the device is improved. A JFET area of a traditional MOS is ingeniously converted into a Schottky area, and the effects of protecting devices and improving the performance are achieved.
(3) Ohmic contact and Schottky contact are separately manufactured through a Lift-off process, and the optimal characteristics of the two contacts (ohmic contact and Schottky contact) can be respectively debugged on the premise of not additionally increasing a photoetching plate.
(4) The gate bottom P region at the bottom of the trench can protect and weaken the electric field at the bottom of the trench, plays a certain role in electrostatic shielding of the gate oxide at the bottom of the trench, and improves the reliability of the device. Meanwhile, the voltage resistance of the device is also helped to a certain extent.
(5) The Schottky barrier metal layer is subjected to chemically-dominant ICP plasma coupled etching, so that interface damage can be reduced. And dry etching can remove surface SiO by etching2The Schottky device comprises a material, a gate oxide layer and a P-type body region contact layer, so that an interface state caused by an oxidation step and an ion implantation step is removed, and the performance of the Schottky device is improved finally.
(6) The P-type impurity injection below the contact holes of the N + source and the P-type body region can reduce the Pbase resistance (P-based resistance), and can effectively improve the anti-surge capability of the device. The implantation step also does not need to add an additional mask.
Drawings
FIG. 1 is a schematic diagram of an enhanced silicon carbide MOSFET device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an enhanced silicon carbide MOSFET device in accordance with an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a device including an N + type heavily doped SiC substrate and an N-epitaxial layer in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a device structure including a P-type body region according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a device structure including N + source formed in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of a device structure including a trench in an embodiment of the present invention;
FIG. 7 is a schematic diagram of a device structure including a P region at the bottom of a gate in an embodiment of the present invention;
FIG. 8 is a schematic diagram of a device structure including a gate oxide layer in an embodiment of the invention;
fig. 9 is a schematic diagram of a device structure including a polysilicon gate in an embodiment of the invention;
FIG. 10 is a diagram of the structure of a device with surface polysilicon etched away in accordance with an embodiment of the present invention;
FIG. 11 is a schematic diagram of a device structure including a P-type body region contact layer in an embodiment of the invention;
FIG. 12 is a schematic diagram of a device structure including an insulating dielectric layer in an embodiment of the invention;
FIG. 13 is a schematic diagram of a device structure including a channel in an embodiment of the invention;
fig. 14 is a schematic view of a device structure including a P + buried layer in an embodiment of the present invention;
FIG. 15 is a schematic structural diagram of a device etched by a dry etching method in the embodiment of the present invention;
FIG. 16 is a schematic diagram of a device structure including a Schottky barrier metal layer in an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a device including an ohmic contact metal layer and a front metal in an embodiment of the invention.
The structure comprises a back metal 1, an N + type heavily doped SiC substrate 2, an N-epitaxial layer 3, a P type body region 4, an N + source electrode 5, a groove 6, a gate oxide layer 7, a polysilicon gate 8, a P type body region contact layer 9, a P + buried layer 10, an insulating dielectric layer 11, a Schottky barrier metal layer 12, an ohmic contact metal layer 13, a front metal 14 and a gate bottom P region 15.
Detailed Description
The content of the invention will now be discussed with reference to a number of exemplary embodiments. It should be understood that these embodiments are discussed only to enable those of ordinary skill in the art to better understand and thus implement the context of the present invention, and are not meant to imply any limitations on the scope of the invention.
As used herein, the term "include" and its variants are to be read as open-ended terms meaning "including, but not limited to. The term "based on" is to be read as "based, at least in part, on". The terms "one embodiment" and "an embodiment" are to be read as "at least one embodiment". The term "another embodiment" is to be read as "at least one other embodiment".
The invention provides an enhanced silicon carbide MOSFET device and a manufacturing method thereof, aiming at the problems that in the prior art, a reverse bias diode is connected in parallel between a source electrode and a channel, so that the turn-on voltage of the device can be improved, and the current driving capability of the device can be reduced. The device is a groove type MOSFET device, and as shown in figure 2, the SiC Schottky device is arranged in the device in parallel, so that the switching speed of the device is increased, the switching loss is reduced, the current driving capability of the device is improved, and the overall reliability of the device is improved. An enhanced silicon carbide MOSFET device comprising, in order from bottom to top:
the back metal 1 is formed by combining metal Ti, metal Ni and metal Ag, and the back of the SiC substrate needs to be ground and thinned before the metal is deposited on the back of the SiC substrate; annealing of the device as a whole is required after the deposition of the back metal 1.
As shown in FIG. 3, the N + type heavily doped SiC substrate 2 can be 2H SiC substrate or 4H SiC substrate, and the doping concentration of the N + type heavily doped substrate is about 3X 1019-3×1020ion/CM3。
An N-epitaxial layer 3 with a doping concentration of 1 × 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doping impurity is nitrogen element. As shown in fig. 4, the upper surface of N-epitaxial layer 3 includes a plurality of P-type body regions arranged in parallel and at intervals in the horizontal direction, and the number of the P-type body regions is not limited and may be arranged according to the size of the device. The P-type body region 4 is formed by injecting first ions downwards on the upper surface of the N-epitaxial layer 3 in a photoetching and ion injection mode, the first ions are preferably boron ions, and the depth of the P-type body region 4 is 1-3 mu m.
As shown in fig. 5, the central region of the upper surfaces of at least three P type body regions 4 includes an N + source 5, the N + source 5 is formed by etching and implanting second ions, preferably phosphorus ions, into the central region of the upper surfaces of the P type body regions 4 by photolithography and ion implantation, and the depth of the N + source 5 is 0.2-0.8 μm.
As shown in fig. 6, the central region of the N + source 5 includes a trench 6, the trench 6 is formed by etching downwards in the central region of the upper surface of the N + source 5 by means of trench lithography and trench etching, the depth of the trench 6 is 1.2-1.5 times of the depth of the P-type body region, the depth is 1-4 μm, and the width is 0.4-1 μm.
As shown in fig. 7, the trench 6 includes a gate bottom P region 15, and the gate bottom P region 15 is formed by implanting third ions, preferably boron ions, downward at the bottom of the trench 6 by means of ion implantation; the groove 6 also comprises a polysilicon grid 8, the polysilicon grid 8 is filled in the whole groove in an injection mode, and the doping concentration of the polysilicon is more than 1 multiplied by 1020ion/CM3(ii) a As shown in fig. 8, the trench 6 and the N-epitaxial layer further include a gate oxide layer 7, the gate oxide layer 7 is grown on the upper surface of the N-epitaxial layer 3 and the inner wall of the trench 6 in a furnace tube thermal oxidation manner, and the thickness of the gate oxide layer 7 is 0.04-0.1 μm.
As shown in fig. 11, the upper surface of the N-epitaxial layer 3 further includes a P-type body region contact layer 9, the P-type body region contact layer 9 is formed by implanting fourth ions, preferably boron ions, below the gate oxide layer 7 by means of ion implantation;
as shown in fig. 14, the P-type body region 4 further includes a P + buried layer 10, the P + buried layer 10 is formed by implanting fifth ions, preferably boron ions, downward on the upper surface of the P-type body region 4 by means of ion implantation, and the implantation depth of the P + buried layer 10 is 0.4-0.6 times the depth of the P-type body region 4;
as shown in fig. 12, the insulating dielectric layer 11 is composed of SiO 2; the insulating medium layer 11 comprises a Schottky barrier metal layer 12 and an ohmic contact metal layer 13; as shown in fig. 16, a schottky barrier metal layer 12 is deposited on the upper surface of the N-epitaxial layer 3 by photolithography and etching and contacts the N-epitaxial layer 3, the schottky barrier metal layer 12 is disposed between the P-type body regions 4; as shown in fig. 17, the ohmic contact metal layer 13 is disposed in the insulating dielectric layer 11 where SiO2 is absent; the thickness of the insulating dielectric layer 11 is
Figure BDA0002310926030000091
The Schottky barrier metal layer 12 isTiMo or TiW, the thickness of the Schottky barrier metal layer 12 is
Figure BDA0002310926030000092
The ohmic contact metal layer 13 is Ti with a thickness of
Figure BDA0002310926030000093
As shown in fig. 17, the front metal 14 is composed of Al and has a thickness of 1 to 5 μm.
The invention discloses a preparation method of an enhanced silicon carbide MOSFET device, which comprises the following steps:
step 1: selecting an N + type heavily doped SiC substrate 2, and growing an N-epitaxial layer 3 on the upper surface of the N + type heavily doped SiC substrate; the N + type heavily doped SiC substrate 2 can be a 2H SiC substrate or a 4H SiC substrate. The doping concentration of the N + type heavily doped SiC substrate 2 is about 3X 1019-3×1020ion/CM3The doping concentration of the N-epitaxial layer 3 is 1 x 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doping impurity is nitrogen element. According to the doping concentration and the thickness of the N-epitaxial layer 3, the voltage resistance of about 1000-3000V can be realized.
And 2, step: first ions, preferably boron ions, are implanted downwards on the upper surface of the N-epitaxial layer 3 through photoetching and ion implantation to form at least three P-type body regions 4 which are arranged in parallel at intervals in the horizontal direction, the implantation mode is multiple times of implantation, and the implantation depth of each time is different, so that impurities at each position in the vertical direction are uniformly distributed. Preferably, the number of injections is 3-5. Single injection dose is 2X 1013-1×1014Ion/cm2In the meantime. The cumulative injection dose is 1 × 1014-5×1014Ion/cm2In the meantime. The implantation energy is 50Kev-1.5Mev, and the energy gradients of all stages are consistent. The implantation depth is between 1um-2.5um from the surface to the bottom. Forming N + source 5 by implanting second ions (phosphorus ions) in the central region of the upper surface of P-type body region 4, preferably at a dose of 3 × 1015-2×1016ion/CM2In the meantime. Injection junctionThe depth is between 0.3 μm and 0.5 μm, and the injection energy is between 150 and 500 kev. Then, the N + source 5 and the P-type body 4 are advanced at high temperature, wherein the advancing temperature is 1700-1900 ℃, and the advancing time is 60-300 min. After the push-in is finished, the junction depth of the P type body region is 1-3 mu m, and the junction depth of the N type source region is 0.2-0.8 mu m.
And 3, step 3: photoresist is coated on the upper surface of the N-epitaxial layer 3 except the central area of the N + source electrode 5, a groove 6 is formed in the central area by means of groove photoetching and groove etching, the depth of the groove 6 is 1.2-1.5 times of the depth of the P type body area 4, and the etching gas is preferably F-based gas, such as CF4, C2F6, CHF3 and the like. And after the etching is finished, the bottom of the groove 6 is subjected to smooth treatment, so that the bottom of the groove 6 is smoother, an electric field at the bottom of the groove 6 can be weakened, and the surface states of SiC and oxide at the bottom are reduced.
And 4, step 4: injecting third ions downwards at the bottom of the groove 6 in an ion injection mode to form a gate bottom P region, wherein the third ions are preferably boron ions; the implantation dose is 1 × 1013-1×1014ion/CM2The implantation energy is 30-80 Kev. And after the injection is finished, removing the photoresist. And 4, the third ions injected in the step 4 can participate in depletion when the device is reversely biased, so that the effect of weakening the electric field at the bottom of the gate oxide is achieved, and the voltage resistance and the reliability of the device can be improved.
And 5: as shown in fig. 8, a first gate oxide layer is grown on the upper surface of the N-epitaxial layer 4 and the inner wall of the trench 6 by multiple rapid thermal oxidation. The multiple rapid thermal oxidation is preferably performed 5-10 times, and the multiple rapid thermal oxidation increases the manufacturing cost of the device. Then stripping the first gate oxide layer in a wet etching mode, and then forming a second gate oxide layer 7 on the upper surface of the N-epitaxial layer and the inner wall of the groove in a furnace tube thermal oxidation mode; the time of the rapid thermal oxidation mode is usually 30s-2min, and the thickness of the single thermal oxidation is
Figure BDA0002310926030000111
Within. Cumulative thermal oxide thickness of
Figure BDA0002310926030000112
As described above. The inner wall of the groove 6 is eventually made smoother,fewer interface states. Then, a gate oxide layer 7 is grown by adopting a furnace tube thermal oxidation method, and CL-based gas can be introduced for oxidation in order to further improve the gate oxide quality. The final oxide layer thickness is between 0.04-0.1 μm. During the oxidation process, the third ions at the bottom are activated.
Step 6: as shown in FIG. 9, polysilicon is deposited on the upper surface of the N-epitaxial layer 3 and in the trenches to form polysilicon gates 7, the polysilicon having an impurity concentration of 1X 1020ion/CM3Above, the thickness of the polysilicon is
Figure BDA0002310926030000113
Meanwhile, as shown in fig. 10, the polysilicon on the upper surface of the N-epitaxial layer is etched by a CMP process;
and 7: as shown in fig. 11, fourth ions are implanted into the upper surface of the N-epitaxial layer 3 below the second gate oxide layer 7 to form a P-type body region contact layer 9, the fourth ions are preferably boron ions, the implantation energy is just enough to penetrate through the gate oxide film, and the optimized energy is about 50 to 150 Kev; the implantation dosage is 1 × 1013-5×1013ion/CM2In the meantime. The fourth ions can make the surface concentration of the P-type body region 4 more concentrated, and make ohmic contact easier to form in the subsequent process. The N + source 5 and the polysilicon gate 8 are still N-type because the N-type impurity concentration is much higher than the P-type impurity concentration.
And step 8: as shown in fig. 12, an insulating dielectric layer 10 is grown on the upper surface of the gate oxide layer 7, and the insulating dielectric layer 10 is composed of SiO 2; the growth mode adopts LPCVD (low pressure chemical vapor deposition), and the thickness of the dielectric layer is
Figure BDA0002310926030000114
In between.
And step 9: as shown in fig. 13, at least six channels are formed by etching the insulating medium layer 10 through photolithography and etching, the channels lead to the upper surface of the P-type body region 4 and the upper surface of the N + source 5, and a region formed by the six channels is a first region.
Step 10: as shown in fig. 14, a fifth ion implantation is performed on the top surface of the P-type body region 4 to which the via leadsForming a P + buried layer by ions; preferably, the fifth ions are boron ions; the implantation depth of the fifth ions is 0.4-0.6 times of the depth of the P type body region 4 and is deeper than the N + source electrode 5; the implantation energy is between 300 and 800Kev, and the implanted impurity dose is 2 x 1013-2×1014ion/CM2In between. The fifth ions injected in the step can reduce the internal resistance of the base region, so that the parasitic NPN triode is prevented from being started, the EAS resistance of the device is improved, the reliability of the device is improved, and the voltage capability and the current capability of the MOSFET cannot be influenced because the P + buried layer 10 has a certain distance from the vertical conducting channel.
Step 11: as shown in fig. 15, the second region is formed by etching through the P-type body region contact layer 9, the second gate oxide layer and the insulating dielectric layer 10 above the region between the P-type body regions 4 by means of dry etching. The dry etching method comprises the following steps: the insulating medium layer 10 is etched in an EOP mode, gaseous byproducts are generated in the EOP mode when dry plasma etching is carried out, the generated byproducts are different when different materials are etched, and when one material is etched, the signal strength of the byproducts is detected through a sensor, so that the etching completion can be known. And after the etching in the EOP mode is finished, etching the oxide layer 7 and the P type body region contact layer 9 by adopting a plasma coupled ICP machine, wherein the general etching depth is within 0.5 um. As shown in FIG. 16, a barrier metal is deposited on the second region to form a Schottky barrier metal layer 12, and after the deposition is completed, N is added2And carrying out high-temperature annealing in the atmosphere.
Step 12: as shown in fig. 17, titanium metal is deposited on the first region and the second region to form an ohmic contact metal layer 13.
Step 13: as shown in fig. 17, Al is grown over the ohmic contact metal layer and the insulating dielectric layer to form a front metal.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (22)

1. An enhanced silicon carbide MOSFET device, comprising:
the upper surface of the N-epitaxial layer comprises a plurality of P-type body regions which are arranged in parallel at intervals in the horizontal direction, the P-type body regions are formed downwards on the upper surface of the N-epitaxial layer and comprise first ions, and the P-type body regions are connected through Schottky barrier metal layers;
a central region of the at least three P-type body region upper surfaces including an N + source formed downward in the P-type body region upper surface central region, the N + source including a second ion;
a groove is arranged below the central region of the N + source electrode, and the depth of the groove is deeper than the P-type body region but is not in contact with the N + type heavily doped SiC substrate; the groove comprises a gate bottom P region, the gate bottom P region is arranged at the bottom of the groove, and the gate bottom P region comprises third ions;
the groove also comprises a polysilicon grid, and the polysilicon grid is filled in the whole groove; the N-epitaxial layer and the groove also comprise a gate oxide layer, and the gate oxide layer grows on the inner wall of the groove;
the outer side of the N + source electrode on the upper surface of the P type body region also comprises a P type body region contact layer, the P type body region contact layer is formed by downward arrangement on the upper surface of the P type body region, and the P type body region contact layer comprises fourth ions;
the P-type body region further comprises a P + buried layer, the P + buried layer is arranged in the center of the P-type body region and outside the groove, and the P + buried layer comprises fifth ions; and an ohmic contact metal layer is arranged above the N + source electrode, the P-type body region contact layer and the Schottky barrier metal layer.
2. The device of claim 1, wherein the device, in order from top to bottom:
a back metal formed from a combination of metal Ti, metal Ni, and metal Ag; an N + type heavily doped SiC substrate; the N-epitaxial layer; an insulating dielectric layer made of SiO2Forming; the insulating medium layer is arranged above the polycrystalline silicon grid and the P-type body region contact layer;
a front metal consisting of Al and having a thickness of 1-5 μm.
3. The device according to claim 2, wherein the silicon carbide single crystal material used for the silicon carbide substrate is one of a 2H-SiC single crystal and a 4H-SiC single crystal, and the doping concentration of the N + -type heavily doped SiC substrate is 3 x 1019-3×1020ion/CM3。
4. The device of claim 1, wherein the N-epitaxial layer has a doping concentration of 1 x 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doping impurity is nitrogen element.
5. The device of claim 1, wherein the P-type body region has a depth of 1-3 μm, the first ions are boron ions, the N + source region has a depth of 0.2-0.8 μm, and the second ions are phosphorous ions.
6. The device of claim 1, wherein the third, fourth, and fifth ions are boron ions.
7. The device of claim 1 wherein said polysilicon has a doping concentration greater than 1 x 1020ion/CM3。
8. The device of claim 1 wherein said gate oxide layer has a thickness of 0.04-0.1 μm.
9. The device of claim 2, wherein the insulating dielectric layer has a thickness of
Figure FDA0003645908830000021
The Schottky barrier metal layer is TiMo or TiW, and the thickness of the Schottky barrier metal layer is
Figure FDA0003645908830000022
The thickness of the ohmic contact metal layer is
Figure FDA0003645908830000023
10. A method of fabricating an enhanced silicon carbide MOSFET device, comprising:
step 1: selecting an N + type heavily doped SiC substrate, and growing an N-epitaxial layer on the upper surface of the N + type heavily doped SiC substrate;
step 2: first ions are downwards implanted into the upper surface of the N-epitaxial layer in a photoetching and ion implantation mode to form at least three P-type body regions which are arranged in parallel at intervals in the horizontal direction, and second ions are downwards implanted into the central regions of the upper surfaces of the at least three P-type body regions in an ion implantation mode to form an N + source electrode;
and 3, step 3: forming a groove in the central area of the N + source electrode by etching downwards in a groove photoetching and groove etching mode, wherein the depth of the groove is deeper than the P-type body area but is not contacted with the N + type heavily doped SiC substrate;
and 4, step 4: injecting third ions downwards at the bottom of the groove in an ion injection mode to form a grid bottom P region;
and 5: growing a first gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a rapid thermal oxidation mode for 5-10 times, stripping the first gate oxide layer by a wet etching mode, and then forming a second gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a furnace tube thermal oxidation mode;
and 6: depositing polycrystalline silicon on the upper surface of the N-epitaxial layer and in the groove, and etching the polycrystalline silicon on the upper surface of the N-epitaxial layer through a CMP (chemical mechanical polishing) process;
and 7: injecting fourth ions on the upper surface of the N-epitaxial layer below the second gate oxide layer to form a P-type body region contact layer;
and step 8: growing an insulating medium layer on the upper surface of the second gate oxide layer, wherein the insulating medium layer is made of SiO2Forming;
and step 9: etching the insulating medium layer by photoetching and etching modes to form at least six channels, wherein the channels lead to the upper surface of the P-type body region and the upper surface of the N + source electrode, and the region formed by the at least six channels is a first region;
step 10: implanting fifth ions on the upper surface of the P-type body region to which the channel leads in an ion implantation mode to form a P + buried layer, wherein the implantation depth of the fifth ions is 0.4-0.6 times of the depth of the P-type body region;
step 11: etching through the P type body region contact layer, the second gate oxide layer and the insulating medium layer above the regions among the P type body regions in a dry etching mode to form a second region, depositing barrier metal on the second region to form a Schottky barrier metal layer, and depositing N type body region contact layer, the second gate oxide layer and the insulating medium layer after the deposition is finished to form a Schottky barrier metal layer2Carrying out high-temperature annealing in the atmosphere;
step 12: depositing metal titanium on the first area and the second area to form an ohmic contact metal layer;
step 13: and growing Al on the ohmic contact metal layer and the insulating medium layer to form front metal.
11. The method according to claim 10, wherein the first ions are boron ions, the number of times of implantation of the first ions is 3 to 5, and a single implantation dose is 2 x 1013-1×1014ion/CM2Cumulative implant dose of 1X 1014-5×1014ion/CM2The implantation energy is 50Kev-1.5Mev, and the implantation depth is 1 μm-2.5 μm.
12. The method according to claim 10, wherein the second ions are phosphorus ions, and the implantation dose of the second ions is 3 x 1015-2×1016ion/CM2The implantation energy is 150Kev-500Kev, and the implantation depth is 0.3 μm-0.5 μm.
13. The method as claimed in claim 10, wherein the N + source and the P-type body region are advanced at a high temperature of 1700-1900 ℃, and the time for advancing at the high temperature is 60-300 min.
14. The method of claim 10, wherein the trench has a depth of 1-4 μm and a width of 0.4-1 μm, and wherein the bottom of the trench is rounded after the trench lithography and trench etching.
15. The method according to claim 10, wherein the third ions are boron ions, and wherein the third ions are implanted at a dose of 1 x 1013-1×1014ion/CM2The implantation energy is 30-80 Kev.
16. The method according to claim 10, wherein the rapid thermal oxidation mode time is 30S-2min, and the thickness of the single rapid thermal oxidation is less than
Figure FDA0003645908830000044
Cumulative rapid thermal oxidation thickness greater than
Figure FDA0003645908830000041
17. The manufacturing method according to claim 10, wherein the furnace tube thermal oxidation mode adopts CL-based gas, and the thickness of the second gate oxide layer formed by the furnace tube thermal oxidation mode is 0.04-0.1 μm.
18. The manufacturing method according to claim 10, wherein the impurity concentration of the polycrystalline silicon is 1 x 1020ion/CM3Above, the thickness of the polysilicon is
Figure FDA0003645908830000042
19. The method according to claim 10, wherein the fourth ions are implanted at an energy of 50 to 150Kev and at an implant dose of 1 x 1013-5×1013ion/CM2。
20. The method of claim 10, wherein the dielectric layer has a thickness of
Figure FDA0003645908830000043
21. The method as claimed in claim 10, wherein the implantation energy of the fifth ions is 300-800Kev, and the implantation dose is 2 x 1013-2×1014ion/CM2。
22. The method as claimed in claim 10, wherein the annealing temperature is 900-1100 ℃ after the deposition of the ohmic contact metal layer.
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