CN113451401A - Abnormal-shaped groove separation gate IGBT structure and manufacturing method thereof - Google Patents
Abnormal-shaped groove separation gate IGBT structure and manufacturing method thereof Download PDFInfo
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- 238000002955 isolation Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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Abstract
The invention provides a special-shaped groove separation gate IGBT structure and a manufacturing method thereof, and relates to the technical field of IGBT structures. The top of collecting electrode is provided with n type substrate, the inside of n type substrate is provided with the vertical slot that the rule was arranged, has oxide layer and polycrystal layer in the slot, be equipped with p type trap between adjacent slot, built-in n + emitter region of p type trap and p + type short circuit district, n + emitter region is located p type trap top limit portion, p + type short circuit district is located in the middle of the n + emitter region, the slot top is equipped with protective oxide layer and projecting pole metal, set up the metal level in the protective oxide layer and form projecting pole and grid. Compared with the prior art, the invention has the beneficial effects that: the IGBT device has the advantages that the upper and lower structures are adopted for the separation gate, the internal structure of the IGBT device is compact and seamless through the unique two-time groove etching process, the Miller capacitance of the IGBT device can be reduced, the switching speed of the IGBT device is improved, and the switching loss is effectively reduced.
Description
Technical Field
The invention relates to the technical field of IGBT (insulated gate bipolar transistor) structures, in particular to a special-shaped groove separation gate IGBT structure and a manufacturing method thereof.
Background
The insulated gate transistor (IGBT) is used as a novel power semiconductor field control self-turn-off device, integrates the high-speed performance of a power MOSFET and the low resistance of a bipolar device, has the characteristics of high input impedance, low voltage control power consumption, simple control circuit, high voltage resistance, large bearing current and the like, and is widely applied to various power conversion. With the continuous increase of the applied power, the switching loss of the IGBT also rises, and the switching loss of the IGBT is obviously reduced through the unique design of the separation gate.
Disclosure of Invention
The invention provides a special-shaped groove separation gate IGBT structure, wherein an upper structure separation gate and a lower structure separation gate are formed through a unique groove etching process twice, so that the Miller capacitance of an IGBT device is reduced, and the switching loss is effectively reduced.
The specific technical scheme is that the abnormal groove separation gate IGBT structure comprises a collector electrode, wherein an n-type substrate is arranged above the collector electrode, vertical grooves which are regularly distributed are arranged inside the n-type substrate, each vertical groove comprises an upper groove and a lower groove which are connected, the lower grooves are positioned below the upper grooves, lower groove emitter thick gate oxide layers are arranged on the inner side wall and the bottom wall of each lower groove, a lower groove emitter polycrystalline layer is arranged on the inner side of each lower groove emitter thick gate oxide layer, an isolation oxide layer is arranged at the top of each lower groove emitter polycrystalline layer, an upper groove gate oxide layer is arranged on the inner side wall of each upper groove, an upper groove gate polycrystalline layer is arranged inside each upper groove gate oxide layer and above each isolation oxide layer, p is arranged between the adjacent grooves, and an n + emitter region and a p + short circuit region are arranged in each p-type trap, the n + emitting region is located on the upper edge portion of the p-type trap, the p + type short-circuit region is located in the middle of the n + emitting region, a protective oxidation layer and emitting electrode metal are arranged on the top of the groove, and a metal layer is arranged in the protective oxidation layer to form an emitting electrode and a grid electrode.
Furthermore, the grooves are bottle-shaped, the width of the lower groove is larger than that of the upper groove, and the height of the lower groove is lower than that of the upper groove.
Further, the height of the p-type well is lower than the height of the upper trench.
Further, the collector electrode includes: a collector metal and a p + collector, the p + collector being located between the collector metal and the n-type substrate.
The manufacturing method of the abnormal-shaped groove separation gate IGBT structure comprises the following steps:
s1, depositing 7000A dense oxide layer on the surface of the n-type substrate as a hard mask,
s2, first photoetching, photoetching a first groove etching window on the top of the hard mask through photoetching and etching processes,
s3, etching a groove for the first time, carrying out high-temperature sacrificial oxidation, removing the sacrificial oxidation, etching downwards from the top of the n-type substrate to form the upper groove, growing the gate oxide layer of the upper groove on the inner wall of the upper groove,
s4, depositing the silicon nitride barrier layer on the inner surface of the upper trench gate oxide layer formed in the step S3,
s5, etching the groove for the second time, etching downwards from the bottom of the silicon nitride barrier layer in the step S4 to form the lower groove,
s6, high-temperature sacrificial oxidation, sacrificial oxidation removal, growing the lower groove emitter thick gate oxide layer on the inner wall of the lower groove,
s7, removing the silicon nitride barrier layer formed in the step S4 in the upper groove, depositing the lower groove emitter polycrystalline layer in the lower groove emitter thick gate oxide layer and etching back the lower groove emitter polycrystalline layer, depositing the isolation oxide layer on the top of the lower groove emitter polycrystalline layer and etching back the isolation oxide layer,
s8, depositing the upper groove gate polycrystalline layer inside the upper groove gate oxide layer and above the isolation oxide layer, etching back the upper groove gate polycrystalline layer,
s9, carrying out third photoetching, photoetching a p-type well injection window between adjacent grooves, carrying out BODY injection, annealing to form the p-type well,
s10, carrying out fourth photoetching, photoetching an n + type emitter injection window at the upper edge part of the p-type trap, carrying out n + ion injection to form the n + emitter region, carrying out chemical vapor deposition on an oxide layer,
s11, fifth photoetching, etching an emitter contact hole in the middle of the n + emitter region, carrying out p + ion implantation, annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃ to form the p + type short-circuit region,
s12, setting a contact window, respectively setting the emitter metal and the protective oxidation layer on the top of the structure finished part, setting a metal layer in the protective oxidation layer to respectively form an emitter and a grid, then removing the back of the n-type substrate, performing p + back injection through ion injection, annealing at 400 ℃, and setting a metal material layer to form a collector.
Compared with the prior art, the invention has the beneficial effects that: the IGBT device has the advantages that the separation gate adopts an upper structure and a lower structure, the design is exquisite, the internal structure of the produced IGBT device is compact and seamless through a unique groove etching process twice, the Miller capacitance of the IGBT device can be reduced, the switching speed of the IGBT device is improved, the switching loss is effectively reduced, and the IGBT device is safe and reliable.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram illustrating a step S1 implemented according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram illustrating a step S2 implemented according to the present invention;
FIG. 3 is a schematic structural diagram illustrating a step S3 implemented according to the present invention;
FIG. 4 is a schematic structural diagram illustrating the completion of step S4 according to the embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating the completion of step S5 according to the embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating a step S6 implemented according to the present invention;
FIG. 7 is a schematic structural diagram illustrating a step S7 implemented according to the present invention;
FIG. 8 is a schematic structural diagram illustrating a step S8 implemented according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram illustrating a step S9 implemented according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram illustrating a step S10 implemented according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram illustrating a step S11 implemented according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram illustrating the implementation of step S12 according to the embodiment of the present invention.
Wherein: 1. collector metal, 2, p + collector, 3, n type substrate, 4, hard mask, 5, upper trench gate oxide layer, 6, silicon nitride barrier layer, 7, trench bottom, 8, lower trench emitter thick gate oxide layer, 9, lower trench emitter polycrystalline layer, 10, isolation oxide layer, 11, upper trench gate polycrystalline layer, 12, p type well, 13, n + emitter region, 14, p + type short-circuit region, 15, protective oxide layer, 16, emitter metal, 17, first trench etching window.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
In the description of the present invention, it should be noted that the terms "inner", "outer", "left" and "right" are used for indicating the orientation or positional relationship based on the positional relationship shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present invention.
The invention is described below with reference to figures 1-12:
example (b): a special-shaped groove separation gate IGBT structure comprises a collector electrode, wherein an n-type substrate 3 is arranged above the collector electrode, vertical grooves which are regularly distributed are arranged inside the n-type substrate 3, each vertical groove comprises an upper groove and a lower groove which are connected, the lower grooves are positioned below the upper grooves, a lower groove emitter thick gate oxide layer 8 is arranged on the inner side wall and the bottom wall of each lower groove, a lower groove emitter polycrystalline layer 9 is arranged on the inner side of the lower groove emitter thick gate oxide layer 8, an isolation oxide layer 10 is arranged at the top of the lower groove emitter polycrystalline layer 9, an upper groove gate oxide layer 5 is arranged on the inner side wall of each upper groove, an upper groove gate polycrystalline layer 11 is arranged inside the upper groove gate oxide layer 5 and above the isolation oxide layer 10, a p-type trap 12 is arranged between the adjacent grooves, and an n + emitter region 13 and a p + type short-circuit region 14 are arranged in the p 12, the n + emitting region 13 is located on the upper edge portion of the p-type well 12, the p + type short-circuit region 14 is located in the middle of the n + emitting region 13, a protective oxide layer 15 and emitting electrode metal 16 are arranged on the top of the groove, and a metal layer is arranged in the protective oxide layer 15 to form an emitting electrode and a grid electrode.
Furthermore, the grooves are bottle-shaped, the width of the lower groove is larger than that of the upper groove, and the height of the lower groove is lower than that of the upper groove.
Further, the height of the p-type well 12 is lower than that of the upper trench.
Further, the collector electrode includes: a collector metal 1 and a p + collector 2, the p + collector 2 being located between the collector metal 1 and the n-type substrate 3.
The manufacturing method of the abnormal-shaped groove separation gate IGBT structure comprises the following steps:
s1, depositing 7000A dense oxide layer on the surface of the n-type substrate 3 as a hard mask 4,
s2, carrying out first photoetching, photoetching a first groove etching window 17 on the top of the hard mask 4 through photoetching and etching processes,
s3, etching the groove for the first time by 3.5um, performing high-temperature sacrificial oxidation, removing the sacrificial oxidation, etching downwards from the top of the n-type substrate 3 to form an upper groove, wherein the bottom of the upper groove is the bottom 7 of the groove, growing the upper groove grid oxide layer 5 on the inner wall of the upper groove,
s4, depositing the silicon nitride barrier layer 6 on the inner surface of the upper trench gate oxide layer 5 formed in the step S3,
s5, etching the groove for the second time by 2.5um, etching downwards from the bottom of the silicon nitride barrier layer 6 in the step S4 to form a lower groove, wherein the bottom of the lower groove is the bottom 7 of the groove, and compared with the step S3, the position of the bottom 7 of the groove is changed,
s6, performing high-temperature sacrificial oxidation, removing the sacrificial oxidation, growing the lower trench emitter thick gate oxide layer 8 on the inner wall of the lower trench, changing the position of the bottom 7 of the trench relative to the step S5, setting the bottom of the lower trench emitter thick gate oxide layer 8 as the bottom 7 of the trench,
s7, removing the silicon nitride barrier layer 6 formed in the step S4 in the upper trench, depositing the lower trench emitter polycrystalline layer 9 in the lower trench emitter thick gate oxide layer 8 and etching back the lower trench emitter polycrystalline layer 9, depositing the isolation oxide layer 10 on the top of the lower trench emitter polycrystalline layer 9 and etching back the isolation oxide layer 10,
s8, depositing the upper trench gate polycrystalline layer 11 inside the upper trench gate oxide layer 5 and above the isolation oxide layer 10, etching back the upper trench gate polycrystalline layer 11,
s9, carrying out third photoetching, photoetching a p-type well injection window between adjacent grooves, carrying out BODY injection, annealing to form the p-type well 12,
s10, carrying out fourth photoetching, photoetching an n + type emitter injection window at the upper side part of the p-type well 12, carrying out n + ion injection to form the n + emission region 13, carrying out chemical vapor deposition on an oxide layer,
s11, carrying out fifth photoetching, etching an emitter contact hole in the middle of the n + emitter region 13, carrying out p + ion implantation, annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃ to form the p + type short-circuit region 14,
s12, setting a contact window, respectively setting the emitter metal 16 and the protective oxidation layer 15 on the top of the structure finished part, setting a metal layer in the protective oxidation layer 15 to respectively form an emitter and a grid, then removing the back of the n-type substrate 3, performing p + back injection through ion injection, annealing at 400 ℃, and setting a metal material layer to form a collector.
In the method used by the application, the grooves are etched twice and are formed step by step, for example, the lower groove emitter polycrystalline layer 9 is firstly deposited in the lower groove emitter thick gate oxide layer 8, then the lower groove emitter polycrystalline layer 9 is etched back, the formed lower groove emitter polycrystalline layer 9 and the lower groove emitter thick gate oxide layer 8 are well combined, and the lower groove emitter polycrystalline layer 9 is uniform and compact. By adopting the process, the produced IGBT device has a compact and seamless internal structure, can reduce the Miller capacitance of the IGBT device, improve the switching speed of the IGBT device, effectively reduce the switching loss, and is safe and reliable.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any person skilled in the art may modify or modify the technical details disclosed above into equivalent embodiments with equivalent variations. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.
Claims (5)
1. The IGBT structure is characterized by comprising a collector electrode, wherein an n-type substrate (3) is arranged above the collector electrode, vertical grooves which are regularly distributed are arranged inside the n-type substrate (3), the vertical grooves comprise an upper groove and a lower groove which are connected, the lower groove is positioned below the upper groove, a lower groove emitter thick gate oxide layer (8) is arranged on the inner side wall and the bottom wall of the lower groove, a lower groove emitter polycrystalline layer (9) is arranged on the inner side of the lower groove emitter thick gate oxide layer (8), an isolation oxide layer (10) is arranged at the top of the lower groove emitter polycrystalline layer (9), an upper groove grid gate oxide layer (5) is arranged on the inner side wall of the upper groove, an upper groove grid polycrystalline layer (11) is arranged inside the upper groove grid oxide layer (5) and above the isolation oxide layer (10), be adjacent be equipped with p type well (12) between the slot, built-in n + emission region (13) and p + type short circuit district (14) are caught to p type well (12), n + emission region (13) are located p type well (12) top edge portion, p + type short circuit district (14) are located in the middle of n + emission region (13), the slot top is equipped with protective oxide layer (15) and emitter metal (16), set up metal layer formation emitter and grid in protective oxide layer (15).
2. The Insulated Gate Bipolar Transistor (IGBT) structure according to claim 1, wherein the trench is shaped like a bottle, the width of the lower trench is larger than that of the upper trench, and the height of the lower trench is lower than that of the upper trench.
3. A profiled trench isolation gate IGBT structure as claimed in claim 1, characterized in that the height of said p-type well (12) is lower than the height of said upper trench.
4. The heavy-type trench isolation gate IGBT structure of claim 1, wherein the collector comprises: a collector metal (1) and a p + collector (2), the p + collector (2) being located between the collector metal (1) and the n-type substrate (3).
5. The method for manufacturing the profiled trench split gate IGBT structure as defined in any one of claims 1 to 4, comprising the steps of:
s1, depositing 7000A dense oxide layer on the surface of the n-type substrate (3) to be used as a hard mask (4),
s2, carrying out first photoetching, photoetching a first groove etching window (17) on the top of the hard mask (4) through photoetching and etching processes,
s3, etching a groove for the first time, carrying out high-temperature sacrificial oxidation, removing the sacrificial oxidation, etching downwards from the top of the n-type substrate (3) to form the upper groove, growing the gate oxide layer (5) of the upper groove on the inner wall of the upper groove,
s4, depositing the silicon nitride barrier layer (6) on the inner surface of the upper trench gate oxide layer (5) formed in the step S3,
s5, etching the groove for the second time, etching downwards from the bottom of the silicon nitride barrier layer (6) in the step S4 to form the lower groove,
s6, sacrificial oxidation at high temperature, sacrificial oxidation removal, growing a thick grid oxide layer (8) of the emitter of the lower groove on the inner wall of the lower groove,
s7, removing the silicon nitride barrier layer (6) formed in the step S4 in the upper groove, depositing the lower groove emitter polycrystalline layer (9) in the lower groove emitter thick gate oxide layer (8) and etching back the lower groove emitter polycrystalline layer (9), depositing the isolation oxide layer (10) on the top of the lower groove emitter polycrystalline layer (9) and etching back the isolation oxide layer (10),
s8, depositing the upper groove grid polycrystalline layer (11) inside the upper groove grid oxide layer (5) and above the isolation oxide layer (10), and etching back the upper groove grid polycrystalline layer (11),
s9, carrying out third photoetching, photoetching a p-type well injection window between the adjacent grooves, carrying out BODY injection, annealing to form the p-type well (12),
s10, carrying out fourth photoetching, photoetching an n + type emitter injection window at the upper side part of the p-type trap (12), carrying out n + ion injection to form the n + emission region (13), carrying out chemical vapor deposition on an oxide layer,
s11, fifth photoetching, etching an emitter contact hole in the middle of the n + emitting region (13), carrying out p + ion implantation, annealing for 30 minutes in a nitrogen atmosphere at the temperature of 875 ℃ to form the p + type short circuit region (14),
s12, setting a contact window, respectively setting the emitter metal (16) and the protective oxidation layer (15) on the top of the structure finished part, setting a metal layer in the protective oxidation layer (15) to respectively form an emitter and a grid, then removing the back of the n-type substrate (3), performing p + back injection through ion injection, annealing at 400 ℃, and setting a metal material layer to form a collector.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115483284A (en) * | 2022-07-20 | 2022-12-16 | 上海林众电子科技有限公司 | Preparation method and application of improved SG IGBT |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115483284A (en) * | 2022-07-20 | 2022-12-16 | 上海林众电子科技有限公司 | Preparation method and application of improved SG IGBT |
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