CN113224135A - Shielding gate MOSFET device with high avalanche tolerance and manufacturing method thereof - Google Patents

Shielding gate MOSFET device with high avalanche tolerance and manufacturing method thereof Download PDF

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Publication number
CN113224135A
CN113224135A CN202110557701.5A CN202110557701A CN113224135A CN 113224135 A CN113224135 A CN 113224135A CN 202110557701 A CN202110557701 A CN 202110557701A CN 113224135 A CN113224135 A CN 113224135A
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oxide layer
region
layer
etching
groove
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王艳颖
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Shanghai Daozhi Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a high avalanche tolerance shielding grid MOSFET device and a manufacturing method thereof, wherein the shielding grid MOSFET device is divided into a terminal area and a cell area, the terminal area and the cell area respectively mainly comprise a substrate layer and an epitaxial layer which are sequentially arranged, and a groove is arranged on the epitaxial layer; the manufacturing method comprises the following steps: performing groove etching on the selected epitaxial silicon substrate; growing a sacrificial oxide layer; removing the sacrificial oxide layer in the primitive cell region by using a mask plate, and reserving the oxide layer in the terminal groove; preparing a field oxide layer by thermal oxidation or thermal oxidation plus deposition of the oxide layer; filling the shield grid with polysilicon; growing a gate oxide layer; filling gate polysilicon; injecting and annealing a body region; photoetching a source region and injecting the source region; photoetching a contact hole, etching an insulating layer, sputtering top metal, photoetching the top metal, depositing a passivation layer, photoetching the passivation layer, and finishing the manufacture of a top layer structure; and finally, wafer thinning and back metal deposition are carried out.

Description

Shielding gate MOSFET device with high avalanche tolerance and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate MOSFET device with high avalanche tolerance and a manufacturing method thereof.
Background
Compared with the traditional trench MOSFET, the shielded gate MOSFET has the advantages of low on-resistance and low switching loss, so that the application of the shielded gate MOSFET in the middle and low voltage power semiconductor market is gradually increased. In recent years, a shielded gate MOSFET device is applied more and more widely as a switching device in a motor driving system, an inverter system and a power management system in the fields of new energy electric vehicles, novel photovoltaic power generation, energy-saving household appliances and the like, and as a core power control component, the requirements on the performance and the reliability of the MOSFET device are higher and higher. In actual reliability tests and system applications, a device with high avalanche tolerance is found to be an important index of a high-reliability device. The cause of the low avalanche resistance of the device is various reasons, one of which is EAS failure caused by non-uniform breakdown, and the termination region of the existing shielded gate MOSFET devices produced in the industry adopts a trench structure similar to the cell region, and the termination region of the structure causes more concentrated electric field especially at the corner, so that breakdown occurs in the termination region first. The termination region only occupies a small part of the area of the device, avalanche current is concentrated in the termination region, the temperature of the termination region is rapidly increased, and the device is burnt, so the avalanche tolerance of the device is low. It should therefore be avoided that breakdown occurs in the termination region of the device during design of the device.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a shielded gate MOSFET device with high avalanche tolerance and a manufacturing method thereof, which is compatible with the existing process and is safer and more reliable, in order to overcome the above drawbacks of the prior art.
The invention aims to provide a high avalanche tolerance shielding grid MOSFET device, which comprises an MOSFET device body, wherein the MOSFET device body is divided into a terminal area and a cell area, the terminal area and the cell area both mainly comprise a substrate layer and an epitaxial layer which are sequentially arranged, and the epitaxial layer is provided with an inward concave groove; a shielding grid polycrystalline silicon and a terminal thick field oxide layer arranged between the shielding grid polycrystalline silicon and the groove are arranged in the groove of the terminal area, and a sacrificial oxide layer, a field oxide layer, a gate oxide layer and a dielectric layer are sequentially arranged on the upper surface of the terminal area from inside to outside; the upper surface of the primitive cell region is etched with an etching groove communicated with the groove in the primitive cell region, the gate polycrystalline silicon and the gate oxide layer are arranged in the etching groove, and a source region and a body region which are sequentially arranged from top to bottom are arranged between every two adjacent etching grooves; the upper surfaces of the gate polycrystalline silicon and the gate oxide layer are provided with dielectric layers, and a plurality of contact holes are formed in the dielectric layers.
Furthermore, the terminal thick field oxide layer in the terminal area comprises a sacrificial oxide layer and a field oxide layer which are sequentially arranged from inside to outside, and the thickness of the dielectric layer in the terminal area is greater than the sum of the thicknesses of the sacrificial oxide layer, the field oxide layer and the gate oxide layer; the depth of the etching groove in the primitive cell area is 0-1 um.
A manufacturing method of a shielded gate MOSFET device mainly comprises the following steps:
1) depositing an oxide layer with the thickness of 1-1.5 um on the selected N epitaxial silicon substrate as a hard mask, photoetching a groove on the N epitaxial silicon substrate by using a first mask and carrying out deep groove etching, and simultaneously forming grooves of a cell region and a terminal region;
2) growing a sacrificial oxide layer, namely generating a thermal oxide layer with the thickness of about 500-3000A on the trenches of the cell region and the terminal region and the silicon surface;
3) selectively removing the sacrificial oxide layer on the trench of the cell region and the silicon surface by using a second mask, and reserving the sacrificial oxide layer on the trench of the terminal region and the silicon surface;
4) according to the requirement of the breakdown voltage of the device, preparing field oxide layers with corresponding thicknesses on the upper surfaces of the cell region and the terminal region and in the groove in a thermal oxidation or thermal oxidation plus deposition oxide layer mode, wherein the sum of the thicknesses of the sacrificial oxide layer and the field oxide layer in the groove of the terminal region is larger than the thickness of the field oxide layer in the groove of the cell region;
5) depositing a shield grid polysilicon in the grooves of the terminal area and the cell area, and etching back to the silicon surface by chemical mechanical polishing or wet etching;
6) photoetching an active region by using a third mask, and etching off the upper surface of the cell region and the field oxide layer with a certain depth in the groove of the cell region;
7) growing a gate oxide layer on the upper surfaces of the terminal area and the primitive cell area in a thermal oxidation mode;
8) depositing gate polysilicon, defining a gate polysilicon lead-out area by using a fourth mask, and etching back to the surface of the silicon by dry etching;
9) carrying out body region injection and annealing to form a P-type body region of the device;
10) using a fifth mask to carry out source region photoetching, injecting N-type impurities and annealing to form a heavily-doped N-type source region;
11) depositing a dielectric layer, then using a sixth mask to carry out contact hole photoetching, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole;
12) sputtering top metal, and photoetching and etching the top metal by using a seventh mask to form a source electrode and a grid electrode of the device; depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using an eighth mask to finish the manufacturing of the top layer structure;
13) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form a drain electrode of the device.
The invention has the beneficial technical effects that: the field oxide layer with relatively thick thickness is formed in the groove of the terminal area through the device and the process manufacturing design, so that the avalanche breakdown of the device is generated in the cell area of the device, thereby avoiding the EAS failure caused by uneven avalanche current and concentration of the avalanche current on the terminal of the device, and effectively improving the avalanche tolerance of the device.
Drawings
FIG. 1 is a schematic diagram of deep trench etching;
FIG. 2 is a schematic illustration of sacrificial oxide growth;
FIG. 3 is a schematic diagram illustrating the removal of a sacrificial oxide layer in a cell region;
fig. 4 is a schematic diagram of field oxide growth;
FIG. 5 is a schematic illustration of shield gate poly-silicon fill;
FIG. 6 is a schematic diagram of etching a field oxide layer;
FIG. 7 is a schematic diagram of gate polysilicon deposition and etching;
FIG. 8 is a schematic illustration of a body implant and anneal;
FIG. 9 is a schematic illustration of source region implantation and annealing;
FIG. 10 is a schematic diagram of contact hole etching.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood by those skilled in the art, the present invention is further described with reference to the accompanying drawings and examples.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", "inside", "outside", "lateral", "vertical", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description of the present invention, and do not indicate or imply that the device or element referred to must have a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1-10, the invention provides a shielded gate MOSFET device with high avalanche tolerance, and the breakdown of the device occurs in the cell region through the design of the process and the manufacturing method, so that the device has high avalanche tolerance. The invention adds a mask plate to make the thickness of the shielding grid oxide layer in the groove of the terminal area larger than that of the shielding grid oxide layer in the groove of the cell area, thereby increasing the breakdown voltage of the terminal area, leading avalanche breakdown to firstly occur in the cell area and further improving the avalanche tolerance of the device. The preparation method provided by the invention is compatible with the existing process, and is safe and reliable.
The invention relates to a high avalanche tolerance shielding grid MOSFET device, which comprises an MOSFET device body, wherein the MOSFET device body is divided into a terminal area and a cell area, the terminal area and the cell area both mainly comprise a substrate layer 1 and an epitaxial layer 2 which are sequentially arranged, and the epitaxial layer 2 is provided with an inwards concave groove 3; a shielding grid polysilicon 4 and a terminal thick field oxide layer arranged between the shielding grid polysilicon 4 and the trench 3 are arranged in the trench 3 of the terminal area, and a sacrificial oxide layer 5, a field oxide layer 6, a gate oxide layer 7 and a dielectric layer 8 are sequentially arranged on the upper surface of the terminal area from inside to outside; a shielding grid polycrystalline silicon 4 and a field oxide layer 6 arranged between the shielding grid polycrystalline silicon 4 and the groove 3 are arranged in the groove 3 of the primitive cell region, an etching groove communicated with the groove 3 in the primitive cell region is etched on the upper surface of the primitive cell region, a grid polycrystalline silicon 9 and a grid oxide layer 7 are arranged in the etching groove, and a source region 10 and a body region 11 which are sequentially arranged from top to bottom are arranged between every two adjacent etching grooves; the upper surfaces of the gate polysilicon 9 and the gate oxide layer 7 are provided with a dielectric layer 8, and a plurality of contact holes 12 are arranged in the dielectric layer 8.
The terminal thick field oxide layer in the terminal area comprises a sacrificial oxide layer 5 and a field oxide layer 6 which are sequentially arranged from inside to outside, and the thickness of a dielectric layer 8 in the terminal area is larger than the sum of the thicknesses of the sacrificial oxide layer 5, the field oxide layer 6 and a gate oxide layer 7; the depth of the etching groove in the primitive cell area is 0-1 um.
A manufacturing method of a shielded gate MOSFET device mainly comprises the following steps:
1) depositing an oxide layer with the thickness of 1-1.5 um on the selected N epitaxial silicon substrate as a hard mask, photoetching a groove on the N epitaxial silicon substrate by using a first mask and carrying out deep groove etching, and simultaneously forming grooves of a cell region and a terminal region, as shown in figure 1;
2) performing sacrificial oxide layer growth, namely generating thermal oxide layers with the thickness of about 500A-3000A on the trenches of the cell region and the terminal region and the silicon surface, as shown in FIG. 2;
3) selectively removing the sacrificial oxide layer on the trench of the cell region and the silicon surface by using a second mask, and reserving the sacrificial oxide layer on the trench of the terminal region and the silicon surface, as shown in fig. 3;
4) according to the requirement of the breakdown voltage of the device, preparing field oxide layers with corresponding thicknesses on the upper surfaces of the cell region and the terminal region and in the trench by thermal oxidation or thermal oxidation plus deposition of oxide layers, wherein the sum of the thicknesses of the sacrificial oxide layer and the field oxide layer in the terminal region trench is larger than the thickness of the field oxide layer in the cell region trench, as shown in fig. 4;
5) depositing a shield grid polysilicon in the trenches of the terminal area and the cell area, and etching back to the silicon surface by chemical mechanical polishing or wet etching, as shown in fig. 5;
6) photoetching an active region by using a third mask, and etching off the field oxide layer with a certain depth on the upper surface of the cell region and in the groove of the cell region, wherein the etching depth is 0-1 um, as shown in FIG. 6;
7) growing a gate oxide layer on the upper surfaces of the terminal area and the primitive cell area in a thermal oxidation mode;
8) depositing gate polysilicon, defining a gate polysilicon lead-out region by using a fourth mask, and etching back to the surface of the silicon by dry etching, as shown in FIG. 7;
9) performing body implantation and annealing to form a P-type body region of the device, as shown in fig. 8;
10) using a fifth mask to carry out source region photoetching, injecting N-type impurities and annealing to form a heavily doped N-type source region as shown in FIG. 9;
11) depositing a dielectric layer, then using a sixth mask to perform contact hole photoetching, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole, as shown in FIG. 10;
12) sputtering top metal, and photoetching and etching the top metal by using a seventh mask to form a source electrode and a grid electrode of the device; depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using an eighth mask to finish the manufacturing of the top layer structure;
13) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form a drain electrode of the device.
The field oxide layer with relatively thick thickness is formed in the groove of the terminal area through the device and the process manufacturing design, so that the avalanche breakdown of the device is generated in the cell area of the device, thereby avoiding the EAS failure caused by uneven avalanche current and concentration of the avalanche current on the terminal of the device, and effectively improving the avalanche tolerance of the device.
The specific embodiments described herein are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (3)

1. A shielded gate MOSFET device with high avalanche tolerance comprises a MOSFET device body, and is characterized in that: the MOSFET device body is divided into a terminal area and a cell area, the terminal area and the cell area both mainly comprise a substrate layer and an epitaxial layer which are sequentially arranged, and the epitaxial layer is provided with an inward concave groove; a shielding grid polycrystalline silicon and a terminal thick field oxide layer arranged between the shielding grid polycrystalline silicon and the groove are arranged in the groove of the terminal area, and a sacrificial oxide layer, a field oxide layer, a gate oxide layer and a dielectric layer are sequentially arranged on the upper surface of the terminal area from inside to outside; the upper surface of the primitive cell region is etched with an etching groove communicated with the groove in the primitive cell region, the gate polycrystalline silicon and the gate oxide layer are arranged in the etching groove, and a source region and a body region which are sequentially arranged from top to bottom are arranged between every two adjacent etching grooves; the upper surfaces of the gate polycrystalline silicon and the gate oxide layer are provided with dielectric layers, and a plurality of contact holes are formed in the dielectric layers.
2. The shielded gate MOSFET device of claim 1, wherein: the terminal thick field oxide layer in the terminal area comprises a sacrificial oxide layer and a field oxide layer which are sequentially arranged from inside to outside, and the thickness of the dielectric layer in the terminal area is greater than the sum of the thicknesses of the sacrificial oxide layer, the field oxide layer and the gate oxide layer; the depth of the etching groove in the primitive cell area is 0-1 um.
3. A method of fabricating a shielded gate MOSFET device as claimed in claim 1 or claim 2, wherein: the method mainly comprises the following steps:
1) depositing an oxide layer with the thickness of 1-1.5 um on the selected N epitaxial silicon substrate as a hard mask, photoetching a groove on the N epitaxial silicon substrate by using a first mask and carrying out deep groove etching, and simultaneously forming grooves of a cell region and a terminal region;
2) growing a sacrificial oxide layer, namely generating a thermal oxide layer with the thickness of about 500-3000A on the trenches of the cell region and the terminal region and the silicon surface;
3) selectively removing the sacrificial oxide layer on the trench of the cell region and the silicon surface by using a second mask, and reserving the sacrificial oxide layer on the trench of the terminal region and the silicon surface;
4) according to the requirement of the breakdown voltage of the device, preparing field oxide layers with corresponding thicknesses on the upper surfaces of the cell region and the terminal region and in the groove in a thermal oxidation or thermal oxidation plus deposition oxide layer mode, wherein the sum of the thicknesses of the sacrificial oxide layer and the field oxide layer in the groove of the terminal region is larger than the thickness of the field oxide layer in the groove of the cell region;
5) depositing a shield grid polysilicon in the grooves of the terminal area and the cell area, and etching back to the silicon surface by chemical mechanical polishing or wet etching;
6) photoetching an active region by using a third mask, and etching off the upper surface of the cell region and the field oxide layer with a certain depth in the groove of the cell region;
7) growing a gate oxide layer on the upper surfaces of the terminal area and the primitive cell area in a thermal oxidation mode;
8) depositing gate polysilicon, defining a gate polysilicon lead-out area by using a fourth mask, and etching back to the surface of the silicon by dry etching;
9) carrying out body region injection and annealing to form a P-type body region of the device;
10) using a fifth mask to carry out source region photoetching, injecting N-type impurities and annealing to form a heavily-doped N-type source region;
11) depositing a dielectric layer, then using a sixth mask to carry out contact hole photoetching, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole;
12) sputtering top metal, and photoetching and etching the top metal by using a seventh mask to form a source electrode and a grid electrode of the device; depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using an eighth mask to finish the manufacturing of the top layer structure;
13) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form a drain electrode of the device.
CN202110557701.5A 2021-05-21 2021-05-21 Shielding gate MOSFET device with high avalanche tolerance and manufacturing method thereof Pending CN113224135A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864403A (en) * 2022-04-20 2022-08-05 捷捷微电(上海)科技有限公司 Trench MOSFET manufacturing process capable of reducing mask times

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864403A (en) * 2022-04-20 2022-08-05 捷捷微电(上海)科技有限公司 Trench MOSFET manufacturing process capable of reducing mask times
CN114864403B (en) * 2022-04-20 2023-05-12 捷捷微电(上海)科技有限公司 Manufacturing process of Trench MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing mask times

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