CN113517350A - Low-voltage shielding grid MOSFET device and manufacturing method thereof - Google Patents
Low-voltage shielding grid MOSFET device and manufacturing method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 30
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- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 13
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- 238000001259 photo etching Methods 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 6
- 210000000746 body region Anatomy 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
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- 238000002347 injection Methods 0.000 claims description 3
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- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 8
- 238000011049 filling Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The invention discloses a low-voltage shielded gate MOSFET device and a manufacturing method thereof, and the low-voltage shielded gate MOSFET device comprises a MOSFET device body, wherein the MOSFET device body mainly comprises an N epitaxial silicon substrate and a plurality of grooves etched in the N epitaxial silicon substrate, a field oxide layer is formed on the inner wall of the middle lower part of each groove, a layer of shielded gate polycrystalline silicon is filled in the field oxide layer, an inter-gate oxide layer is arranged at the top of the shielded gate polycrystalline silicon, a control gate and a gate oxide layer are arranged at the top of the inter-gate oxide layer, and the gate oxide layer is formed on the side wall of the upper part of each groove; the back surface of the N epitaxial silicon substrate is provided with a layer of drain electrode formed by metal; the manufacturing method mainly comprises the steps of growing an oxide layer on the side wall of the groove and the top of the shielding gate by utilizing a thermal oxidation process after the shielding gate is formed, wherein the oxide layer is thick enough to completely fill the groove on the upper part of the shielding gate, and then carrying out back etching on the oxide layer to form an inter-gate oxide layer between the shielding gate and the control gate.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a low-voltage shielded gate MOSFET device and a manufacturing method thereof.
Background
Compared with the traditional trench MOSFET, the shielded gate MOSFET has the advantages of low on-resistance and low switching loss, so that the application of the shielded gate MOSFET in the middle and low voltage power semiconductor market is gradually increased. The grid electrode of the shielding grid groove type MOSFET structure simultaneously comprises the shielding grid and the control grid, the existence of the shielding grid enables the longitudinal electric field of the device to be similar to rectangular distribution when the device is broken down, and compared with the traditional groove type MOSFET, the device can obtain higher breakdown voltage by applying epitaxy with smaller resistivity, so that the device has smaller on-resistance. Shielded gate MOSFET devices are generally classified into an up-down structure and a left-right structure according to the relative positions of the shielded gate and the control gate in the trench. Because the field oxide layer of the low-voltage shielded gate MOSFET is thinner, and the grid electrodes on two sides of the shielded gate are too narrow, the low-voltage shielded gate MOSFET device generally adopts an up-down structure at present.
At present, a shielded gate MOSFET device with an upper structure and a lower structure is generally formed on a field Oxide layer, and after a polysilicon shielded gate is filled and etched back to form a shielded gate, HDP filling and etching back are adopted to form an Inter Poly Oxide (Inter Poly Oxide). The process method has higher cost; and with the reduction of the size of the device, the width of the groove is reduced, the depth-to-width ratio during HDP filling exceeds the optimal range, so that the filling thickness of an oxidation layer between grids of the device is not uniform, and the problems of cavities and the like are easy to occur, thereby causing the problems of larger electric leakage, poorer reliability and the like of the device.
Disclosure of Invention
The invention provides a low-voltage shielded gate MOSFET device and a manufacturing method thereof, which can effectively improve the reliability of the device, can be compatible with the existing process and can reduce the production cost, aiming at the above defects of the prior art.
The invention aims to realize a low-voltage shielded gate MOSFET device, which comprises a MOSFET device body, wherein the MOSFET device body mainly comprises an N epitaxial silicon substrate and a plurality of grooves etched in the N epitaxial silicon substrate, a field Oxide layer is formed on the inner wall of the middle lower part of each groove, a layer of shielded gate polysilicon is filled in the field Oxide layer, the top of the shielded gate polysilicon is provided with an Inter-gate Oxide layer (Inter Poly Oxide) etched by an Oxide layer, the top of the Inter-gate Oxide layer (Inter Poly Oxide) is provided with a control gate and a gate Oxide layer, and the gate Oxide layer is formed on the side wall of the upper part of each groove; and a layer of drain electrode formed by metal is arranged on the back surface of the N epitaxial silicon substrate.
Further, the cross section of the control gate is of an inverted trapezoid structure, the shape of the Inter-gate Oxide layer (Inter Poly Oxide) is similar to the cross section of the control gate, so that the width of the top of the Inter-gate Oxide layer (Inter Poly Oxide) is larger than that of the bottom of the Inter-gate Oxide layer (Inter Poly Oxide), and the tops of the control gate and the gate Oxide layer are flush with the top of the N epitaxial silicon substrate or slightly lower than the silicon surface.
A manufacturing method of a low-voltage shielded gate MOSFET device comprises the following steps:
1) depositing an oxide layer on the selected N epitaxial silicon substrate as a hard mask, photoetching a groove by using a first mask and carrying out deep groove etching to simultaneously form grooves of a cell region and a terminal region;
2) preparing a field oxide layer with corresponding thickness according to the requirement of the breakdown voltage of a product;
3) depositing polycrystalline silicon, performing active area photoetching by using a second mask plate, etching off the polycrystalline silicon with the depth of 0.5-1 um in the groove of the cell area to form shield gate polycrystalline silicon, and etching off the field oxide layer with the depth of 0.5-1 um in the groove;
4) thermal oxidation; generating an oxide layer on the side wall of the trench in the cell region, the top of the polysilicon of the shield grid and the silicon surface, wherein the oxide layer can completely fill the trench on the upper part of the shield grid in the cell region;
5) etching the Oxide layer on the top of the shielding grid of the cell region to form an Inter Poly Oxide (Inter Poly Oxide) of the device;
6) growing a gate oxide layer, and forming the gate oxide layer on the side wall of the trench in the primitive cell region;
7) depositing gate polysilicon, and etching the gate polysilicon to the silicon surface or slightly lower than the silicon surface by using chemical mechanical polishing or wet etching to form a control gate of the device;
8) carrying out body region injection and annealing to form a body region with the opposite conductivity type to the substrate and the epitaxial conductivity type;
9) performing source region photoetching by using a third mask, injecting impurities with the same conductivity type as the substrate and the epitaxy, and annealing to form a heavily doped source region;
10) depositing a dielectric layer, performing contact hole photoetching by using a fourth mask, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole;
11) sputtering top metal, and photoetching and etching by using a fifth mask to form the top metal;
12) depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using a sixth mask to finish the manufacturing of the top layer structure;
13) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form the drain electrode of the device.
Further, in the step 1), the thickness of the deposited oxide layer is 0.5-1 um; in the step 2), the field oxide layer may be formed by thermal oxidation, or may be formed by thermal oxidation and deposition of an oxide layer.
Further, in the step 5), the Oxide layer on the top of the cell area shielding gate is etched to form an Inter-gate Oxide layer (Inter Poly Oxide) of 0.2-0.4 um.
The invention has the beneficial technical effects that: the low-voltage shielded gate MOSFET device generates the thick Oxide layer to fill the trench at the top of the shielded gate through thermal oxidation, replaces the conventional process of filling through HDP, avoids the problems of process difficulty and poor quality and uniformity of an Inter-gate Oxide layer (Inter Poly Oxide) caused by the fact that HDP filling is carried out on the low-voltage product with small trench width, and meanwhile, the preparation method is compatible with the whole process steps, the device is safer and more reliable, and meanwhile, the production cost is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of the deep trench etching of the present invention;
FIG. 2 is a schematic diagram illustrating the growth of a field oxide layer according to the present invention;
FIG. 3 is a schematic diagram of the shield gate polysilicon filling and etch back of the present invention;
FIG. 4 is a schematic view illustrating the thermal oxide trench filling according to the present invention;
FIG. 5 is a schematic diagram of the formation of Inter Poly Oxide (Inter Poly Oxide) of the present invention;
fig. 6 is a schematic diagram of the body of a MOSFET device according to the present invention;
FIG. 7 is a graph showing simulation results of thermal oxide trench filling according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood by those skilled in the art, the present invention is further described with reference to the accompanying drawings and examples.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", "inside", "outside", "lateral", "vertical", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description of the present invention, and do not indicate or imply that the device or element referred to must have a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1-7, the low-voltage shielded gate MOSFET device of the present invention includes a MOSFET device body, wherein the MOSFET device body mainly includes an N-epi silicon substrate 2 and a plurality of trenches 3 etched in the N-epi silicon substrate 2, a field Oxide layer 4 is formed on an inner wall of a middle lower portion of each trench 3, a layer of shielded gate polysilicon 5 is filled in the field Oxide layer 4, a Inter-gate Oxide layer (Inter Poly Oxide) 7 etched from an Oxide layer 6 is disposed on a top of the shielded gate polysilicon 5, a control gate 9 and a gate Oxide layer 8 are disposed on a top of the Inter-gate Oxide layer (Inter Poly Oxide) 7, and the gate Oxide layer 8 is formed on an upper sidewall of each trench 3; the back of the N epitaxial silicon substrate 2 is provided with a layer of drain electrode 1 formed by metal.
Referring to fig. 6, the cross section of the control gate 9 is an inverted trapezoid structure and the shape of the Inter-gate Oxide layer (Inter Poly Oxide) 7 is similar to the cross section of the control gate 9, so that the top width of the Inter-gate Oxide layer (Inter Poly Oxide) 7 is greater than the bottom width, and the tops of the control gate 9 and the gate Oxide layer 8 are flush with or slightly lower than the top of the N-epi silicon substrate 2.
A method for manufacturing a low-voltage shielded gate MOSFET device comprises the steps of growing an Oxide layer on the side wall of a groove and the top of a shielded gate by utilizing a thermal oxidation process after the shielded gate is formed, wherein the Oxide layer is thick enough to completely fill the groove on the upper part of the shielded gate, and then carrying out back etching on the Oxide layer to form an Inter-gate Oxide layer (Inter Poly Oxide) between the shielded gate and a control gate. The preparation method provided by the invention avoids the traditional mode of forming the Inter-gate Oxide (Inter Poly Oxide) by HDP filling, reduces the production cost, forms the Inter-gate Oxide (Inter Poly Oxide) with better quality and uniformity, is compatible with the prior art, and is safe and reliable. The specific manufacturing method comprises the following steps:
1) depositing an oxide layer of 0.5-1 um as a hard mask on a selected N epitaxial silicon substrate 2, photoetching a groove 3 by using a first mask and performing deep groove etching to simultaneously form grooves of a cell region and a terminal region, as shown in FIG. 1;
2) preparing a field oxide layer 4 with a corresponding thickness according to the requirement of the product breakdown voltage, wherein the field oxide layer 4 can be formed by thermal oxidation or by a thermal oxidation plus deposition oxide layer manner, as shown in fig. 2;
3) depositing polycrystalline silicon, performing active area photoetching by using a second mask plate of the invention, etching off the polycrystalline silicon with the depth of 0.5-1 um in the groove 3 of the cell area to form a shield gate polycrystalline silicon 5, and etching off the field oxide layer 4 with the depth of 0.5-1 um in the groove 3, as shown in figure 3;
4) thermal oxidation; forming an oxide layer 6 on the sidewall of the trench 3 in the cell region, the top of the polysilicon of the shield gate and the silicon surface, wherein the oxide layer 3 can completely fill the trench on the upper portion of the shield gate in the cell region, as shown in fig. 4;
5) etching the Oxide layer 6 on the top of the cell region shielding gate to make the thickness of the Oxide layer on the top of the cell region shielding gate be 0.2-0.4 um to form an Inter-gate Oxide layer (Inter Poly Oxide) 7 of the device, as shown in fig. 5;
6) carrying out gate oxide growth, and forming a gate oxide layer 8 on the side wall of the trench in the primitive cell region;
7) depositing gate polysilicon, and etching the gate polysilicon to the silicon surface or slightly lower than the silicon surface by using chemical mechanical polishing or wet etching to form a control gate 9 of the device, as shown in fig. 6;
8) carrying out body region injection and annealing to form a body region with the opposite conductivity type to the substrate and the epitaxial conductivity type;
9) carrying out source region photoetching by using the third mask plate, injecting impurities with the same conductivity type as the substrate and the epitaxy, and annealing to form a heavily doped source region;
10) depositing a dielectric layer, carrying out contact hole photoetching by using a fourth mask of the invention, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole;
11) sputtering top metal, and photoetching and etching by utilizing a fifth mask plate to form the top metal;
12) depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by utilizing a sixth mask to complete the manufacture of a top layer structure;
13) the back of the silicon chip is thinned to a specific thickness, and back metal is deposited by a sputtering or evaporation method to form the drain electrode 1 of the device.
According to the invention, after the shielding gate is formed, an oxidation layer grows on the side wall of the groove and the top of the shielding gate by utilizing a thermal oxidation process, the oxidation layer is thick enough to completely fill the groove on the upper part of the shielding gate, and the oxidation layer is subsequently etched back to form an Inter-gate oxidation layer (Inter Poly Oxide) between the shielding gate and the control gate. The preparation method provided by the invention avoids the traditional mode of forming an Inter-gate Oxide (Inter Poly Oxide) by HDP filling, forms the Inter-gate Oxide (Inter Poly Oxide) with better quality and uniformity, and improves the reliability of the device; meanwhile, the preparation method reduces the production cost, is compatible with the existing process, and is safe and reliable. In addition, the device design method is not only suitable for low-voltage shielded gate MOSFET, but also suitable for medium-high voltage trench type MOSFET devices with small trench width.
The specific embodiments described herein are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. A low voltage shielded gate MOSFET device comprising a MOSFET device body, characterized in that: the MOSFET device body mainly comprises an N epitaxial silicon substrate and a plurality of grooves etched in the N epitaxial silicon substrate, wherein a field oxide layer is formed on the inner wall of the middle lower part of each groove, a shielding grid polycrystalline silicon layer is filled in the field oxide layer, an inter-grid oxide layer formed by etching the oxide layer is arranged on the top of the shielding grid polycrystalline silicon layer, a control grid and a grid oxide layer are arranged on the top of the inter-grid oxide layer, and the grid oxide layer is formed on the side wall of the upper part of each groove; and a layer of drain electrode formed by metal is arranged on the back surface of the N epitaxial silicon substrate.
2. The low voltage shielded gate MOSFET device of claim 1, wherein: the cross section of the control gate is of an inverted trapezoid structure, the shape of the inter-gate oxide layer is similar to that of the cross section of the control gate, so that the width of the top of the inter-gate oxide layer is larger than that of the bottom of the inter-gate oxide layer, and the tops of the control gate and the gate oxide layer are flush with the top of the N epitaxial silicon substrate or slightly lower than the silicon surface.
3. A method of fabricating a low voltage shielded gate MOSFET device as claimed in claim 1 or claim 2, wherein: the manufacturing method comprises the following steps:
1) depositing an oxide layer on the selected N epitaxial silicon substrate as a hard mask, photoetching a groove by using a first mask and carrying out deep groove etching to simultaneously form grooves of a cell region and a terminal region;
2) preparing a field oxide layer with corresponding thickness according to the requirement of the breakdown voltage of a product;
3) depositing polycrystalline silicon, performing active area photoetching by using a second mask plate, etching off the polycrystalline silicon with the depth of 0.5-1 um in the groove of the cell area to form shield gate polycrystalline silicon, and etching off the field oxide layer with the depth of 0.5-1 um in the groove;
4) thermal oxidation; generating an oxide layer on the side wall of the trench in the cell region, the top of the polysilicon of the shield grid and the silicon surface, wherein the oxide layer can completely fill the trench on the upper part of the shield grid in the cell region;
5) etching the oxide layer on the top of the shielding grid of the cell region to form an inter-grid oxide layer of the device;
6) growing a gate oxide layer, and forming the gate oxide layer on the side wall of the trench in the primitive cell region;
7) depositing gate polysilicon, and etching the gate polysilicon to the silicon surface or slightly lower than the silicon surface by using chemical mechanical polishing or wet etching to form a control gate of the device;
8) carrying out body region injection and annealing to form a body region with the opposite conductivity type to the substrate and the epitaxial conductivity type;
9) performing source region photoetching by using a third mask, injecting impurities with the same conductivity type as the substrate and the epitaxy, and annealing to form a heavily doped source region;
10) depositing a dielectric layer, performing contact hole photoetching by using a fourth mask, and etching to form a source electrode, a grid electrode and a shielding grid electrode contact hole;
11) sputtering top metal, and photoetching and etching by using a fifth mask to form the top metal;
12) depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using a sixth mask to finish the manufacturing of the top layer structure;
13) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form the drain electrode of the device.
4. The method of manufacturing according to claim 3, wherein: in the step 1), the thickness of the deposited oxide layer is 0.5-1 um; in the step 2), the field oxide layer may be formed by thermal oxidation, or may be formed by thermal oxidation and deposition of an oxide layer.
5. The method of manufacturing according to claim 3, wherein: and in the step 5), etching the oxide layer on the top of the shielding grid of the cell region to form an inter-grid oxide layer with the thickness of 0.2-0.4 um.
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| CN202110823695.3A CN113517350A (en) | 2021-07-21 | 2021-07-21 | Low-voltage shielding grid MOSFET device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116565010A (en) * | 2023-04-10 | 2023-08-08 | 浙江广芯微电子有限公司 | Manufacturing method of shielded gate trench type MOS device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116565010A (en) * | 2023-04-10 | 2023-08-08 | 浙江广芯微电子有限公司 | Manufacturing method of shielded gate trench type MOS device |
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