CN116721925B - SBD integrated silicon carbide SGT-MOSFET and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide SGT-MOSFET of an integrated SBD and a preparation method thereof, wherein the silicon carbide SGT-MOSFET of the integrated SBD comprises: the semiconductor device comprises a silicon carbide substrate, an N-type drift region, a first groove, a second groove, a first P+ type doped region, a second P+ type doped region, a P well region, an N+ type doped region, a first ohmic contact region, a Schottky contact region, a shielding gate, a control gate, a second ohmic contact region and the like, wherein the first groove and the second groove are arranged in the N-type drift region, and the second ohmic contact region is arranged on the other surface of the silicon carbide substrate. According to the invention, the reverse breakdown voltage is effectively improved through the two P+ type doped regions, the reverse electric leakage is reduced, the metal layer is deposited above the second groove to form the embedded SBD, the embedded SBD can optimize the problem of low surge resistance of the body diode of the traditional MOSFET, and the reverse follow current capability can be enhanced.

Description

Silicon carbide SGT-MOSFET integrated with SBD and preparation method thereof

Technical field

The invention belongs to the technical field of power semiconductors, and specifically relates to an SBD-integrated silicon carbide SGT-MOSFET and a preparation method thereof.

Background technique

Power devices have a series of advantages such as high switching speed, high withstand voltage, and good thermal stability. They have been widely used in various complex working environments, such as industrial control, power supplies, portable appliances, consumer electronics, and automotive electronics. As well as aviation, aerospace and other fields. The third generation of semiconductor materials represented by SiC has become an ideal material for the preparation of high-voltage, high-temperature, high-power, and radiation-resistant power electronic devices due to its excellent material properties.

The reverse leakage of existing trench SiC MOSFETs is relatively large, resulting in high power consumption when the entire device is turned off, severe device heating, reduced reliability, and in severe cases, gate performance degradation and failure. In addition, the existing silicon carbide MOSFET has poor recovery characteristics because there is no insertion of the shield gate SG. The reverse recovery peak current Irm, reverse recovery time Trr and reverse recovery charge Qrr are all large, seriously affecting the switching speed and switching loss of the SiC MOSFET. . In addition, the existing MOSFET does not have an embedded SBD, which causes the instantaneous current in the loop to pass through the body diode, seriously degrading the performance of the entire MOSFET.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide an SBD-integrated silicon carbide SGT-MOSFET and a preparation method thereof.

To achieve the above objectives, the present invention provides an SBD-integrated silicon carbide SGT-MOSFET, including:

silicon carbide substrate;

An N-type drift region is located on one surface of the silicon carbide substrate;

A first trench and a second trench disposed in the N-type drift region;

The first trench and the second trench are separated by a partition wall; the partition wall is obtained by ion implantation from an unetched N-type drift region;

A first P+ type doping region is provided at the bottom of the first trench;

A second P+ type doped region is provided at the bottom of the second trench;

A P-well region is provided in the partition wall;

An N+-type doped region is located above the P-well region;

A first ohmic contact region is located above the N+ type doped region;

A first oxide layer and a second oxide layer are provided at the bottom and sides of the second trench, and a mounting hole is provided on the first oxide layer at the bottom, and a Schottky contact area formed by SBD is provided in the mounting hole;

A third oxide layer is provided above the Schottky contact area, and a shielding gate is provided on the third oxide layer;

The Schottky contact area and the shielding grid are closely attached, and are connected together with the first ohmic contact area through the layout as the source of the power device;

a fourth oxide layer provided above the shielding gate, and a control gate provided above the fourth oxide layer;

Wherein, the control gate and the shielding gate are arranged in parallel, the lower end of the control gate and the shielding gate are spaced by a fourth oxide layer, the side surfaces of the control gate are arranged opposite to the P-well region, and the side surfaces of the control gate and the P-well region are separated by a third oxide layer. Dioxide layer spacing arrangement;

Prevent leakage by depositing a passivation layer above the control gate and above the first trench;

A second ohmic contact area is provided on another surface of the silicon carbide substrate.

Further, the doping concentration of the first P+ type doping region and the second P+ type doping region are consistent and higher than the doping concentration of the N- type drift region and the P well region.

Further, the etching width or depth of the first trench in the N-type drift region is smaller than the etching width or depth of the second trench in the N-type drift region.

Further, a first metal layer is deposited at the bottom of the second trench. The first metal layer is not in contact with the partition wall and is partially in contact with the second P+ type doped region at the bottom. It is annealed at high temperature to form a gold half contact to form Schottky contact zone.

Further, the first P+ type doped region, the second P+ type doped region and the P well region have the same conductivity type, and the P well region and the N+ type doped region have different conductivity types. Conductivity type.

Further, the width of the second trench is greater than the width of the Schottky contact area or the shield gate.

Further, the thickness of the Schottky contact area is smaller than the thickness of the shielding grid, and the thickness of the shielding grid is smaller than the thickness of the control grid.

Further, a second metal layer is deposited above the N+ type doped region to form a first ohmic contact region.

The invention also provides a method for preparing an SBD-integrated silicon carbide SGT-MOSFET, including:

Provide silicon carbide substrate;

growing an N-type drift region on one surface of the silicon carbide substrate;

Etching a first trench and a second trench in the N-type drift region, the etching depth of the first trench in the N-type drift region being smaller than the etching depth of the second trench in the N-type drift region corrosion depth;

Perform Al ion implantation at the bottom of the first trench to form two adjacent first P+ type doped regions separated by an N-type drift region;

Al ion implantation is performed at the bottom of the second trench to form two second P+ type doped regions of equal size;

Perform Al ion implantation into the partition wall between the first trench and the second trench to form a P-well region;

Perform N ion implantation above the P well region to form an N+ type doped region;

Metal deposition is performed above the N+ type doped area and annealed at high temperature to form the first ohmic contact area;

Deposit a first oxide layer and a second oxide layer on the bottom and sides of the second trench, and open holes on the first oxide layer on the bottom surface to deposit SBD to form a Schottky contact area;

Deposit a third oxide layer above the Schottky contact area, and open holes on the third oxide layer to deposit doped polysilicon to form a shield gate;

depositing a fourth oxide layer above the shield gate, and then depositing doped polysilicon above the fourth oxide layer to form a control gate;

Wherein, the control gate and the shielding gate are arranged in parallel, the lower end of the control gate and the shielding gate are spaced by a fourth oxide layer, the side surfaces of the control gate are arranged opposite to the P-well region, and the side surfaces of the control gate and the P-well region are separated by a third oxide layer. Dioxide layer spacing arrangement;

Thin the silicon carbide substrate and sputter metal ions on the other surface of the silicon carbide substrate to form an electrode.

Further, the implantation depth of Al ions in the second P+ type doped region at the bottom of the second trench is equal to the implantation depth of Al ions in the first P+ type doped region at the bottom of the first trench.

Further, the material of the first oxide layer, the second oxide layer, the third oxide layer and the fourth oxide layer is silicon dioxide.

The invention has the following beneficial effects:

1. Under the same breakdown voltage, the present invention increases the doping concentration of the drift region by introducing a shield gate, thereby reducing the on-resistance of the drift region. Moreover, the shield gate can also effectively reduce the gate drain capacitance and gate charge, thereby improving On-off level;

2. In the present invention, due to the reduction of gate-drain capacitance and gate charge, the switching time is reduced, so the energy consumed by each switch is lower;

3. The present invention can effectively reduce the source leakage Idss during turn-off, and solve the problem that excessive source leakage Idss during turn-off causes the power consumption of the entire device to increase in the blocking state, and at the same time, the heat generation continues to rise. Overheating of the device will reduce the reliability of the device and cause the risk of failure. This improves the reliability of the entire device and prevents the device from failing due to local overheating;

4. The present invention embeds the SBD at the bottom of the trench. When there is an inductor in the loop, the instantaneous small current can continue to flow through the SBD to prevent the body diode of the MOSFET itself from working, thereby causing the performance degradation of the entire MOSFET. , and the present invention integrates the SBD inside the MOSFET, eliminating the need for an external SBD, which reduces the entire chip packaging cost. In addition, the integrated SBD also improves the freewheeling aspect.

Description of drawings

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on the drawings without exerting creative efforts.

Figure 1 is an overall structural diagram of an SBD-integrated silicon carbide SGT-MOSFET according to some embodiments of the present invention;

Figure 2 is a cross-sectional view of the chip of a silicon carbide SGT-MOSFET integrated with SBD after etching trenches according to some embodiments of the present invention;

Figure 3 is a cross-sectional view of the chip after ion implantation of the SBD-integrated silicon carbide SGT-MOSFET according to some embodiments of the present invention;

Figure 4 is a cross-sectional view of the SBD-integrated silicon carbide SGT-MOSFET after depositing a metal layer to form the first ohmic contact area and the Schottky contact area in some embodiments of the present invention;

Figure 5 is a cross-sectional view of an SBD-integrated silicon carbide SGT-MOSFET after forming a shield gate and a control gate according to some embodiments of the present invention;

Figure 6 is a cross-sectional view of the SBD-integrated silicon carbide SGT-MOSFET according to some embodiments of the present invention after chemical mechanical polishing, thinning the back and depositing a metal layer to form a second ohmic contact area.

The reference numbers in the specific implementation are as follows:

Silicon carbide substrate 1, N-type drift region 2, second P+ type doped region 3, first P+ type doped region 6, P well region 4, N+ type doped region 5, Schottky contact region 7, Shield gate 8 , control gate 9 , silicon dioxide 10 , first ohmic contact area 11 and second ohmic contact area 12 .

Detailed ways

In order to better explain the purpose, technical solutions and advantages of the present invention, the present invention will be further described below with reference to specific embodiments.

Please refer to Figure 1. In one embodiment of the present invention, the present invention provides an SBD-integrated silicon carbide SGT-MOSFET, including:

Silicon carbide substrate 1;

N-type drift region 2 is located on one surface of the silicon carbide substrate 1;

The first trench and the second trench provided in the N-type drift region 2;

The first trench and the second trench are separated by a partition wall of a certain thickness, and the partition wall is obtained by ion implantation from the unetched N-type drift region 2;

The first P+ type doped region 6 is provided at the bottom of the first trench, the second P+ type doped region 3 is provided at the bottom of the second trench, and the P well region 4 is provided in the partition wall. , the second P+ type doped region 3 and the first P+ type doped region 6 are formed by injecting Al ions at the bottom of the trench. In the off state, the depletion region formed between the two P+ type doped regions can be well Prevent source leakage. Furthermore, when the P well region 4 is depleted toward the N-type drift region 2, the source leakage of the entire device can also be reduced twice. The depletion region formed by the two P+ type doped regions and the P The depletion region formed in the well region can greatly reduce the source leakage of the device in the off state, and can also reduce the power consumption of the entire device. It averages the heating area of the device from one point to the entire surface, avoiding overheating failure of the device. risks of;

N+ type doped region 5 is located above the P well region 4;

The first ohmic contact region 11 is located above the N+ type doped region 5;

A first oxide layer and a second oxide layer are provided at the bottom and sides of the second trench. The first oxide layer at the bottom is provided with a mounting hole, and a Schottky contact area 7 formed by SBD is provided in the mounting hole. Embed the SBD at the bottom of the trench. When there is an inductor in the loop, the instantaneous small current can continue to flow through the SBD, preventing the body diode of the MOSFET itself from working, thus causing the performance degradation of the entire MOSFET. Moreover, in the trench The SBD barrier introduced at the bottom is lower and the starting voltage is reduced. In the case of small current freewheeling, only the Schottky contact area 7 can open freewheeling. In the case of large current inrush, the second P+ type The ohmic contact formed by the partial contact between the doped region 3 and the metal layer deposited above the second trench can be turned on, thereby realizing a large current freewheeling and preventing the MOSFET body diode from turning on and causing the performance of the entire MOSFET to decline;

A third oxide layer is provided above the Schottky contact area, and a shield gate 8 is provided on the third oxide layer. The introduction of the shield gate 8 can improve the withstand voltage and reduce the on-resistance. The most important thing is the shield gate. The introduction of the separation of the control gate and drain can greatly reduce the gate-to-drain capacitance, that is, the Miller capacitance, thereby increasing the switching rate of the entire device;

By introducing the shielding gate 8 to act as a field plate in the body, it assists the depletion of the N-type drift region 2 during forward blocking, reaching a higher breakdown voltage Vbr, and the shielding gate isolates the control gate and the drain, which greatly improves the Reducing the gate-to-drain capacitance Cgd, that is, the Miller capacitance, effectively increases the switching rate of the MOSFET, thereby reducing switching losses.

The Schottky contact area 7 and the shielding gate 8 are closely adhered to each other, and are connected together with the first ohmic contact area 11 through the layout as the source of the power device;

A fourth oxide layer provided above the shield gate 8, and a control gate 9 provided above the fourth oxide layer;

Among them, the control gate 9 and the shield gate 8 are arranged in parallel, and the lower end of the control gate 9 and the shield gate 8 are spaced by a fourth oxide layer. The side surfaces of the control gate 9 are arranged opposite to the P-well region 4, and the side surfaces of the control gate 9 are arranged opposite to the P-well region 4. The P-well regions 4 are spaced apart by a second oxide layer;

The passivation layer silicon dioxide 10 deposited above the control gate 9 and the first trench prevents leakage;

A second ohmic contact area 12 is provided on the other surface of the silicon carbide substrate 1 .

The first P+ type doped region 6 has the same doping concentration as the second P+ type doped region 3 , and is higher than the doping concentration of the N- type drift region 2 and the P well region 4 .

The etching width or depth of the first trench in the N-type drift region 2 is smaller than the etching width or depth of the second trench in the N-type drift region 2 .

A first metal layer is deposited at the bottom of the second trench. The first metal layer does not contact the partition wall and is partially in contact with the second P+ type doped region 3 at the bottom. It is annealed at high temperature to form a gold half contact to form a Schott. Base contact area 7.

The first P+ type doped region 6, the second P+ type doped region 3 and the P well region 4 have the same conductivity type, and the P well region 4 and the N+ type doped region 5 have the same conductivity type. Different conductivity types.

The width of the second trench is greater than the width of the Schottky contact area 7 or the shield gate 8 .

The thickness of the Schottky contact area 7 is smaller than the thickness of the shielding grid 8 , and the thickness of the shielding grid 8 is smaller than the thickness of the control grid 9 .

A second metal layer is deposited above the N+ type doped region 5 to form a first ohmic contact region 11 .

The second P+ type doping region 3, the first P+ type doping region 6 and the P well region 4 are implanted with the same ions, but the implantation energy and depth used are different. The P+ type doping in the second trench In order to save costs, the same process conditions can be used for implantation in region 3 and the P+ type doped region 6 in the first trench.

The N+ type doped region 5 and the P well region 4 have different implanted ion types.

The bottom of the first P+ type doped region 6 is higher than the top of the second P+ type doped region 3 .

The bottom of the P-well region 4 is lower than the top of the first P+-type doped region 6, but higher than the bottom of the first P+-type doped region 6, and the P-well region 4 and the first P+-type doped region Region 6 is isolated by a certain thickness of N-type drift region 2.

The implantation depth of the first P+ type doped region 6 is smaller than the implantation depth of the P-well region 4 .

The implantation depth of the N+ type doped region 5 is much smaller than the implantation depth of the P-well region 4 .

In one embodiment of the present invention, the reverse breakdown voltage is effectively increased and the reverse leakage is reduced through two P+ type doped regions. A metal layer is deposited above the second trench to form an embedded SBD. The embedded SBD is The problem of low surge resistance of the body diode of the traditional MOSFET can be optimized, and the reverse freewheeling capability is also enhanced, and a shield gate (SGT) is deposited above the embedded SBD. Under the same breakdown voltage, by introducing the shield gate The doping concentration of the drift region is increased, thereby reducing the on-resistance of the drift region. Moreover, the shielded gate can also effectively reduce the gate-drain capacitance and gate charge, thereby increasing the switching frequency. By introducing SBD under the SGT, the present invention not only improves the switching frequency frequency, enhanced voltage resistance level, and improved reverse freewheeling and surge resistance capabilities.

In one embodiment of the present invention, the present invention also provides a method for preparing an SBD-integrated silicon carbide SGT-MOSFET, including:

Provide silicon carbide substrate 1;

Grow an N-type drift region 2 on one surface of the silicon carbide substrate 1;

Etching a first trench and a second trench in the N-type drift region 2, the etching depth of the first trench being smaller than the etching depth of the second trench;

Perform Al ion implantation at the bottom of the first trench to form adjacent first P+ type doped regions 6 separated by N-type drift regions 2;

Al ion implantation is performed at the bottom of the second trench to form two second P+ type doped regions 3 of equal size;

Perform Al ion implantation into the partition wall between the first trench and the second trench to form a P-well region 4;

Perform N ion implantation above the P well region 4 to form an N+ type doped region 5;

Metal deposition is performed above the N+ type doped region 5 and annealed at high temperature to form the first ohmic contact region 11;

The first oxide layer and the second oxide layer are deposited on the bottom and sides of the second trench, and SBD is deposited on the first oxide layer on the bottom surface to form a Schottky contact area 7. The Schottky contact area 7 and the partition wall are not Contact, and partial contact with two second P+ type doped regions 3 of equal size;

Deposit a third oxide layer above the Schottky contact area, and open holes on the third oxide layer to deposit doped polysilicon to form a shield gate 8;

Deposit a fourth oxide layer above the shield gate, then deposit doped polysilicon above the fourth oxide layer to form a control gate 9, and then deposit a certain passivation layer silicon dioxide 10 above the control gate 9;

Among them, the control gate 9 and the shield gate 8 are arranged in parallel, and the lower end of the control gate 9 and the shield gate 8 are spaced by a fourth oxide layer. The side surfaces of the control gate 9 are arranged opposite to the P-well region 4, and the side surfaces of the control gate 9 are arranged opposite to the P-well region 4. The P-well regions 4 are spaced apart by a second oxide layer;

The silicon carbide substrate 1 is thinned, and metal ions are sputtered on the other surface of the silicon carbide substrate to form an electrode.

The Al ion implantation depth of the second P+ type doped region 3 at the bottom of the second trench is equal to the Al ion implantation depth of the first P+ type doped region 6 at the bottom of the first trench.

The material of the first oxide layer, the second oxide layer, the third oxide layer and the fourth oxide layer is silicon dioxide.

Within one embodiment of the present invention, the present invention provides an SBD-integrated silicon carbide SGT MOSFET, including:

Silicon carbide substrate 1;

epitaxially growing the N-type drift region 2 on one surface of the silicon carbide substrate 1;

A first trench and a second trench are etched in the N-type drift region 2, as shown in Figure 2;

Al ions are implanted at the bottom of the first trench and the second trench respectively to form the second P+ type doped region 3 and the first P+ type doped region 6, which serve as the first depletion region during turn-off to prevent source leakage. And bear its blocking withstand voltage, perform Al ion implantation above the N-type drift region 2 to form the P-well region 4, which serves as the second depletion region to reduce the field intensity distribution of the entire device;

N ions are implanted above the P well region 4 to form an N+ type doped region 5, as shown in Figure 3;

Metal deposition is performed on the upper surface of the N+ type doped region 5 to form a first ohmic contact region 11;

A metal layer is deposited at the bottom of the second trench to form the Schottky contact region 7. Since the Schottky contact region 7 is located between the two second P+ type doped regions 3, in the off state, the first depletion regions on both sides will They are connected together to withstand the reverse withstand voltage, and the rest of the bottom of the trench is filled with silicon dioxide 10, as shown in Figure 4;

Doped polysilicon is deposited on the Schottky contact area 7 to form a shield gate (SGT) 8. The shield gate (SGT) 8 formed in the trench can be used as a field plate in the longitudinal direction to adjust the distribution of the internal electric field of the SGT-MOSFET, thereby improving the Rated withstand voltage of the entire chip;

The Schottky contact area 7, the shield gate 8 and the first ohmic contact area 11 are interconnected and jointly serve as the source of the SGT MOSFET. The Schottky contact area 7 of the integrated SBD can achieve freewheeling under small current conditions, preventing the MOSFET from The conduction of the body diode solves the problem of serious performance degradation of the entire MOSFET;

Grow an oxide layer of silicon dioxide 10 above the shield gate 8, leaving a predetermined thickness and the SGT shield gate to prevent short circuit between the gate and the source, then etch the trench oxide layer at an appropriate position to an appropriate depth, and deposit Dope polysilicon to form a control gate 9, and finally deposit silicon dioxide 10 to fill the trench, and then use CMP technology to remove excess silicon dioxide from the metal surface, as shown in Figure 5;

The substrate is thinned to 150 μm, and metal is deposited on the other surface of the silicon carbide substrate 1, and then laser annealed to form the second ohmic contact region 12, as shown in Figure 6.

It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be regarded as illustrative and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is therefore intended that all claims falling within the claims All changes within the meaning and scope of equivalent elements are included in the present invention, and any sign in a claim should not be construed as limiting the claim involved.

Claims (9)

1. A SBD integrated silicon carbide SGT-MOSFET comprising:

a silicon carbide substrate;

an N-type drift region on one surface of the silicon carbide substrate;

a first trench and a second trench disposed within the N-type drift region;

the first groove and the second groove are separated by a partition wall; the partition wall is obtained by ion implantation of an N-type drift region which is not etched;

the first P+ type doped region is arranged at the bottom of the first groove;

the second P+ type doped region is arranged at the bottom of the second groove;

the P well region is arranged in the partition wall;

the N+ type doped region is positioned above the P well region;

the first ohmic contact region is positioned above the N+ type doped region;

the first oxide layer at the bottom and the side surface of the second groove are provided with a mounting hole, and a Schottky contact area formed by SBD is arranged in the mounting hole;

a third oxide layer arranged above the Schottky contact region, and a shielding grid arranged on the third oxide layer;

the Schottky contact area is tightly attached to the shielding grid, and the Schottky contact area and the shielding grid are jointly used as a source electrode of the power device to be connected through the layout;

a fourth oxide layer arranged above the shielding grid, and a control grid arranged above the fourth oxide layer;

the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through the second oxide layer;

preventing electric leakage above the control gate and above the first trench by a deposited passivation layer;

a second ohmic contact region is arranged on the other surface of the silicon carbide substrate;

a first metal layer is deposited at the bottom of the second groove, the first metal layer is not contacted with the partition wall and is contacted with a second P+ type doped region part at the bottom, a metal-semiconductor contact is formed by high-temperature annealing to form a Schottky contact region, the first metal layer is contacted with the second P+ type doped region part to form ohmic contact, and the Schottky contact region is positioned between the two second P+ type doped regions;

the bottom of the P well region is lower than the top of the first P+ type doped region, but higher than the bottom of the first P+ type doped region structure;

and the implantation depth of the first P+ type doped region is smaller than that of the P well region.

2. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the first p+ type doped region has a doping concentration that is consistent with the doping concentration of the second p+ type doped region and higher than the doping concentrations of the N-type drift region and the P-well region.

3. The SBD integrated silicon carbide SGT-MOSFET of claim 1 wherein the first trench has an etch width or depth within the N-type drift region that is less than the etch width or depth of the second trench within the N-type drift region.

4. The SBD integrated silicon carbide SGT-MOSFET of claim 1 wherein the first p+ doped region, and the P-well region have the same conductivity type, and the P-well region and the n+ doped region have different conductivity types.

5. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the second trench has a width greater than a width of the schottky contact region or the shield gate.

6. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the schottky contact region has a thickness less than a thickness of a shield gate, the shield gate having a thickness less than a thickness of a control gate.

7. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein a second metal layer is deposited over the n+ doped region to form a first ohmic contact region.

8. A method of making a SBD integrated silicon carbide SGT-MOSFET according to any one of claims 1 to 7, comprising:

providing a silicon carbide substrate;

growing an N-type drift region on one surface of a silicon carbide substrate;

etching a first groove and a second groove in the N-type drift region, wherein the etching depth of the first groove in the N-type drift region is smaller than that of the second groove in the N-type drift region;

al ion implantation is carried out at the bottom of the first groove to form two adjacent first P+ type doped regions separated by an N-type drift region;

al ion implantation is carried out at the bottom of the second groove to form two second P+ type doped regions with equal size;

performing Al ion implantation on the partition wall between the first groove and the second groove to form a P well region;

n ion implantation is carried out above the P well region, and an N+ type doped region is formed;

performing metal deposition and high-temperature annealing on the upper part of the N+ type doped region to form a first ohmic contact region;

depositing a first oxide layer and a second oxide layer on the bottom and the side surface of the second groove, and opening a hole on the first oxide layer on the bottom surface to deposit an SBD (styrene-butadiene-styrene) to form a Schottky contact area;

depositing a third oxide layer above the Schottky contact region, and opening a hole on the third oxide layer to deposit doped polysilicon to form a shielding gate;

depositing a fourth oxide layer above the shielding gate, and then depositing doped polysilicon above the fourth oxide layer to form a control gate;

the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through a second oxide layer;

thinning the silicon carbide substrate, and sputtering metal ions on the other surface of the silicon carbide substrate to prepare an electrode.

9. The method of claim 8, wherein the second p+ type doped region Al ion implantation depth at the bottom of the second trench is equal to the first p+ type doped region Al ion implantation depth at the bottom of the first trench.