CN116721925B - SBD integrated silicon carbide SGT-MOSFET and preparation method thereof - Google Patents
SBD integrated silicon carbide SGT-MOSFET and preparation method thereof Download PDFInfo
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- CN116721925B CN116721925B CN202310986654.5A CN202310986654A CN116721925B CN 116721925 B CN116721925 B CN 116721925B CN 202310986654 A CN202310986654 A CN 202310986654A CN 116721925 B CN116721925 B CN 116721925B
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 56
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- FACXGONDLDSNOE-UHFFFAOYSA-N buta-1,3-diene;styrene Chemical compound C=CC=C.C=CC1=CC=CC=C1.C=CC1=CC=CC=C1 FACXGONDLDSNOE-UHFFFAOYSA-N 0.000 claims description 43
- 229920000468 styrene butadiene styrene block copolymer Polymers 0.000 claims description 43
- 238000005468 ion implantation Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 17
- 238000005192 partition Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229910021645 metal ion Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 7
- 238000006731 degradation reaction Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H01L29/66068—
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- H01L29/4236—
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- H01L29/7806—
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- H01L29/7813—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide SGT-MOSFET of an integrated SBD and a preparation method thereof, wherein the silicon carbide SGT-MOSFET of the integrated SBD comprises: the semiconductor device comprises a silicon carbide substrate, an N-type drift region, a first groove, a second groove, a first P+ type doped region, a second P+ type doped region, a P well region, an N+ type doped region, a first ohmic contact region, a Schottky contact region, a shielding gate, a control gate, a second ohmic contact region and the like, wherein the first groove and the second groove are arranged in the N-type drift region, and the second ohmic contact region is arranged on the other surface of the silicon carbide substrate. According to the invention, the reverse breakdown voltage is effectively improved through the two P+ type doped regions, the reverse electric leakage is reduced, the metal layer is deposited above the second groove to form the embedded SBD, the embedded SBD can optimize the problem of low surge resistance of the body diode of the traditional MOSFET, and the reverse follow current capability can be enhanced.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide SGT-MOSFET integrated with an SBD and a preparation method thereof.
Background
The power device has a series of advantages of high switching speed, high voltage resistance, good thermal stability and the like, and is widely applied to various complex working environments at present, such as industrial control, power supply, portable electric appliances, consumer electronics, automotive electronics, aviation, aerospace and other fields. The third generation semiconductor material represented by SiC is an ideal material for preparing high-voltage, high-temperature, high-power and radiation-resistant power electronic devices by virtue of excellent material characteristics.
The existing trench SiC MOSFET has large reverse leakage, so that the power consumption of the whole device is high in the closed state, the device heats seriously, the reliability is reduced, and the performance of the grid electrode is degraded and is disabled under serious conditions. In addition, the existing silicon carbide MOSFET has poor recovery characteristics due to the fact that no shielding grid SG is inserted, and the reverse recovery peak current Irm, the reverse recovery time Trr and the reverse recovery charge Qrr are all large, so that the switching speed and the switching loss of the SiC MOSFET are seriously affected. In addition, the existing MOSFETs have no embedded SBD, so that transient current in a loop passes through a body diode, and the performance of the whole MOSFET is seriously degraded.
Disclosure of Invention
The present invention aims to overcome the above-mentioned shortcomings of the prior art and provide a silicon carbide SGT-MOSFET integrated with SBD and a method for manufacturing the same.
To achieve the above object, the present invention provides a silicon carbide SGT-MOSFET of an integrated SBD, comprising:
a silicon carbide substrate;
an N-type drift region on one surface of the silicon carbide substrate;
a first trench and a second trench disposed within the N-type drift region;
the first groove and the second groove are separated by a partition wall; the partition wall is obtained by ion implantation of an N-type drift region which is not etched;
the first P+ type doped region is arranged at the bottom of the first groove;
the second P+ type doped region is arranged at the bottom of the second groove;
the P well region is arranged in the partition wall;
the N+ type doped region is positioned above the P well region;
the first ohmic contact region is positioned above the N+ type doped region;
the first oxide layer at the bottom and the side surface of the second groove are provided with a mounting hole, and a Schottky contact area formed by SBD is arranged in the mounting hole;
a third oxide layer arranged above the Schottky contact region, and a shielding grid arranged on the third oxide layer;
the Schottky contact area is tightly attached to the shielding grid, and the Schottky contact area and the shielding grid are jointly used as a source electrode of the power device to be connected through the layout;
a fourth oxide layer arranged above the shielding grid, and a control grid arranged above the fourth oxide layer;
the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through a second oxide layer;
preventing electric leakage above the control gate and above the first trench by a deposited passivation layer;
a second ohmic contact region is disposed on the other surface of the silicon carbide substrate.
Further, the doping concentration of the first P+ type doping region is consistent with that of the second P+ type doping region and is higher than that of the N-type drift region and the P well region.
Further, the etching width or depth of the first groove in the N-type drift region is smaller than that of the second groove in the N-type drift region.
Further, a first metal layer is deposited at the bottom of the second trench, the first metal layer is not in contact with the partition wall and is in contact with the second P+ type doped region part at the bottom, and a metal-semiconductor contact is formed by high-temperature annealing to form a Schottky contact region.
Further, the first p+ type doped region, the second p+ type doped region and the P well region have the same conductivity type, and the P well region and the n+ type doped region have different conductivity types.
Further, the width of the second groove is larger than that of the schottky contact area or the shielding gate.
Further, the thickness of the schottky contact area is smaller than that of the shielding grid, and the thickness of the shielding grid is smaller than that of the control grid.
Further, a second metal layer is deposited over the n+ doped region to form a first ohmic contact region.
The invention also provides a preparation method of the SBD integrated silicon carbide SGT-MOSFET, which comprises the following steps:
providing a silicon carbide substrate;
growing an N-type drift region on one surface of a silicon carbide substrate;
etching a first groove and a second groove in the N-type drift region, wherein the etching depth of the first groove in the N-type drift region is smaller than that of the second groove in the N-type drift region;
al ion implantation is carried out at the bottom of the first groove to form two adjacent first P+ type doped regions separated by an N-type drift region;
al ion implantation is carried out at the bottom of the second groove to form two second P+ type doped regions with equal size;
performing Al ion implantation on the partition wall between the first groove and the second groove to form a P well region;
n ion implantation is carried out above the P well region, and an N+ type doped region is formed;
performing metal deposition and high-temperature annealing on the upper part of the N+ type doped region to form a first ohmic contact region;
depositing a first oxide layer and a second oxide layer on the bottom and the side surface of the second groove, and opening a hole on the first oxide layer on the bottom surface to deposit an SBD (styrene-butadiene-styrene) to form a Schottky contact area;
depositing a third oxide layer above the Schottky contact region, and opening a hole on the third oxide layer to deposit doped polysilicon to form a shielding gate;
depositing a fourth oxide layer above the shielding gate, and then depositing doped polysilicon above the fourth oxide layer to form a control gate;
the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through a second oxide layer;
thinning the silicon carbide substrate, and sputtering metal ions on the other surface of the silicon carbide substrate to prepare an electrode.
Further, the implantation depth of the Al ions of the second P+ type doped region at the bottom of the second groove is equal to the implantation depth of the Al ions of the first P+ type doped region at the bottom of the first groove.
Further, the materials of the first oxide layer, the second oxide layer, the third oxide layer and the fourth oxide layer are all silicon dioxide.
The invention has the following beneficial effects:
1. under the condition of the same breakdown voltage, the doping concentration of the drift region is improved by introducing the shielding grid, so that the on-resistance of the drift region is reduced, and the grid leakage capacitance and grid charge can be effectively reduced by the shielding grid, so that the switching frequency is improved;
2. in the invention, the switching time is reduced due to the reduction of the gate-drain capacitance and the gate charge, so that the energy consumed by each switching is lower;
3. the invention can effectively reduce the source electrode leakage Idss when the device is turned off, solves the problems that the power consumption of the whole device is increased in a blocking state due to overlarge source electrode leakage Idss when the device is turned off, and the reliability of the device is reduced and the risk of failure occurs due to overheating of the device along with continuous rising of heating value, improves the reliability of the whole device and prevents the device from failure due to local overheating;
4. according to the invention, the SBD is embedded at the bottom of the groove, when an inductor exists in a loop, instantaneous small current can further carry out follow current through the SBD, so that the problem of performance degradation of the whole MOSFET is caused by the fact that a body diode carried by the MOSFET works is prevented, the SBD is integrated in the MOSFET without externally connecting the SBD, the packaging cost of the whole chip is reduced, and in addition, the integrated SBD is improved in the follow current aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is an overall block diagram of a SBD integrated silicon carbide SGT-MOSFET of some embodiments of the present invention;
FIG. 2 is a cross-sectional view of a chip after trench etching for a silicon carbide SGT-MOSFET of an integrated SBD according to some embodiments of the present invention;
FIG. 3 is a cross-sectional view of a chip after ion implantation of a silicon carbide SGT-MOSFET of an integrated SBD according to some embodiments of the present invention;
fig. 4 is a cross-sectional view of an SBD integrated silicon carbide SGT-MOSFET deposited metal layer after forming a first ohmic contact region and a schottky contact region according to some embodiments of the present invention;
FIG. 5 is a cross-sectional view of an SBD integrated silicon carbide SGT-MOSFET of some embodiments of the present invention after forming a shield gate and a control gate;
fig. 6 is a cross-sectional view of an SBD integrated silicon carbide SGT-MOSFET of some embodiments of the present invention after chemical mechanical polishing, backside thinning and depositing a metal layer to form a second ohmic contact region.
Reference numerals in the specific embodiments are as follows:
the silicon carbide substrate 1, an N-type drift region 2, a second P+ type doped region 3, a first P+ type doped region 6, a P well region 4, an N+ type doped region 5, a Schottky contact region 7, a shielding gate 8, a control gate 9, silicon dioxide 10, a first ohmic contact region 11 and a second ohmic contact region 12.
Detailed Description
For a better description of the objects, technical solutions and advantages of the present invention, the present invention will be further described with reference to the following specific examples.
Referring to FIG. 1, in one embodiment of the present invention, the present invention provides an SBD integrated silicon carbide SGT-MOSFET comprising:
a silicon carbide substrate 1;
an N-type drift region 2 located on one surface of the silicon carbide substrate 1;
a first trench and a second trench disposed in the N-type drift region 2;
the first groove and the second groove are separated by a certain thickness of partition wall, and the partition wall is obtained by ion implantation of an unetched N-type drift region 2;
the first p+ type doped region 6 is arranged at the bottom of the first groove, the second p+ type doped region 3 is arranged at the bottom of the second groove, the P well region 4 is arranged in the partition wall, al ions are injected at the bottom of the groove to form the second p+ type doped region 3 and the first p+ type doped region 6, under the closed state, the depletion region formed between the two p+ type doped regions can well prevent source leakage, further, when the P well region 4 is depleted towards the N-type drift region 2, the source leakage of the whole device can be reduced secondarily, the source leakage condition of the device under the off state can be greatly reduced together with the depletion region formed by the two p+ type doped regions, the power consumption of the whole device can be reduced, the heating region of the device is averaged to the whole surface from one point, and the risk of overheat failure of the device is avoided;
an N+ doped region 5 located above the P well region 4;
a first ohmic contact region 11 located above the n+ type doped region 5;
the bottom and the side of the second groove are provided with a first oxide layer and a second oxide layer, the first oxide layer at the bottom is provided with a mounting hole, the mounting hole is internally provided with a Schottky contact area 7 formed by SBD, the SBD is embedded in the bottom of the groove, when inductance exists in a loop, instantaneous small current can freewheel through the SBD, the body diode of the MOSFET is prevented from working, so that the performance degradation problem of the whole MOSFET is caused, the barrier of the SBD introduced in the bottom of the groove is lower, the starting voltage is reduced, under the condition of small current freewheel, the starting freewheel of only the Schottky contact area 7 area can be realized, and under the condition of large current inrush, the ohmic contact formed by the contact of the second P+ type doped area 3 and the metal layer deposited above the second groove can be conducted, so that the large current freewheel is realized, the starting of the MOSFET body diode is avoided, and the performance degradation of the whole MOSFET is caused;
the third oxide layer is arranged above the Schottky contact region, and the shielding grid 8 is arranged on the third oxide layer, so that the voltage resistance can be improved and the on-resistance can be reduced by introducing the shielding grid 8, and most importantly, the control grid and the drain are separated by introducing the shielding grid, so that the grid-drain capacitance, namely the Miller capacitance, can be greatly reduced, and the switching rate of the whole device is improved;
the shielding grid 8 is introduced to play a role of a field plate in the body, the N-type drift region 2 is assisted to be exhausted during forward blocking, higher breakdown voltage Vbr is achieved, the shielding grid isolates the control grid from the drain, the grid-drain capacitance Cgd, namely the Miller capacitance, is greatly reduced, and the switching rate of the MOSFET is effectively improved, so that the switching loss is reduced.
The schottky contact area 7 and the shielding grid 8 are tightly attached, and are jointly used as a source electrode of the power device through the layout and the first ohmic contact area 11;
a fourth oxide layer disposed over the shield gate 8, and a control gate 9 disposed over the fourth oxide layer;
the control grid 9 and the shielding grid 8 are arranged in parallel, the lower end of the control grid 9 and the shielding grid 8 are arranged at intervals through a fourth oxide layer, the side surface of the control grid 9 is arranged opposite to the P well region 4, and the side surface of the control grid 9 and the P well region 4 are arranged at intervals through a second oxide layer;
preventing leakage above the control gate 9 and above the first trench by a deposited passivation layer of silicon dioxide 10;
a second ohmic contact region 12 is provided on the other surface of the silicon carbide substrate 1.
The doping concentration of the first p+ type doped region 6 is identical to that of the second p+ type doped region 3 and higher than that of the N-type drift region 2 and the P-well region 4.
The etching width or depth of the first groove in the N-type drift region 2 is smaller than that of the second groove in the N-type drift region 2.
The bottom of the second trench is deposited with a first metal layer, the first metal layer is not contacted with the partition wall, and is partially contacted with the second P+ type doped region 3 at the bottom, and the metal-semiconductor contact is formed by high-temperature annealing to form the Schottky contact region 7.
The first p+ type doped region 6, the second p+ type doped region 3 and the P well region 4 have the same conductivity type, and the P well region 4 and the n+ type doped region 5 have different conductivity types.
The width of the second trench is larger than the width of the schottky contact region 7 or the shield gate 8.
The thickness of the schottky contact region 7 is smaller than the thickness of the shielding gate 8, and the thickness of the shielding gate 8 is smaller than the thickness of the control gate 9.
A second metal layer is deposited over the N + type doped region 5 to form a first ohmic contact region 11.
The second p+ doped region 3, the first p+ doped region 6 and the P well region 4 are implanted by the same ion, but the implantation energy and the depth used are different, and the p+ doped region 3 in the second trench and the p+ doped region 6 in the first trench can be implanted by using the same process conditions for saving the cost.
The n+ type doped region 5 and the P well region 4 are different in implanted ion type.
The bottom of the first p+ type doped region 6 is higher than the top of the second p+ type doped region 3.
The bottom of the P-well region 4 is lower than the top of the first p+ doped region 6, but higher than the bottom of the first p+ doped region 6, and the P-well region 4 and the first p+ doped region 6 are isolated by the N-type drift region 2 with a certain thickness.
The implantation depth of the first p+ type doped region 6 is smaller than the implantation depth of the P well region 4.
The implantation depth of the n+ doped region 5 is much smaller than that of the P-well region 4.
In one embodiment of the invention, the reverse breakdown voltage is effectively improved through the two P+ type doped regions, the reverse leakage is reduced, a metal layer is deposited above the second groove to form an embedded SBD, the embedded SBD can optimize the problem of low anti-surge capability of a body diode of a traditional MOSFET, the reverse freewheeling capability is also enhanced, a Shielding Gate (SGT) is deposited above the embedded SBD, under the condition of the same breakdown voltage, the doping concentration of the drift region is improved through introducing the shielding gate, so that the on resistance of the drift region is reduced, and the shielding gate can also effectively reduce the gate-drain capacitance and the gate charge, so that the switching frequency is improved.
In one embodiment of the present invention, the present invention further provides a method for preparing an SBD integrated silicon carbide SGT-MOSFET, comprising:
providing a silicon carbide substrate 1;
growing an N-type drift region 2 on one surface of a silicon carbide substrate 1;
etching a first groove and a second groove in the N-type drift region 2, wherein the etching depth of the first groove is smaller than that of the second groove;
al ion implantation is carried out at the bottom of the first groove to form adjacent first P+ type doped regions 6 separated by the N-type drift region 2;
al ion implantation is carried out at the bottom of the second groove to form two second P+ type doped regions 3 with equal size;
al ion implantation is carried out on the partition wall between the first groove and the second groove, so that a P well region 4 is formed;
n ion implantation is carried out above the P well region 4 to form an N+ type doped region 5;
performing metal deposition and high-temperature annealing on the upper part of the N+ type doped region 5 to form a first ohmic contact region 11;
depositing a first oxide layer and a second oxide layer on the bottom and the side surface of the second groove, and opening a hole on the first oxide layer on the bottom surface to deposit SBD to form a Schottky contact region 7, wherein the Schottky contact region 7 is not contacted with the partition wall and is partially contacted with two equal-sized second P+ type doped regions 3;
depositing a third oxide layer above the Schottky contact region, and opening a hole on the third oxide layer to deposit doped polysilicon to form a shielding gate 8;
depositing a fourth oxide layer over the shielding gate, then depositing doped polysilicon over the fourth oxide layer to form a control gate 9, and then depositing a passivation layer of silicon dioxide 10 over the control gate 9;
the control grid 9 and the shielding grid 8 are arranged in parallel, the lower end of the control grid 9 and the shielding grid 8 are arranged at intervals through a fourth oxide layer, the side surface of the control grid 9 is arranged opposite to the P well region 4, and the side surface of the control grid 9 and the P well region 4 are arranged at intervals through a second oxide layer;
thinning the silicon carbide substrate 1, and sputtering metal ions on the other surface of the silicon carbide substrate to prepare an electrode.
The Al ion implantation depth of the second P+ type doped region 3 at the bottom of the second groove is equal to the Al ion implantation depth of the first P+ type doped region 6 at the bottom of the first groove.
The first oxide layer, the second oxide layer, the third oxide layer and the fourth oxide layer are all made of silicon dioxide.
In one embodiment of the invention, the invention provides an SBD integrated silicon carbide SGT MOSFET comprising:
a silicon carbide substrate 1;
an N-type drift region 2 is epitaxially grown on one surface of a silicon carbide substrate 1;
etching a first groove and a second groove in the N-type drift region 2, as shown in figure 2;
al ions are respectively injected into the bottoms of the first groove and the second groove to form a second P+ type doped region 3 and a first P+ type doped region 6, the second P+ type doped region is used as a first depletion region when the first P+ type doped region is turned off, source leakage is prevented, blocking withstand voltage is born, al ion injection is carried out above the N-type drift region 2 to form a P well region 4, and the P well region is used as a second depletion region, so that field intensity distribution of the whole device is reduced;
n ion implantation is performed above the P well region 4 to form an N+ type doped region 5, as shown in FIG. 3;
performing metal deposition on the upper surface of the N+ type doped region 5 to form a first ohmic contact region 11;
a metal layer is deposited at the bottom of the second groove to form a Schottky contact region 7, and the Schottky contact region 7 is positioned between the two second P+ type doped regions 3, so that the first depletion regions at the two sides are connected into a whole and bear reverse withstand voltage together in the off state, and the rest positions of the bottom of the groove are filled with silicon dioxide 10 as shown in fig. 4;
a Shielding Gate (SGT) 8 is formed by depositing doped polysilicon on the Schottky contact region 7, and the Shielding Gate (SGT) 8 formed in the groove can be used as a field plate in the longitudinal direction to adjust the distribution of an electric field in the SGT-MOSFET so as to improve the rated withstand voltage of the whole chip;
the Schottky contact area 7, the shielding grid 8 and the first ohmic contact area 11 are interconnected to be used as the source electrode of the SGT MOSFET together, the Schottky contact area 7 of the integrated SBD can realize follow current under the condition of small current, the conduction of the MOSFET body diode is prevented, and the problem of serious degradation of the performance of the whole MOSFET is solved;
growing a layer of oxide silicon dioxide 10 above the shielding gate 8, reserving the shielding gate with the preset thickness and SGT to prevent the short circuit between the shielding gate and the source, etching the oxide layer of the groove to a proper depth at a proper position, depositing doped polysilicon to form a control gate 9, finally depositing the silicon dioxide 10 to fill up the groove, and then removing redundant silicon dioxide on the metal surface by using a CMP technology, as shown in figure 5;
the substrate is thinned to 150 μm and a metal is deposited on the other surface of the silicon carbide substrate 1 and then laser annealed to form a second ohmic contact region 12, as shown in fig. 6.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. A SBD integrated silicon carbide SGT-MOSFET comprising:
a silicon carbide substrate;
an N-type drift region on one surface of the silicon carbide substrate;
a first trench and a second trench disposed within the N-type drift region;
the first groove and the second groove are separated by a partition wall; the partition wall is obtained by ion implantation of an N-type drift region which is not etched;
the first P+ type doped region is arranged at the bottom of the first groove;
the second P+ type doped region is arranged at the bottom of the second groove;
the P well region is arranged in the partition wall;
the N+ type doped region is positioned above the P well region;
the first ohmic contact region is positioned above the N+ type doped region;
the first oxide layer at the bottom and the side surface of the second groove are provided with a mounting hole, and a Schottky contact area formed by SBD is arranged in the mounting hole;
a third oxide layer arranged above the Schottky contact region, and a shielding grid arranged on the third oxide layer;
the Schottky contact area is tightly attached to the shielding grid, and the Schottky contact area and the shielding grid are jointly used as a source electrode of the power device to be connected through the layout;
a fourth oxide layer arranged above the shielding grid, and a control grid arranged above the fourth oxide layer;
the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through the second oxide layer;
preventing electric leakage above the control gate and above the first trench by a deposited passivation layer;
a second ohmic contact region is arranged on the other surface of the silicon carbide substrate;
a first metal layer is deposited at the bottom of the second groove, the first metal layer is not contacted with the partition wall and is contacted with a second P+ type doped region part at the bottom, a metal-semiconductor contact is formed by high-temperature annealing to form a Schottky contact region, the first metal layer is contacted with the second P+ type doped region part to form ohmic contact, and the Schottky contact region is positioned between the two second P+ type doped regions;
the bottom of the P well region is lower than the top of the first P+ type doped region, but higher than the bottom of the first P+ type doped region structure;
and the implantation depth of the first P+ type doped region is smaller than that of the P well region.
2. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the first p+ type doped region has a doping concentration that is consistent with the doping concentration of the second p+ type doped region and higher than the doping concentrations of the N-type drift region and the P-well region.
3. The SBD integrated silicon carbide SGT-MOSFET of claim 1 wherein the first trench has an etch width or depth within the N-type drift region that is less than the etch width or depth of the second trench within the N-type drift region.
4. The SBD integrated silicon carbide SGT-MOSFET of claim 1 wherein the first p+ doped region, and the P-well region have the same conductivity type, and the P-well region and the n+ doped region have different conductivity types.
5. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the second trench has a width greater than a width of the schottky contact region or the shield gate.
6. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the schottky contact region has a thickness less than a thickness of a shield gate, the shield gate having a thickness less than a thickness of a control gate.
7. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein a second metal layer is deposited over the n+ doped region to form a first ohmic contact region.
8. A method of making a SBD integrated silicon carbide SGT-MOSFET according to any one of claims 1 to 7, comprising:
providing a silicon carbide substrate;
growing an N-type drift region on one surface of a silicon carbide substrate;
etching a first groove and a second groove in the N-type drift region, wherein the etching depth of the first groove in the N-type drift region is smaller than that of the second groove in the N-type drift region;
al ion implantation is carried out at the bottom of the first groove to form two adjacent first P+ type doped regions separated by an N-type drift region;
al ion implantation is carried out at the bottom of the second groove to form two second P+ type doped regions with equal size;
performing Al ion implantation on the partition wall between the first groove and the second groove to form a P well region;
n ion implantation is carried out above the P well region, and an N+ type doped region is formed;
performing metal deposition and high-temperature annealing on the upper part of the N+ type doped region to form a first ohmic contact region;
depositing a first oxide layer and a second oxide layer on the bottom and the side surface of the second groove, and opening a hole on the first oxide layer on the bottom surface to deposit an SBD (styrene-butadiene-styrene) to form a Schottky contact area;
depositing a third oxide layer above the Schottky contact region, and opening a hole on the third oxide layer to deposit doped polysilicon to form a shielding gate;
depositing a fourth oxide layer above the shielding gate, and then depositing doped polysilicon above the fourth oxide layer to form a control gate;
the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through a second oxide layer;
thinning the silicon carbide substrate, and sputtering metal ions on the other surface of the silicon carbide substrate to prepare an electrode.
9. The method of claim 8, wherein the second p+ type doped region Al ion implantation depth at the bottom of the second trench is equal to the first p+ type doped region Al ion implantation depth at the bottom of the first trench.
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