CN116721925B - SBD integrated silicon carbide SGT-MOSFET and preparation method thereof - Google Patents

SBD integrated silicon carbide SGT-MOSFET and preparation method thereof Download PDF

Info

Publication number
CN116721925B
CN116721925B CN202310986654.5A CN202310986654A CN116721925B CN 116721925 B CN116721925 B CN 116721925B CN 202310986654 A CN202310986654 A CN 202310986654A CN 116721925 B CN116721925 B CN 116721925B
Authority
CN
China
Prior art keywords
region
silicon carbide
type doped
oxide layer
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310986654.5A
Other languages
Chinese (zh)
Other versions
CN116721925A (en
Inventor
王晓
任真伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Pingchuang Semiconductor Research Institute Co ltd
Shenzhen Pingchuang Semiconductor Co ltd
Original Assignee
Chongqing Pingchuang Semiconductor Research Institute Co ltd
Shenzhen Pingchuang Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chongqing Pingchuang Semiconductor Research Institute Co ltd, Shenzhen Pingchuang Semiconductor Co ltd filed Critical Chongqing Pingchuang Semiconductor Research Institute Co ltd
Priority to CN202310986654.5A priority Critical patent/CN116721925B/en
Publication of CN116721925A publication Critical patent/CN116721925A/en
Application granted granted Critical
Publication of CN116721925B publication Critical patent/CN116721925B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141VDMOS having built-in components
    • H10D84/146VDMOS having built-in components the built-in components being Schottky barrier diodes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide SGT-MOSFET of an integrated SBD and a preparation method thereof, wherein the silicon carbide SGT-MOSFET of the integrated SBD comprises: the semiconductor device comprises a silicon carbide substrate, an N-type drift region, a first groove, a second groove, a first P+ type doped region, a second P+ type doped region, a P well region, an N+ type doped region, a first ohmic contact region, a Schottky contact region, a shielding gate, a control gate, a second ohmic contact region and the like, wherein the first groove and the second groove are arranged in the N-type drift region, and the second ohmic contact region is arranged on the other surface of the silicon carbide substrate. According to the invention, the reverse breakdown voltage is effectively improved through the two P+ type doped regions, the reverse electric leakage is reduced, the metal layer is deposited above the second groove to form the embedded SBD, the embedded SBD can optimize the problem of low surge resistance of the body diode of the traditional MOSFET, and the reverse follow current capability can be enhanced.

Description

集成SBD的碳化硅SGT-MOSFET及其制备方法Silicon carbide SGT-MOSFET integrated with SBD and preparation method thereof

技术领域Technical field

本发明属于功率半导体技术领域,具体涉及一种集成SBD 的碳化硅 SGT-MOSFET及其制备方法。The invention belongs to the technical field of power semiconductors, and specifically relates to an SBD-integrated silicon carbide SGT-MOSFET and a preparation method thereof.

背景技术Background technique

功率器件拥有高开关速度,高耐压,良好的热稳定性等一系列的优点,当前已在各类复杂工作环境下得到广泛的应用,如工业控制、电源、便携式电器、消费电子、汽车电子以及航空、航天等领域。以SiC为代表的第三代半导体材料,以其优良的材料特性成为制备高压、高温、大功率、抗辐射电力电子器件的理想材料。Power devices have a series of advantages such as high switching speed, high withstand voltage, and good thermal stability. They have been widely used in various complex working environments, such as industrial control, power supplies, portable appliances, consumer electronics, and automotive electronics. As well as aviation, aerospace and other fields. The third generation of semiconductor materials represented by SiC has become an ideal material for the preparation of high-voltage, high-temperature, high-power, and radiation-resistant power electronic devices due to its excellent material properties.

现有的沟槽SiC MOSFET的反向漏电偏大,导致整个器件在关闭状态下,功耗偏高,器件发热严重,可靠性降低,严重情况下会导致栅极性能退化并使其失效。并且现有碳化硅MOSFET由于没有屏蔽栅SG的插入,恢复特性差,反向恢复峰值电流Irm、反向恢复时间Trr以及反向恢复电荷Qrr均较大,严重影响SiC MOSFET的开关速度以及开关损耗。此外,现有MOSFET由于没有SBD的嵌入,导致回路中的瞬时电流通过体二极管,使整个MOSFET的性能严重衰退。The reverse leakage of existing trench SiC MOSFETs is relatively large, resulting in high power consumption when the entire device is turned off, severe device heating, reduced reliability, and in severe cases, gate performance degradation and failure. In addition, the existing silicon carbide MOSFET has poor recovery characteristics because there is no insertion of the shield gate SG. The reverse recovery peak current Irm, reverse recovery time Trr and reverse recovery charge Qrr are all large, seriously affecting the switching speed and switching loss of the SiC MOSFET. . In addition, the existing MOSFET does not have an embedded SBD, which causes the instantaneous current in the loop to pass through the body diode, seriously degrading the performance of the entire MOSFET.

发明内容Contents of the invention

本发明的目的在于克服上述现有技术不足之处而提供一种集成SBD 的碳化硅SGT-MOSFET 及其制备方法。The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide an SBD-integrated silicon carbide SGT-MOSFET and a preparation method thereof.

为实现上述目的,本发明提供了一种集成SBD 的碳化硅 SGT-MOSFET,包括:To achieve the above objectives, the present invention provides an SBD-integrated silicon carbide SGT-MOSFET, including:

碳化硅衬底;silicon carbide substrate;

N-型漂移区,位于所述碳化硅衬底的一个表面上;An N-type drift region is located on one surface of the silicon carbide substrate;

设置于所述N-型漂移区内的第一沟槽和第二沟槽;A first trench and a second trench disposed in the N-type drift region;

所述第一沟槽和第二沟槽通过间隔壁分隔;所述间隔壁由未被刻蚀的N-型漂移区通过离子注入获得;The first trench and the second trench are separated by a partition wall; the partition wall is obtained by ion implantation from an unetched N-type drift region;

第一P+型掺杂区,设置于所述第一沟槽底部;A first P+ type doping region is provided at the bottom of the first trench;

第二P+型掺杂区,设置于所述第二沟槽底部;A second P+ type doped region is provided at the bottom of the second trench;

P阱区,设置于所述间隔壁内;A P-well region is provided in the partition wall;

N+型掺杂区,位于所述P阱区上方;An N+-type doped region is located above the P-well region;

第一欧姆接触区,位于所述N+型掺杂区上方;A first ohmic contact region is located above the N+ type doped region;

所述第二沟槽的底部和侧面设置的第一氧化层和第二氧化层,底部的第一氧化层上设有安装孔,所述安装孔中设置SBD形成的肖特基接触区;A first oxide layer and a second oxide layer are provided at the bottom and sides of the second trench, and a mounting hole is provided on the first oxide layer at the bottom, and a Schottky contact area formed by SBD is provided in the mounting hole;

所述肖特基接触区上方设置的第三氧化层,并在该第三氧化层上设置屏蔽栅;A third oxide layer is provided above the Schottky contact area, and a shielding gate is provided on the third oxide layer;

其中所述肖特基接触区和屏蔽栅之间紧密贴附,通过版图与第一欧姆接触区共同作为功率器件的源极连出;The Schottky contact area and the shielding grid are closely attached, and are connected together with the first ohmic contact area through the layout as the source of the power device;

所述屏蔽栅上方设置的第四氧化层,在该第四氧化层上方设置的控制栅;a fourth oxide layer provided above the shielding gate, and a control gate provided above the fourth oxide layer;

其中,控制栅和屏蔽栅平行布置,控制栅的下端与屏蔽栅之间通过第四氧化层间隔布置,控制栅的侧面与P阱区相对布置,控制栅的侧面与P阱区之间通过第二氧化层间隔布置;Wherein, the control gate and the shielding gate are arranged in parallel, the lower end of the control gate and the shielding gate are spaced by a fourth oxide layer, the side surfaces of the control gate are arranged opposite to the P-well region, and the side surfaces of the control gate and the P-well region are separated by a third oxide layer. Dioxide layer spacing arrangement;

在所述控制栅上方与第一沟槽上方通过沉积的钝化层防止漏电;Prevent leakage by depositing a passivation layer above the control gate and above the first trench;

所述碳化硅衬底的另一个表面上设置第二欧姆接触区。A second ohmic contact area is provided on another surface of the silicon carbide substrate.

进一步地,所述第一P+型掺杂区与所述第二P+型掺杂区的掺杂浓度一致,并高于所述N-型漂移区和所述P阱区的掺杂浓度。Further, the doping concentration of the first P+ type doping region and the second P+ type doping region are consistent and higher than the doping concentration of the N- type drift region and the P well region.

进一步地,所述第一沟槽在所述N-型漂移区内的刻蚀宽度或深度小于第二沟槽在所述N-型漂移区内的刻蚀宽度或深度。Further, the etching width or depth of the first trench in the N-type drift region is smaller than the etching width or depth of the second trench in the N-type drift region.

进一步地,所述第二沟槽底部沉积有第一金属层,第一金属层和间隔壁不接触,且与底部的第二P+型掺杂区部分接触,高温退火形成金半接触,以形成肖特基接触区。Further, a first metal layer is deposited at the bottom of the second trench. The first metal layer is not in contact with the partition wall and is partially in contact with the second P+ type doped region at the bottom. It is annealed at high temperature to form a gold half contact to form Schottky contact zone.

进一步地,所述第一P+型掺杂区、所述第二P+型掺杂区和所述P阱区具有相同的导电类型,所述P阱区和所述N+型掺杂区具有不同的导电类型。Further, the first P+ type doped region, the second P+ type doped region and the P well region have the same conductivity type, and the P well region and the N+ type doped region have different conductivity types. Conductivity type.

进一步地,所述第二沟槽的宽度大于肖特基接触区或屏蔽栅的宽度。Further, the width of the second trench is greater than the width of the Schottky contact area or the shield gate.

进一步地,所述肖特基接触区的厚度小于屏蔽栅的厚度,所述屏蔽栅的厚度小于控制栅的厚度。Further, the thickness of the Schottky contact area is smaller than the thickness of the shielding grid, and the thickness of the shielding grid is smaller than the thickness of the control grid.

进一步地,在所述N+型掺杂区上方沉积有第二金属层,以形成第一欧姆接触区。Further, a second metal layer is deposited above the N+ type doped region to form a first ohmic contact region.

本发明还提供了一种集成SBD 的碳化硅 SGT-MOSFET的制备方法,包括:The invention also provides a method for preparing an SBD-integrated silicon carbide SGT-MOSFET, including:

提供碳化硅衬底;Provide silicon carbide substrate;

于碳化硅衬底的一个表面上生长N-型漂移区;growing an N-type drift region on one surface of the silicon carbide substrate;

于N-型漂移区内刻蚀第一沟槽和第二沟槽,所述第一沟槽在N-型漂移区内的刻蚀深度小于第二沟槽在N-型漂移区内的刻蚀深度;Etching a first trench and a second trench in the N-type drift region, the etching depth of the first trench in the N-type drift region being smaller than the etching depth of the second trench in the N-type drift region corrosion depth;

在第一沟槽底部进行Al离子注入,形成两个相邻的通过N-型漂移区分隔的第一P+型掺杂区;Perform Al ion implantation at the bottom of the first trench to form two adjacent first P+ type doped regions separated by an N-type drift region;

在第二沟槽底部进行Al离子注入,形成两个等大的第二P+型掺杂区;Al ion implantation is performed at the bottom of the second trench to form two second P+ type doped regions of equal size;

于所述第一沟槽和所述第二沟槽中间的间隔壁进行Al离子注入,形成P阱区;Perform Al ion implantation into the partition wall between the first trench and the second trench to form a P-well region;

在P阱区上方进行N离子注入,形成N+型掺杂区;Perform N ion implantation above the P well region to form an N+ type doped region;

于N+型掺杂区上方进行金属沉积,高温退火,形成第一欧姆接触区;Metal deposition is performed above the N+ type doped area and annealed at high temperature to form the first ohmic contact area;

于第二沟槽的底部和侧面沉积第一氧化层和第二氧化层,在底面的第一氧化层上开孔沉积SBD形成肖特基接触区;Deposit a first oxide layer and a second oxide layer on the bottom and sides of the second trench, and open holes on the first oxide layer on the bottom surface to deposit SBD to form a Schottky contact area;

在肖特基接触区上方沉积第三氧化层,并在第三氧化层上开孔沉积掺杂多晶硅,形成屏蔽栅;Deposit a third oxide layer above the Schottky contact area, and open holes on the third oxide layer to deposit doped polysilicon to form a shield gate;

在屏蔽栅上方沉积第四氧化层,然后在该第四氧化层上方沉积掺杂多晶硅,形成控制栅;depositing a fourth oxide layer above the shield gate, and then depositing doped polysilicon above the fourth oxide layer to form a control gate;

其中,控制栅和屏蔽栅平行布置,控制栅的下端与屏蔽栅之间通过第四氧化层间隔布置,控制栅的侧面与P阱区相对布置,控制栅的侧面与P阱区之间通过第二氧化层间隔布置;Wherein, the control gate and the shielding gate are arranged in parallel, the lower end of the control gate and the shielding gate are spaced by a fourth oxide layer, the side surfaces of the control gate are arranged opposite to the P-well region, and the side surfaces of the control gate and the P-well region are separated by a third oxide layer. Dioxide layer spacing arrangement;

减薄碳化硅衬底,在碳化硅衬底的另一个表面上金属离子溅射制成电极,即得。Thin the silicon carbide substrate and sputter metal ions on the other surface of the silicon carbide substrate to form an electrode.

进一步地,所述第二沟槽底部的第二P+型掺杂区Al离子的注入深度等于第一沟槽底部的第一P+型掺杂区Al离子注入深度。Further, the implantation depth of Al ions in the second P+ type doped region at the bottom of the second trench is equal to the implantation depth of Al ions in the first P+ type doped region at the bottom of the first trench.

进一步地,所述第一氧化层、所述第二氧化层、所述第三氧化层和所述第四氧化层的材料均为二氧化硅。Further, the material of the first oxide layer, the second oxide layer, the third oxide layer and the fourth oxide layer is silicon dioxide.

本发明具有如下的有益效果:The invention has the following beneficial effects:

1.在相同击穿电压情况下,本发明通过引入屏蔽栅提高漂移区的掺杂浓度,从而降低漂移区的导通电阻,而且屏蔽栅还可以有效降低栅漏电容和栅极电荷,从而提升开关频率;1. Under the same breakdown voltage, the present invention increases the doping concentration of the drift region by introducing a shield gate, thereby reducing the on-resistance of the drift region. Moreover, the shield gate can also effectively reduce the gate drain capacitance and gate charge, thereby improving On-off level;

2.在本发明中,由于栅漏电容和栅极电荷的降低,开关时间减少,因此每次开关所损耗的能量更低;2. In the present invention, due to the reduction of gate-drain capacitance and gate charge, the switching time is reduced, so the energy consumed by each switch is lower;

3.本发明可以有效地降低关断时的源极漏电Idss,解决了关断时的源极漏电Idss过大导致整个器件在阻断状态下的功耗增加,同时伴随着发热量持续上升,而器件过热会致使器件的可靠性降低,出现失效的风险的问题,提升了整个器件的可靠性,防止器件因局部过热而出现失效;3. The present invention can effectively reduce the source leakage Idss during turn-off, and solve the problem that excessive source leakage Idss during turn-off causes the power consumption of the entire device to increase in the blocking state, and at the same time, the heat generation continues to rise. Overheating of the device will reduce the reliability of the device and cause the risk of failure. This improves the reliability of the entire device and prevents the device from failing due to local overheating;

4.本发明将SBD 嵌入在沟槽底部,当回路中有电感时,瞬时的小电流还可通过SBD 进行续流,防止 MOSFET 自身带有的体二极管工作,从而引起整个 MOSFET 的性能衰退的问题,而且本发明集成了SBD在MOSFET内部则无需外接SBD,降低了整个芯片封装成本,此外集成的SBD在续流方面也得到提升。4. The present invention embeds the SBD at the bottom of the trench. When there is an inductor in the loop, the instantaneous small current can continue to flow through the SBD to prevent the body diode of the MOSFET itself from working, thereby causing the performance degradation of the entire MOSFET. , and the present invention integrates the SBD inside the MOSFET, eliminating the need for an external SBD, which reduces the entire chip packaging cost. In addition, the integrated SBD also improves the freewheeling aspect.

附图说明Description of drawings

为了更清楚地说明本发明实施例的技术方案,下面将对本发明实施例中所需要使用的附图作简单地介绍,显而易见地,下面所描述的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据附图获得其他的附图。In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on the drawings without exerting creative efforts.

图1为本发明一些实施例的集成SBD 的碳化硅 SGT-MOSFET的整体结构图;Figure 1 is an overall structural diagram of an SBD-integrated silicon carbide SGT-MOSFET according to some embodiments of the present invention;

图2为本发明一些实施例的集成SBD 的碳化硅 SGT-MOSFET刻蚀沟槽后芯片截面图;Figure 2 is a cross-sectional view of the chip of a silicon carbide SGT-MOSFET integrated with SBD after etching trenches according to some embodiments of the present invention;

图3为本发明一些实施例的集成SBD 的碳化硅 SGT-MOSFET离子注入后的芯片截面图;Figure 3 is a cross-sectional view of the chip after ion implantation of the SBD-integrated silicon carbide SGT-MOSFET according to some embodiments of the present invention;

图4为本发明一些实施例的集成SBD 的碳化硅 SGT-MOSFET沉积金属层形成第一欧姆接触区和肖特基接触区后的截面图;Figure 4 is a cross-sectional view of the SBD-integrated silicon carbide SGT-MOSFET after depositing a metal layer to form the first ohmic contact area and the Schottky contact area in some embodiments of the present invention;

图5为本发明一些实施例的集成SBD 的碳化硅 SGT-MOSFET形成屏蔽栅和控制栅后的截面图;Figure 5 is a cross-sectional view of an SBD-integrated silicon carbide SGT-MOSFET after forming a shield gate and a control gate according to some embodiments of the present invention;

图6为本发明一些实施例的集成SBD 的碳化硅 SGT-MOSFET在化学机械抛光后,背部减薄并沉积金属层形成第二欧姆接触区后的截面图。Figure 6 is a cross-sectional view of the SBD-integrated silicon carbide SGT-MOSFET according to some embodiments of the present invention after chemical mechanical polishing, thinning the back and depositing a metal layer to form a second ohmic contact area.

具体实施方式中的附图标号如下:The reference numbers in the specific implementation are as follows:

碳化硅衬底1、N-型漂移区2、第二P+型掺杂区3、第一P+型掺杂区6、P阱区4、N+型掺杂区5、肖特基接触区7、屏蔽栅8、控制栅9、二氧化硅10、第一欧姆接触区11和第二欧姆接触区12。Silicon carbide substrate 1, N-type drift region 2, second P+ type doped region 3, first P+ type doped region 6, P well region 4, N+ type doped region 5, Schottky contact region 7, Shield gate 8 , control gate 9 , silicon dioxide 10 , first ohmic contact area 11 and second ohmic contact area 12 .

具体实施方式Detailed ways

为更好的说明本发明的目的、技术方案和优点,下面将结合具体实施例对本发明作进一步说明。In order to better explain the purpose, technical solutions and advantages of the present invention, the present invention will be further described below with reference to specific embodiments.

请参阅图1,在本发明的一个实施例内,本发明提供了一种集成SBD 的碳化硅SGT-MOSFET,包括:Please refer to Figure 1. In one embodiment of the present invention, the present invention provides an SBD-integrated silicon carbide SGT-MOSFET, including:

碳化硅衬底1;Silicon carbide substrate 1;

N-型漂移区2,位于所述碳化硅衬底1的一个表面上;N-type drift region 2 is located on one surface of the silicon carbide substrate 1;

设置于所述N-型漂移区2内的第一沟槽和第二沟槽;The first trench and the second trench provided in the N-type drift region 2;

所述第一沟槽和第二沟槽通过一定厚度的间隔壁分隔,所述间隔壁由未被刻蚀的N-型漂移区2通过离子注入获得;The first trench and the second trench are separated by a partition wall of a certain thickness, and the partition wall is obtained by ion implantation from the unetched N-type drift region 2;

第一P+型掺杂区6,设置于所述第一沟槽底部,第二P+型掺杂区3,设置于所述第二沟槽底部,P阱区4,设置于所述间隔壁内,通过在沟槽底部注入 Al 离子形成第二P+型掺杂区3 和第一P+型掺杂区6,关闭状态下,两个 P+型掺杂区之间形成的耗尽区可以很好的防止源极漏电,进一步的,当 P阱区4向N-型漂移区2 区域耗尽时也可二次降低整个器件的源极漏电,两个 P+型掺杂区形成的耗尽区与P阱区形成的耗尽区可以一起极大地降低器件关断状态下的源极漏电情况,并可以降低整个器件的功耗,将器件的发热区域从一个点平均到整个面,避免了器件过热失效的风险;The first P+ type doped region 6 is provided at the bottom of the first trench, the second P+ type doped region 3 is provided at the bottom of the second trench, and the P well region 4 is provided in the partition wall. , the second P+ type doped region 3 and the first P+ type doped region 6 are formed by injecting Al ions at the bottom of the trench. In the off state, the depletion region formed between the two P+ type doped regions can be well Prevent source leakage. Furthermore, when the P well region 4 is depleted toward the N-type drift region 2, the source leakage of the entire device can also be reduced twice. The depletion region formed by the two P+ type doped regions and the P The depletion region formed in the well region can greatly reduce the source leakage of the device in the off state, and can also reduce the power consumption of the entire device. It averages the heating area of the device from one point to the entire surface, avoiding overheating failure of the device. risks of;

N+型掺杂区5,位于所述P阱区4上方;N+ type doped region 5 is located above the P well region 4;

第一欧姆接触区11,位于所述N+型掺杂区5上方;The first ohmic contact region 11 is located above the N+ type doped region 5;

所述第二沟槽的底部和侧面设置的第一氧化层和第二氧化层,底部的第一氧化层上设有安装孔,所述安装孔中设置SBD形成的肖特基接触区7,将SBD嵌入在沟槽底部,当回路中有电感时,瞬时的小电流可通过SBD进行续流,防止MOSFET自身带有的体二极管工作,从而引起整个MOSFET的性能衰退问题,而且,在沟槽底部引入的SBD势垒更低,启动电压降低,在小电流续流的情况下,可以做到仅肖特基接触区7区域开启续流,在大电流涌入的情况下,第二P+型掺杂区 3与第二沟槽上方沉积的金属层部分接触形成的欧姆接触可以导通,从而实现大电流续流,避免MOSFET体二极管开启,使整个MOSFET的性能衰退;A first oxide layer and a second oxide layer are provided at the bottom and sides of the second trench. The first oxide layer at the bottom is provided with a mounting hole, and a Schottky contact area 7 formed by SBD is provided in the mounting hole. Embed the SBD at the bottom of the trench. When there is an inductor in the loop, the instantaneous small current can continue to flow through the SBD, preventing the body diode of the MOSFET itself from working, thus causing the performance degradation of the entire MOSFET. Moreover, in the trench The SBD barrier introduced at the bottom is lower and the starting voltage is reduced. In the case of small current freewheeling, only the Schottky contact area 7 can open freewheeling. In the case of large current inrush, the second P+ type The ohmic contact formed by the partial contact between the doped region 3 and the metal layer deposited above the second trench can be turned on, thereby realizing a large current freewheeling and preventing the MOSFET body diode from turning on and causing the performance of the entire MOSFET to decline;

所述肖特基接触区上方设置的第三氧化层,并在该第三氧化层上设置屏蔽栅8,屏蔽栅8的引入,可以提高耐压并降低导通电阻,最重要的是屏蔽栅的引入分离了控制栅和漏极,可以极大的降低栅漏电容,即米勒电容,从而提高整个器件的开关速率;A third oxide layer is provided above the Schottky contact area, and a shield gate 8 is provided on the third oxide layer. The introduction of the shield gate 8 can improve the withstand voltage and reduce the on-resistance. The most important thing is the shield gate. The introduction of the separation of the control gate and drain can greatly reduce the gate-to-drain capacitance, that is, the Miller capacitance, thereby increasing the switching rate of the entire device;

通过引入屏蔽栅8在体内起到场板作用,正向阻断时辅助N-型漂移区2耗尽,达到更高的击穿电压Vbr,而且屏蔽栅隔离了控制栅和漏极,极大的降低了栅漏电容Cgd,即米勒电容,有效的提高了MOSFET的开关速率,从而降低了开关损耗。By introducing the shielding gate 8 to act as a field plate in the body, it assists the depletion of the N-type drift region 2 during forward blocking, reaching a higher breakdown voltage Vbr, and the shielding gate isolates the control gate and the drain, which greatly improves the Reducing the gate-to-drain capacitance Cgd, that is, the Miller capacitance, effectively increases the switching rate of the MOSFET, thereby reducing switching losses.

其中所述肖特基接触区7和屏蔽栅8之间紧密贴附,通过版图与第一欧姆接触区11共同作为功率器件的源极连出;The Schottky contact area 7 and the shielding gate 8 are closely adhered to each other, and are connected together with the first ohmic contact area 11 through the layout as the source of the power device;

所述屏蔽栅8上方设置的第四氧化层,在该第四氧化层上方设置的控制栅9;A fourth oxide layer provided above the shield gate 8, and a control gate 9 provided above the fourth oxide layer;

其中,控制栅9和屏蔽栅8平行布置,控制栅9的下端与屏蔽栅8之间通过第四氧化层间隔布置,控制栅9的侧面与P阱区4相对布置,控制栅9的侧面与P阱区4之间通过第二氧化层间隔布置;Among them, the control gate 9 and the shield gate 8 are arranged in parallel, and the lower end of the control gate 9 and the shield gate 8 are spaced by a fourth oxide layer. The side surfaces of the control gate 9 are arranged opposite to the P-well region 4, and the side surfaces of the control gate 9 are arranged opposite to the P-well region 4. The P-well regions 4 are spaced apart by a second oxide layer;

在所述控制栅9上方与第一沟槽上方通过沉积的钝化层二氧化硅10防止漏电;The passivation layer silicon dioxide 10 deposited above the control gate 9 and the first trench prevents leakage;

所述碳化硅衬底1的另一个表面上设置第二欧姆接触区12。A second ohmic contact area 12 is provided on the other surface of the silicon carbide substrate 1 .

所述第一P+型掺杂区6与所述第二P+型掺杂区3的掺杂浓度一致,并高于所述N-型漂移区2和所述P阱区4的掺杂浓度。The first P+ type doped region 6 has the same doping concentration as the second P+ type doped region 3 , and is higher than the doping concentration of the N- type drift region 2 and the P well region 4 .

所述第一沟槽在所述N-型漂移区2内的刻蚀宽度或深度小于第二沟槽在所述N-型漂移区2内的刻蚀宽度或深度。The etching width or depth of the first trench in the N-type drift region 2 is smaller than the etching width or depth of the second trench in the N-type drift region 2 .

所述第二沟槽底部沉积有第一金属层,第一金属层和间隔壁不接触,且与底部的第二P+型掺杂区3部分接触,高温退火形成金半接触,以形成肖特基接触区7。A first metal layer is deposited at the bottom of the second trench. The first metal layer does not contact the partition wall and is partially in contact with the second P+ type doped region 3 at the bottom. It is annealed at high temperature to form a gold half contact to form a Schott. Base contact area 7.

所述第一P+型掺杂区6、所述第二P+型掺杂区3和所述P阱区4具有相同的导电类型,所述P阱区4和所述N+型掺杂区5具有不同的导电类型。The first P+ type doped region 6, the second P+ type doped region 3 and the P well region 4 have the same conductivity type, and the P well region 4 and the N+ type doped region 5 have the same conductivity type. Different conductivity types.

所述第二沟槽的宽度大于肖特基接触区7或屏蔽栅8的宽度。The width of the second trench is greater than the width of the Schottky contact area 7 or the shield gate 8 .

所述肖特基接触区7的厚度小于屏蔽栅8的厚度,所述屏蔽栅8的厚度小于控制栅9的厚度。The thickness of the Schottky contact area 7 is smaller than the thickness of the shielding grid 8 , and the thickness of the shielding grid 8 is smaller than the thickness of the control grid 9 .

在所述N+型掺杂区5上方沉积有第二金属层,以形成第一欧姆接触区11。A second metal layer is deposited above the N+ type doped region 5 to form a first ohmic contact region 11 .

所述第二P+型掺杂区3、第一P+型掺杂区6和 P阱区4采用相同的离子进行注入,但使用的注入能量和深度不一样,第二沟槽内P+型掺杂区3和第一沟槽内P+型掺杂区6为节省成本可以使用同样的工艺条件进行注入。The second P+ type doping region 3, the first P+ type doping region 6 and the P well region 4 are implanted with the same ions, but the implantation energy and depth used are different. The P+ type doping in the second trench In order to save costs, the same process conditions can be used for implantation in region 3 and the P+ type doped region 6 in the first trench.

所述 N+型掺杂区5和 P阱区4的注入离子类型不一样。The N+ type doped region 5 and the P well region 4 have different implanted ion types.

所述第一P+型掺杂区6的底部高于第二P+型掺杂区3的顶部。The bottom of the first P+ type doped region 6 is higher than the top of the second P+ type doped region 3 .

所述P阱区4的底部低于第一P+型掺杂区6的顶部,但高于第一P+型掺杂区6结构的底部,且所述P阱区4和第一P+型掺杂区6通过一定厚度的N-型漂移区2隔离。The bottom of the P-well region 4 is lower than the top of the first P+-type doped region 6, but higher than the bottom of the first P+-type doped region 6, and the P-well region 4 and the first P+-type doped region Region 6 is isolated by a certain thickness of N-type drift region 2.

所述第一P+型掺杂区6的注入深度小于P阱区4的注入深度。The implantation depth of the first P+ type doped region 6 is smaller than the implantation depth of the P-well region 4 .

所述N+型掺杂区5的注入深度远远小于P阱区4的注入深度。The implantation depth of the N+ type doped region 5 is much smaller than the implantation depth of the P-well region 4 .

在本发明的一个实施例内,通过两个P+型掺杂区有效提升反向击穿电压,降低反向漏电,所述第二沟槽上方沉积有金属层,形成内嵌SBD,内嵌SBD可以优化传统MOSFET的体二极管抗浪涌能力低的问题,而且反向续流能力也得到加强,而且内嵌SBD上方沉积有屏蔽栅(SGT),在相同击穿电压情况下,通过引入屏蔽栅提高漂移区的掺杂浓度,从而降低漂移区的导通电阻,而且屏蔽栅还可以有效降低栅漏电容和栅极电荷,从而提升开关频率,本发明通过在SGT下方引入SBD,不仅提升了开关频率,增强耐压等级,同时在反向续流和抗浪涌能力上得到了提升。In one embodiment of the present invention, the reverse breakdown voltage is effectively increased and the reverse leakage is reduced through two P+ type doped regions. A metal layer is deposited above the second trench to form an embedded SBD. The embedded SBD is The problem of low surge resistance of the body diode of the traditional MOSFET can be optimized, and the reverse freewheeling capability is also enhanced, and a shield gate (SGT) is deposited above the embedded SBD. Under the same breakdown voltage, by introducing the shield gate The doping concentration of the drift region is increased, thereby reducing the on-resistance of the drift region. Moreover, the shielded gate can also effectively reduce the gate-drain capacitance and gate charge, thereby increasing the switching frequency. By introducing SBD under the SGT, the present invention not only improves the switching frequency frequency, enhanced voltage resistance level, and improved reverse freewheeling and surge resistance capabilities.

在本发明的一个实施例内,本发明还提供了一种集成SBD 的碳化硅 SGT-MOSFET的制备方法,包括:In one embodiment of the present invention, the present invention also provides a method for preparing an SBD-integrated silicon carbide SGT-MOSFET, including:

提供碳化硅衬底1;Provide silicon carbide substrate 1;

于碳化硅衬底1的一个表面上生长N-型漂移区2;Grow an N-type drift region 2 on one surface of the silicon carbide substrate 1;

于N-型漂移区2内刻蚀第一沟槽和第二沟槽,所述第一沟槽的刻蚀深度小于第二沟槽的刻蚀深度;Etching a first trench and a second trench in the N-type drift region 2, the etching depth of the first trench being smaller than the etching depth of the second trench;

在第一沟槽底部进行Al离子注入,形成相邻的通过N-型漂移区2分隔的第一P+型掺杂区6;Perform Al ion implantation at the bottom of the first trench to form adjacent first P+ type doped regions 6 separated by N-type drift regions 2;

在第二沟槽底部进行Al离子注入,形成两个等大的第二P+型掺杂区3;Al ion implantation is performed at the bottom of the second trench to form two second P+ type doped regions 3 of equal size;

于所述第一沟槽和所述第二沟槽中间的间隔壁进行Al离子注入,形成P阱区4;Perform Al ion implantation into the partition wall between the first trench and the second trench to form a P-well region 4;

在P阱区4上方进行N离子注入,形成N+型掺杂区5;Perform N ion implantation above the P well region 4 to form an N+ type doped region 5;

于N+型掺杂区5上方进行金属沉积,高温退火,形成第一欧姆接触区11;Metal deposition is performed above the N+ type doped region 5 and annealed at high temperature to form the first ohmic contact region 11;

于第二沟槽的底部和侧面沉积第一氧化层和第二氧化层,在底面的第一氧化层上开孔沉积SBD形成肖特基接触区7,肖特基接触区7和间隔壁不接触,和两个等大的第二P+型掺杂区3部分接触;The first oxide layer and the second oxide layer are deposited on the bottom and sides of the second trench, and SBD is deposited on the first oxide layer on the bottom surface to form a Schottky contact area 7. The Schottky contact area 7 and the partition wall are not Contact, and partial contact with two second P+ type doped regions 3 of equal size;

在肖特基接触区上方沉积第三氧化层,并在第三氧化层上开孔沉积掺杂多晶硅,形成屏蔽栅8;Deposit a third oxide layer above the Schottky contact area, and open holes on the third oxide layer to deposit doped polysilicon to form a shield gate 8;

在屏蔽栅上方沉积第四氧化层,然后在该第四氧化层上方沉积掺杂多晶硅,形成控制栅9,然后在控制栅9上方沉积一定的钝化层二氧化硅10;Deposit a fourth oxide layer above the shield gate, then deposit doped polysilicon above the fourth oxide layer to form a control gate 9, and then deposit a certain passivation layer silicon dioxide 10 above the control gate 9;

其中,控制栅9和屏蔽栅8平行布置,控制栅9的下端与屏蔽栅8之间通过第四氧化层间隔布置,控制栅9的侧面与P阱区4相对布置,控制栅9的侧面与P阱区4之间通过第二氧化层间隔布置;Among them, the control gate 9 and the shield gate 8 are arranged in parallel, and the lower end of the control gate 9 and the shield gate 8 are spaced by a fourth oxide layer. The side surfaces of the control gate 9 are arranged opposite to the P-well region 4, and the side surfaces of the control gate 9 are arranged opposite to the P-well region 4. The P-well regions 4 are spaced apart by a second oxide layer;

减薄碳化硅衬底1,在碳化硅衬底的另一个表面上金属离子溅射制成电极,即得。The silicon carbide substrate 1 is thinned, and metal ions are sputtered on the other surface of the silicon carbide substrate to form an electrode.

所述第二沟槽底部的第二P+型掺杂区3的Al离子注入深度等于第一沟槽底部的第一P+型掺杂区6的Al离子注入深度。The Al ion implantation depth of the second P+ type doped region 3 at the bottom of the second trench is equal to the Al ion implantation depth of the first P+ type doped region 6 at the bottom of the first trench.

所述第一氧化层、所述第二氧化层、所述第三氧化层和所述第四氧化层的材料均为二氧化硅。The material of the first oxide layer, the second oxide layer, the third oxide layer and the fourth oxide layer is silicon dioxide.

在本发明的一个实施例内,本发明提供了一种集成SBD 的碳化硅 SGT MOSFET,包括:Within one embodiment of the present invention, the present invention provides an SBD-integrated silicon carbide SGT MOSFET, including:

碳化硅衬底 1;Silicon carbide substrate 1;

于碳化硅衬底1的一个表面上外延N-型漂移区2;epitaxially growing the N-type drift region 2 on one surface of the silicon carbide substrate 1;

在N-型漂移区2刻蚀出第一沟槽和第二沟槽,如图2所示;A first trench and a second trench are etched in the N-type drift region 2, as shown in Figure 2;

在第一沟槽和第二沟槽底部分别注入Al离子形成第二P+型掺杂区3 和第一P+型掺杂区6,在关断时作为第一耗尽区,防止源极漏电,并承担其阻断耐压,在 N-型漂移区2上方进行Al离子注入形成P阱区4,作为第二耗尽区,降低整个器件的场强分布;Al ions are implanted at the bottom of the first trench and the second trench respectively to form the second P+ type doped region 3 and the first P+ type doped region 6, which serve as the first depletion region during turn-off to prevent source leakage. And bear its blocking withstand voltage, perform Al ion implantation above the N-type drift region 2 to form the P-well region 4, which serves as the second depletion region to reduce the field intensity distribution of the entire device;

在P阱区4上方进行N离子注入形成N+型掺杂区5,如图3所示;N ions are implanted above the P well region 4 to form an N+ type doped region 5, as shown in Figure 3;

在N+型掺杂区5上表面进行金属沉积形成第一欧姆接触区 11;Metal deposition is performed on the upper surface of the N+ type doped region 5 to form a first ohmic contact region 11;

在第二沟槽底部沉积金属层形成肖特基接触区7,由于肖特基接触区7位于两个第二P+型掺杂区3中间,关断状态下,两边的第一耗尽区将连成一片,共同承受反向耐压,沟槽底部其余位置用二氧化硅10进行填充,如图 4所示;A metal layer is deposited at the bottom of the second trench to form the Schottky contact region 7. Since the Schottky contact region 7 is located between the two second P+ type doped regions 3, in the off state, the first depletion regions on both sides will They are connected together to withstand the reverse withstand voltage, and the rest of the bottom of the trench is filled with silicon dioxide 10, as shown in Figure 4;

在肖特基接触区7上面沉积掺杂多晶硅形成屏蔽栅(SGT) 8,沟槽内形成的屏蔽栅(SGT)8可以在纵向上做为场板调节 SGT-MOSFET 内部电场的分布,进而提高整个芯片的额定耐压;Doped polysilicon is deposited on the Schottky contact area 7 to form a shield gate (SGT) 8. The shield gate (SGT) 8 formed in the trench can be used as a field plate in the longitudinal direction to adjust the distribution of the internal electric field of the SGT-MOSFET, thereby improving the Rated withstand voltage of the entire chip;

将肖特基接触区7、屏蔽栅8和第一欧姆接触区11 进行互联共同作为 SGT MOSFET的源极,集成SBD的肖特基接触区7可以在小电流情况下实现续流,防止由于MOSFET体二极管的导通,解决整个MOSFET的性能严重衰退的问题;The Schottky contact area 7, the shield gate 8 and the first ohmic contact area 11 are interconnected and jointly serve as the source of the SGT MOSFET. The Schottky contact area 7 of the integrated SBD can achieve freewheeling under small current conditions, preventing the MOSFET from The conduction of the body diode solves the problem of serious performance degradation of the entire MOSFET;

生长一层氧化层二氧化硅10在屏蔽栅8上方,保留预定厚度与 SGT 屏蔽栅,防止栅极与源极短接,然后在适当的位置刻蚀沟槽氧化层至适当的深度,淀积掺杂多晶硅,形成控制栅9,最后沉积二氧化硅10填平沟槽,然后用 CMP 技术将金属表面多余的二氧化硅清除掉,如图5所示;Grow an oxide layer of silicon dioxide 10 above the shield gate 8, leaving a predetermined thickness and the SGT shield gate to prevent short circuit between the gate and the source, then etch the trench oxide layer at an appropriate position to an appropriate depth, and deposit Dope polysilicon to form a control gate 9, and finally deposit silicon dioxide 10 to fill the trench, and then use CMP technology to remove excess silicon dioxide from the metal surface, as shown in Figure 5;

减薄衬底到150μm,并在碳化硅衬底1的另一个表面上沉积金属、然后激光退火形成第二欧姆接触区12,如图 6 所示。The substrate is thinned to 150 μm, and metal is deposited on the other surface of the silicon carbide substrate 1, and then laser annealed to form the second ohmic contact region 12, as shown in Figure 6.

对于本领域技术人员而言,显然本发明不限于上述示范性实施例的细节,而且在不背离本发明的精神或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论从哪一点来看,均应将实施例看作是示范性的,而且是非限制性的,本发明的范围由所附权利要求而不是上述说明限定,因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内,不应将权利要求中的任何标记视为限制所涉及的权利要求。It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be regarded as illustrative and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is therefore intended that all claims falling within the claims All changes within the meaning and scope of equivalent elements are included in the present invention, and any sign in a claim should not be construed as limiting the claim involved.

Claims (9)

1. A SBD integrated silicon carbide SGT-MOSFET comprising:
a silicon carbide substrate;
an N-type drift region on one surface of the silicon carbide substrate;
a first trench and a second trench disposed within the N-type drift region;
the first groove and the second groove are separated by a partition wall; the partition wall is obtained by ion implantation of an N-type drift region which is not etched;
the first P+ type doped region is arranged at the bottom of the first groove;
the second P+ type doped region is arranged at the bottom of the second groove;
the P well region is arranged in the partition wall;
the N+ type doped region is positioned above the P well region;
the first ohmic contact region is positioned above the N+ type doped region;
the first oxide layer at the bottom and the side surface of the second groove are provided with a mounting hole, and a Schottky contact area formed by SBD is arranged in the mounting hole;
a third oxide layer arranged above the Schottky contact region, and a shielding grid arranged on the third oxide layer;
the Schottky contact area is tightly attached to the shielding grid, and the Schottky contact area and the shielding grid are jointly used as a source electrode of the power device to be connected through the layout;
a fourth oxide layer arranged above the shielding grid, and a control grid arranged above the fourth oxide layer;
the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through the second oxide layer;
preventing electric leakage above the control gate and above the first trench by a deposited passivation layer;
a second ohmic contact region is arranged on the other surface of the silicon carbide substrate;
a first metal layer is deposited at the bottom of the second groove, the first metal layer is not contacted with the partition wall and is contacted with a second P+ type doped region part at the bottom, a metal-semiconductor contact is formed by high-temperature annealing to form a Schottky contact region, the first metal layer is contacted with the second P+ type doped region part to form ohmic contact, and the Schottky contact region is positioned between the two second P+ type doped regions;
the bottom of the P well region is lower than the top of the first P+ type doped region, but higher than the bottom of the first P+ type doped region structure;
and the implantation depth of the first P+ type doped region is smaller than that of the P well region.
2. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the first p+ type doped region has a doping concentration that is consistent with the doping concentration of the second p+ type doped region and higher than the doping concentrations of the N-type drift region and the P-well region.
3. The SBD integrated silicon carbide SGT-MOSFET of claim 1 wherein the first trench has an etch width or depth within the N-type drift region that is less than the etch width or depth of the second trench within the N-type drift region.
4. The SBD integrated silicon carbide SGT-MOSFET of claim 1 wherein the first p+ doped region, and the P-well region have the same conductivity type, and the P-well region and the n+ doped region have different conductivity types.
5. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the second trench has a width greater than a width of the schottky contact region or the shield gate.
6. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein the schottky contact region has a thickness less than a thickness of a shield gate, the shield gate having a thickness less than a thickness of a control gate.
7. The SBD integrated silicon carbide SGT-MOSFET according to claim 1, wherein a second metal layer is deposited over the n+ doped region to form a first ohmic contact region.
8. A method of making a SBD integrated silicon carbide SGT-MOSFET according to any one of claims 1 to 7, comprising:
providing a silicon carbide substrate;
growing an N-type drift region on one surface of a silicon carbide substrate;
etching a first groove and a second groove in the N-type drift region, wherein the etching depth of the first groove in the N-type drift region is smaller than that of the second groove in the N-type drift region;
al ion implantation is carried out at the bottom of the first groove to form two adjacent first P+ type doped regions separated by an N-type drift region;
al ion implantation is carried out at the bottom of the second groove to form two second P+ type doped regions with equal size;
performing Al ion implantation on the partition wall between the first groove and the second groove to form a P well region;
n ion implantation is carried out above the P well region, and an N+ type doped region is formed;
performing metal deposition and high-temperature annealing on the upper part of the N+ type doped region to form a first ohmic contact region;
depositing a first oxide layer and a second oxide layer on the bottom and the side surface of the second groove, and opening a hole on the first oxide layer on the bottom surface to deposit an SBD (styrene-butadiene-styrene) to form a Schottky contact area;
depositing a third oxide layer above the Schottky contact region, and opening a hole on the third oxide layer to deposit doped polysilicon to form a shielding gate;
depositing a fourth oxide layer above the shielding gate, and then depositing doped polysilicon above the fourth oxide layer to form a control gate;
the control grid and the shielding grid are arranged in parallel, the lower end of the control grid and the shielding grid are arranged at intervals through a fourth oxide layer, the side face of the control grid is arranged opposite to the P well region, and the side face of the control grid and the P well region are arranged at intervals through a second oxide layer;
thinning the silicon carbide substrate, and sputtering metal ions on the other surface of the silicon carbide substrate to prepare an electrode.
9. The method of claim 8, wherein the second p+ type doped region Al ion implantation depth at the bottom of the second trench is equal to the first p+ type doped region Al ion implantation depth at the bottom of the first trench.
CN202310986654.5A 2023-08-08 2023-08-08 SBD integrated silicon carbide SGT-MOSFET and preparation method thereof Active CN116721925B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310986654.5A CN116721925B (en) 2023-08-08 2023-08-08 SBD integrated silicon carbide SGT-MOSFET and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310986654.5A CN116721925B (en) 2023-08-08 2023-08-08 SBD integrated silicon carbide SGT-MOSFET and preparation method thereof

Publications (2)

Publication Number Publication Date
CN116721925A CN116721925A (en) 2023-09-08
CN116721925B true CN116721925B (en) 2024-02-09

Family

ID=87866422

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310986654.5A Active CN116721925B (en) 2023-08-08 2023-08-08 SBD integrated silicon carbide SGT-MOSFET and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116721925B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116994956B (en) * 2023-09-26 2023-12-05 深圳市万微半导体有限公司 Silicon carbide power device, preparation method thereof and chip
CN117238968B (en) * 2023-11-10 2024-03-15 安建科技(深圳)有限公司 Trench gate silicon carbide MOSFET device and preparation method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109244136A (en) * 2018-09-19 2019-01-18 电子科技大学 Slot bottom Schottky contacts SiC MOSFET element
CN114649421A (en) * 2020-12-17 2022-06-21 黄智方 Semiconductor structure with trench junction barrier schottky diode
CN116110796A (en) * 2023-04-17 2023-05-12 深圳平创半导体有限公司 Silicon carbide SGT-MOSFET with integrated SBD and its preparation method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5498431B2 (en) * 2011-02-02 2014-05-21 ローム株式会社 Semiconductor device and manufacturing method thereof
JP5920970B2 (en) * 2011-11-30 2016-05-24 ローム株式会社 Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109244136A (en) * 2018-09-19 2019-01-18 电子科技大学 Slot bottom Schottky contacts SiC MOSFET element
CN114649421A (en) * 2020-12-17 2022-06-21 黄智方 Semiconductor structure with trench junction barrier schottky diode
CN116110796A (en) * 2023-04-17 2023-05-12 深圳平创半导体有限公司 Silicon carbide SGT-MOSFET with integrated SBD and its preparation method

Also Published As

Publication number Publication date
CN116721925A (en) 2023-09-08

Similar Documents

Publication Publication Date Title
CN111403486B (en) Groove type MOSFET structure and manufacturing method thereof
CN116721925B (en) SBD integrated silicon carbide SGT-MOSFET and preparation method thereof
CN109920839B (en) P+ shielding layer potential adjustable silicon carbide MOSFET device and preparation method
CN102723363B (en) A kind of VDMOS device and preparation method thereof
CN114038908B (en) Diode-integrated trench gate silicon carbide MOSFET device and method of manufacture
CN114784108B (en) Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof
CN114664929B (en) Split gate SiC MOSFET integrated with heterojunction diode and manufacturing method thereof
JPWO2015019797A1 (en) High voltage semiconductor device and manufacturing method thereof
CN114944421B (en) Trench type silicon carbide insulated gate field effect transistor and manufacturing method thereof
CN105810754B (en) A kind of metal-oxide-semiconductor diode with accumulation layer
CN114551586B (en) Silicon carbide split gate MOSFET cell with integrated gated diode and preparation method
CN116110796B (en) Silicon carbide SGT-MOSFET with integrated SBD and its preparation method
CN106057798A (en) A MOSFET with Integrated Trench Schottky
CN114843332A (en) Low-power-consumption high-reliability half-packaged trench gate MOSFET device and preparation method thereof
CN113972261A (en) Silicon carbide semiconductor device and preparation method
CN117038455A (en) MOSFET structure and process method
CN117080269A (en) Silicon carbide MOSFET device and preparation method thereof
CN114784107B (en) SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof
CN105957894A (en) DMOS with composite dielectric layer structure
CN106098799A (en) A kind of accumulation type trench diode
CN106057906B (en) A kind of accumulation type DMOS with p type buried layer
CN110504313B (en) A lateral trench type insulated gate bipolar transistor and its preparation method
CN116525683B (en) A deep well type SiC Mosfet device and preparation method
CN117913143A (en) Groove type SiC MOSFET structure and manufacturing method
CN114784109B (en) Planar gate SiC MOSFET and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant