CN111244177A - Structure and manufacturing process of groove type MOS device and electronic device - Google Patents
Structure and manufacturing process of groove type MOS device and electronic device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 29
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- 238000002347 injection Methods 0.000 claims description 12
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- 238000000151 deposition Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
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- -1 boron ions Chemical class 0.000 description 2
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- 230000003071 parasitic effect Effects 0.000 description 2
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a structure of a groove type MOS device, a manufacturing process and an electronic device, it can play the guard action to the ditch groove gate, avoid the ditch groove gate to be punctured, the time that can bear the short circuit simultaneously is longer, switching loss is little, the structure of ditch groove type MOS device includes substrate layer and the epitaxial layer that is located substrate layer top, the below of substrate layer is the drain electrode zone layer, the epitaxial layer upper end is provided with the P well region layer, be provided with N + source electrode zone layer on the P well region layer, source electrode contact P + district layer, N + source electrode zone top is provided with insulating medium layer, N + source electrode zone layer, source electrode contact P + district layer top is provided with source level metal area layer, still including passing N + source electrode zone and P well region layer, the slot in the epitaxial layer downwardly extending, be provided with the packing semiconductor in the ditch groove, be located the epitaxial layer of bottom and be provided with P.
Description
Technical Field
The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a structure and a manufacturing process of a groove type MOS device and an electronic device.
Background
With the continuous and rapid development of economy in China, the energy consumption is increased year by year, and particularly under the large background of global warming, low-carbon economy gradually becomes a global hotspot, so that the energy conservation becomes one of the basic national policies of China; the trench MOS device is a semiconductor device which is developed rapidly and has a good market prospect, has the advantages of high switching speed, high input impedance, good thermal stability, high reliability, and the like, and is widely applied to the fields of power supply circuits of computers, communication equipment and general office equipment and automotive electronic circuits.
Taking an N-type trench MOS device as an example, the process flow is as follows: firstly, a groove is etched on the surface of an N-epitaxial layer, a gate oxide layer grows in the groove, N-type heavily doped polycrystalline silicon is filled in the groove in a deposition mode to form a grid electrode, then boron ions are injected into the surface of the epitaxial layer to form a P-channel region after heating diffusion, and then phosphorus ions are injected at low energy to form an N + source region. And etching a contact hole on the surface of the epitaxial layer, filling metal, connecting the channel region and the source region, and taking the back N + substrate as a drain region. Compared with the traditional MOSFET, the MOSFET has the advantages of high switching speed, low on resistance, high voltage resistance, large current, good thermal stability and the like, and is widely applied.
However, in the conventional trench MOS device, a high electric field is easily generated at the bottom of the trench gate, and the device is easily broken down under the condition of lacking protection, and particularly has poor short-circuit capability and short-circuit time.
Disclosure of Invention
In view of the above problems, the present invention provides a structure, a manufacturing process and an electronic device of a trench MOS device, which can protect a trench gate, prevent the trench gate from being broken down, and simultaneously endure a short circuit for a long time with a small switching loss.
The technical scheme is as follows: the utility model provides a structure of ditch cell type MOS device, includes the substrate layer and is located the epitaxial layer of substrate layer top, the below of substrate layer is drain electrode zone layer, the epitaxial layer upper end is provided with P well region layer, be provided with N + source region layer, source electrode contact P + district layer on the P well region layer, N + source region top is provided with insulating medium layer, N + source region layer, source electrode contact P + district layer top are provided with source level metal area layer, still include to pass N + source region with P well region layer, downwardly extending reach slot in the epitaxial layer, the ditch inslot is provided with the packing semiconductor, its characterized in that: and a P + region layer is arranged in the epitaxial layer at the bottom of the groove.
Further, the filling semiconductor comprises a gate oxide layer and a polysilicon layer which are sequentially arranged.
Further, the epitaxial layer is an N-type Si epitaxial layer, and the substrate layer is an N-type Si substrate.
Further, the insulating dielectric layer is any one of a silicon dioxide layer and a silicon nitride layer.
Further, the source metal area layer is an Al layer.
A manufacturing process of a groove type MOS device is characterized by comprising the following steps:
step 1: providing a substrate, growing an epitaxial layer on the substrate, and growing a mask layer on the upper surface of the epitaxial layer; photoetching the mask layer, and forming a process window at a corresponding position on the mask layer;
step 2: etching the epitaxial layer at the process window to form a groove on the epitaxial layer;
and step 3: injecting P-type impurities into the epitaxial layer at the bottom of the groove in an ion injection mode to form a P + region layer, and removing the mask layer on the epitaxial layer;
and 4, step 4: growing a grid oxide layer on the upper surfaces of the groove and the epitaxial layer, and depositing a polycrystalline silicon layer on the grid oxide layer;
and 5: etching to remove the polysilicon layer and the gate oxide layer on the upper surface of the epitaxial layer to form a trench MOSFET gate structure;
step 6: forming a P-well region layer, an N + source region layer and a source contact P + region layer on the epitaxial layer sequentially through an ion implantation process;
and 7: forming an insulating medium layer at the upper ends of the groove and the N + source electrode region layer;
and 8: depositing metal on the insulating medium layer to form a source metal area layer, wherein the P + area layer and the N + source area layer are respectively connected with the source metal area layer to form a source metal electrode;
and step 9: and depositing a back metal layer on the lower surface of the substrate to form a drain electrode region layer, wherein the back metal layer forms a drain electrode metal electrode.
Furthermore, in the step 3, the magnitude order of the injected P-type impurity is more than or equal to 1E +15cm-3, and the thickness of the P + region layer is 2.0-6.0 μm.
Further, in step 5, a thermal oxidation process is used to form the gate oxide layer.
Further, step 6 specifically includes the following steps:
injecting P-type impurities on the epitaxial layer through an ion injection process to form a P-well region layer;
growing a mask layer on the P-well region layer, forming a process window at a corresponding position on the P-well region layer by adopting a photoetching technology, injecting N-type impurities at the position of the process window through an ion injection process to form an N + source region layer, and removing the mask layer;
growing a mask layer on the P-well region layer, forming a process window at a corresponding position on the P-well region layer by adopting a photoetching technology, injecting high-concentration P-type impurities at the position of the process window through an ion injection process to form a source electrode contact P + region layer, and removing the mask layer.
An electronic device, comprising the trench type MOS device.
According to the trench type MOS device, the P + region is manufactured at the bottom of the trench gate to shield a strong electric field, so that the trench gate is protected, the trench gate is prevented from being broken down, short circuit can be borne for a long time, and Cgd capacitance in parasitic capacitance can be obviously reduced, so that switching loss is reduced, and the performance of the MOS device is improved.
Drawings
FIG. 1 is a schematic structural diagram of a trench MOS device according to the present invention;
FIG. 2 is a flow chart of a process for fabricating a trench MOS device according to the invention;
FIG. 3 is a schematic diagram of the preparation step of step 1 in the process for manufacturing a trench type MOS device according to the present invention;
FIG. 4 is a schematic diagram illustrating a manufacturing step of step 2 in the manufacturing process of the trench type MOS device according to the present invention;
FIG. 5 is a schematic diagram illustrating a step of step 3 in the process of fabricating a trench type MOS device according to the present invention;
FIG. 6 is a schematic diagram illustrating a manufacturing step of step 4 in the manufacturing process of the trench type MOS device according to the present invention;
FIG. 7 is a schematic diagram illustrating a step of step 5 in the process of fabricating a trench MOS device according to the present invention;
FIG. 8 is a schematic diagram illustrating a step of step 6 in the process of fabricating a trench MOS device according to the present invention;
FIG. 9 is a schematic diagram illustrating a step of step 7 in the process of fabricating a trench MOS device according to the present invention;
FIG. 10 is a schematic diagram illustrating a step of step 8 in the process of fabricating a trench MOS device according to the present invention;
fig. 11 is a schematic view of the preparation step of step 9 in the process of manufacturing the trench MOS device according to the present invention.
Detailed Description
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
Spatially relative terms, such as "under", "at a lower end", "below", "over", "at an upper end", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures.
Referring to fig. 1, the structure of a trench type MOS device of the present invention includes a substrate layer 1 and an epitaxial layer 2 located above the substrate layer 1, where the epitaxial layer in this embodiment is an N-type Si epitaxial layer, the substrate layer is an N-type Si substrate, a drain region layer 3 is located below the substrate layer 2, a P-well region layer 4 is located at an upper end of the epitaxial layer 2, an N + source region layer 5 and a source contact P + region layer 6 are located on the P-well region layer 4, an insulating dielectric layer 7 is located above the N + source region 5, a source metal region layer 8 is located above the insulating dielectric layer 7, the N + source region layer 5 and the source contact P + region layer 6, a trench 9 passing through the N + source region 5 and the P-well region layer 4 and extending downward into the epitaxial layer 2, a filling semiconductor is located in the trench 9, and in this embodiment, the filling semiconductor includes a gate oxide layer 10 and, a P + region layer 12 is provided in the epitaxial layer at the bottom of the trench.
In this embodiment, the insulating dielectric layer is a silicon dioxide layer, and in other embodiments of the present invention, a silicon nitride layer may also be used.
In addition, in the present embodiment, the source metal region layer is an Al layer.
In the trench type MOS device in the above embodiment, a P + region is formed at the bottom of the trench gate to shield a strong electric field, so as to protect the trench gate and prevent the trench gate from being broken down, and meanwhile, the short circuit can be endured for a long time, and the breakdown voltage, the threshold voltage and the specific on-resistance of the trench type MOS device are not lost, parasitic capacitances exist among three pins of the MOS transistor, which are not required by people and are generated due to the limitation of the manufacturing process, whereas the Cgd capacitance of the trench type MOS device in the above embodiment is greatly reduced, which indicates that the structure can greatly improve the switching characteristics of the device without losing the breakdown voltage and the threshold voltage, the voltage at two ends of the MOS transistor has a process of decreasing, the flowing current has a process of increasing, and the loss of the MOS transistor is the product of the voltage and the current in this period, which is called switching loss, the groove type MOS device in the embodiment can reduce the switching loss and improve the performance of the MOS tube.
The embodiment of the invention also provides a manufacturing process of the groove type MOS device, which comprises the following steps:
step 1: providing a substrate 1, growing an epitaxial layer 2 on the substrate 1, wherein the epitaxial layer is made of a semiconductor material and can be one of Si, SiB, SiGe, SiC, SiP, SiGeB, and SiCP, in this embodiment, the epitaxial layer is made of Si, the thickness of the epitaxial layer can be set reasonably according to the requirements of specific devices, the epitaxial layer can be formed by any suitable method for selective epitaxial growth, which is well known to those skilled in the art, low-pressure chemical vapor deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and then a mask layer 13 is grown on the upper surface of the epitaxial layer; photoetching is carried out on the mask layer 13, and a process window is formed at the corresponding position on the mask layer 13 and used for defining the position and the size of a groove to be formed;
step 2: etching the epitaxial layer at the process window to form a groove 9 on the epitaxial layer;
and step 3: injecting a P-type impurity on the epitaxial layer at the bottom of the trench in an ion injection manner to form a P + region layer, and removing the mask layer on the epitaxial layer, wherein in the embodiment, the magnitude of the injected P-type impurity is more than or equal to 1E +15cm < -3 >, and the thickness of the P + region layer is 2.0 to 6.0 microns;
and 4, step 4: growing a grid oxide layer on the upper surfaces of the groove and the epitaxial layer by adopting a thermal oxidation process, and depositing a polycrystalline silicon layer on the grid oxide layer;
and 5: etching to remove the polysilicon layer and the gate oxide layer on the upper surface of the epitaxial layer to form a trench MOSFET gate structure;
step 6: a P-well region layer, an N + source region layer and a source contact P + region layer are formed on the epitaxial layer by ion implantation, specifically,
injecting P-type impurities on the epitaxial layer through an ion injection process to form a P-well region layer;
growing a mask layer on the P-well region layer, forming a process window at a corresponding position on the P-well region layer by adopting a photoetching technology, injecting N-type impurities at the position of the process window through an ion injection process to form an N + source region layer, and removing the mask layer;
growing a mask layer on the P-well region layer, forming a process window at a corresponding position on the P-well region layer by adopting a photoetching technology, injecting high-concentration P-type impurities at the position of the process window through an ion injection process to form a source electrode contact P + region layer, and removing the mask layer.
And 7: forming an insulating medium layer at the upper ends of the groove and the N + source electrode region layer;
and 8: depositing metal on the insulating medium layer to form a source metal area layer, wherein the P + area layer and the N + source area layer are respectively connected with the source metal area layer to form a source metal electrode;
and step 9: and depositing a back metal layer on the lower surface of the substrate to form a drain electrode region layer, wherein the back metal layer forms a drain electrode metal electrode.
The manufacturing process of the groove type MOS device in the embodiment is compatible with the traditional process, is easy to realize, has the advantages of simple manufacturing process flow and excellent characteristics, does not need to increase extra preparation cost, can be put into production in large batch, reduces the cost, and increases the market competitiveness, so that the groove type MOS device has prominent substantive characteristics and remarkable progress.
An embodiment of the present invention further provides an electronic apparatus including a trench type MOS device formed using one of the fabrication processes in the foregoing embodiments. The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a VD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance and reliability because the groove type MOS device is used.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (10)
1. The utility model provides a structure of ditch cell type MOS device, includes the substrate layer and is located the epitaxial layer of substrate layer top, the below of substrate layer is drain electrode zone layer, the epitaxial layer upper end is provided with P well region layer, be provided with N + source region layer, source electrode contact P + district layer on the P well region layer, N + source region top is provided with insulating dielectric layer, N + source region layer, source electrode contact P + district layer top are provided with source level metal area layer, still include to pass N + source region with P well region layer, downwardly extending reach slot in the epitaxial layer, the ditch inslot is provided with the packing semiconductor, its characterized in that: and a P + region layer is arranged in the epitaxial layer at the bottom of the groove.
2. The structure of a trench type MOS device as claimed in claim 1, wherein: the filling semiconductor comprises a grid oxide layer and a polysilicon layer which are sequentially arranged.
3. The structure of a trench type MOS device as claimed in claim 1, wherein: the epitaxial layer is an N-type Si epitaxial layer, and the substrate layer is an N-type Si substrate.
4. The structure of a trench type MOS device as claimed in claim 1, wherein: the insulating medium layer is any one of a silicon dioxide layer and a silicon nitride layer.
5. The structure of a trench type MOS device as claimed in claim 1, wherein: the source metal area layer is an Al layer.
6. A manufacturing process of a groove type MOS device is characterized by comprising the following steps:
step 1: providing a substrate, growing an epitaxial layer on the substrate, and growing a mask layer on the upper surface of the epitaxial layer; photoetching the mask layer, and forming a process window at a corresponding position on the mask layer;
step 2: etching the epitaxial layer at the process window to form a groove on the epitaxial layer;
and step 3: injecting P-type impurities into the epitaxial layer at the bottom of the groove in an ion injection mode to form a P + region layer, and removing the mask layer on the epitaxial layer;
and 4, step 4: growing a grid oxide layer on the upper surfaces of the groove and the epitaxial layer, and depositing a polycrystalline silicon layer on the grid oxide layer;
and 5: etching to remove the polysilicon layer and the gate oxide layer on the upper surface of the epitaxial layer to form a trench MOSFET gate structure;
step 6: forming a P-well region layer, an N + source region layer and a source contact P + region layer on the epitaxial layer sequentially through an ion implantation process;
and 7: forming an insulating medium layer at the upper ends of the groove and the N + source electrode region layer;
and 8: depositing metal on the insulating medium layer to form a source metal area layer, wherein the P + area layer and the N + source area layer are respectively connected with the source metal area layer to form a source metal electrode;
and step 9: and depositing a back metal layer on the lower surface of the substrate to form a drain electrode region layer, wherein the back metal layer forms a drain electrode metal electrode.
7. The process of claim 6, wherein: in step 3, the magnitude order of the injected P-type impurity is more than or equal to 1E +15cm-3The thickness of the P + region layer is 2.0-6.0 μm.
8. The process of claim 6, wherein: in step 5, a thermal oxidation process is used to form the gate oxide layer.
9. The process for manufacturing a trench type MOS device according to claim 6, wherein the step 6 specifically comprises the following steps:
injecting P-type impurities on the epitaxial layer through an ion injection process to form a P-well region layer;
growing a mask layer on the P-well region layer, forming a process window at a corresponding position on the P-well region layer by adopting a photoetching technology, injecting N-type impurities at the position of the process window through an ion injection process to form an N + source region layer, and removing the mask layer;
growing a mask layer on the P-well region layer, forming a process window at a corresponding position on the P-well region layer by adopting a photoetching technology, injecting high-concentration P-type impurities at the position of the process window through an ion injection process to form a source electrode contact P + region layer, and removing the mask layer.
10. An electronic apparatus comprising the trench type MOS device according to claims 1 to 5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112185816A (en) * | 2020-08-14 | 2021-01-05 | 江苏东海半导体科技有限公司 | High-energy-efficiency shielded gate trench MOSFET and manufacturing method thereof |
| CN113299739A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Power device epitaxial structure and manufacturing method thereof |
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| CN109979987A (en) * | 2017-12-28 | 2019-07-05 | 深圳尚阳通科技有限公司 | A kind of shield grid power device and manufacturing method |
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| CN112185816A (en) * | 2020-08-14 | 2021-01-05 | 江苏东海半导体科技有限公司 | High-energy-efficiency shielded gate trench MOSFET and manufacturing method thereof |
| CN112185816B (en) * | 2020-08-14 | 2022-04-08 | 江苏东海半导体股份有限公司 | High-energy-efficiency shielded gate trench MOSFET and manufacturing method thereof |
| CN113299739A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Power device epitaxial structure and manufacturing method thereof |
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