CN115083920B - Manufacturing method of silicon carbide MOSFET with adjustable charge balance threshold voltage - Google Patents
Manufacturing method of silicon carbide MOSFET with adjustable charge balance threshold voltage Download PDFInfo
- Publication number
- CN115083920B CN115083920B CN202211003446.0A CN202211003446A CN115083920B CN 115083920 B CN115083920 B CN 115083920B CN 202211003446 A CN202211003446 A CN 202211003446A CN 115083920 B CN115083920 B CN 115083920B
- Authority
- CN
- China
- Prior art keywords
- barrier layer
- source region
- etching
- layer
- conductive channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 6
- 238000009826 distribution Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
Abstract
The invention provides a manufacturing method of a silicon carbide MOSFET with adjustable charge balance threshold voltage, which comprises the following steps: growing a barrier layer on the isolation layer of the silicon carbide substrate, and performing ion implantation on the isolation layer after etching to form a conductive channel region; growing the barrier layer again, etching the barrier layer to form a through hole, and performing ion implantation on the isolation layer through the through hole to form a drain source region and a source region, wherein the left side surface of the conductive channel region is connected to the right side surface of the source region, and the right side surface of the conductive channel region is connected to the left side surface of the drain source region; respectively depositing a drain metal layer and a source metal layer on the drain source region and the source region; growing the barrier layer again, and oxidizing to form an insulating layer after etching; growing the barrier layer again, and etching to form a groove; and growing the barrier layer again, depositing on the groove after etching to form a grid metal layer, and removing all the barrier layers, so that the charge distribution in the channel is more balanced, the charge balance of the channel is realized, and the use of the device is ensured.
Description
Technical Field
The invention relates to a manufacturing method of a silicon carbide MOSFET with adjustable charge balance threshold voltage.
Background
Silicon carbide (SiC) materials for silicon carbide devices have received much attention and research due to their excellent physical properties. The excellent characteristics of high temperature, high frequency and the like gradually become the focus of attention of researchers.
In a silicon carbide transverse MOSFET, the drain-source voltage distribution of a traditional MOSFET ensures that the charge distribution of a logic device in a conducting channel is in gradient distribution, at this time, the channel charge distribution is not uniform, the channel resistance is not uniformly distributed transversely, different resistances can be formed in different areas, and the problem of non-uniform heat distribution can be formed when current flows, so that the failure of the device is easily caused.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for manufacturing a silicon carbide MOSFET with adjustable charge balance threshold voltage, so that the charge distribution in a channel is more balanced, the charge balance of the channel is realized, and the use of a device is ensured.
The invention is realized in the following way: a method for manufacturing a silicon carbide MOSFET with adjustable charge balance threshold voltage comprises the following steps:
and 6, growing the barrier layer again, etching the barrier layer to form a through hole, depositing on the groove to form a gate metal layer, and removing all the barrier layers.
Further, the conductive channel region includes at least two conductive channels, and the doping concentration of the left conductive channel is less than the doping concentration of the right conductive channel, where the step 1 is further specifically:
growing a barrier layer on the isolation layer of the silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the isolation layer through the through hole to form a conductive channel; and repeating the steps until all the conductive channel regions are completed.
Furthermore, the conductive channel region and the isolation layer are both of a P type.
Furthermore, the drain source region and the source region are both N + type.
The invention has the following advantages:
the concentration gradient is established in the conducting channel of the MOSFET; the concentration gradient is gradually reduced from the drain to the source doping concentration; the source and drain of the transverse device are not interchangeable and have an asymmetric structure; the threshold voltage of the device can be adjusted by adjusting the doping concentration in the conducting channel with the concentration gradient; the charge distribution in the channel is more balanced, the charge balance of the channel is realized, and the use of the device is ensured.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a first flowchart of a method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage according to the present invention.
Fig. 2 is a flow chart of a second method of fabricating a silicon carbide MOSFET with an adjustable charge balance threshold voltage in accordance with the present invention.
Fig. 3 is a flow chart of a third method for manufacturing a silicon carbide MOSFET with adjustable charge balance threshold voltage according to the present invention.
Fig. 4 is a flow chart of a method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage in accordance with a fourth aspect of the present invention.
Fig. 5 is a flow chart of a method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage according to a fifth aspect of the present invention.
Fig. 6 is a flow chart of a sixth method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage in accordance with the present invention.
Fig. 7 is a flow chart of a seventh method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage in accordance with the present invention.
Fig. 8 is a flow chart of an eighth method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage in accordance with the present invention.
Fig. 9 is a flow chart of a method of fabricating a silicon carbide MOSFET with adjustable charge balance threshold voltage in accordance with the present invention.
Fig. 10 is a schematic diagram of a silicon carbide MOSFET with adjustable charge balance threshold voltage according to the present invention.
Detailed Description
As shown in fig. 1 to 10, the present invention provides a method for manufacturing a silicon carbide MOSFET with adjustable charge balance threshold voltage, comprising the steps of:
and 6, growing the barrier layer a again, etching the barrier layer a to form a through hole, depositing on the groove 61 to form a gate metal layer 8, and removing all the barrier layer a.
The conductive channel region 5 includes at least two conductive channels, the doping concentration of the left conductive channel is less than the doping concentration of the right conductive channel, and the step 1 further specifically includes:
growing a barrier layer a on the isolation layer 2 of the silicon carbide substrate 1, etching the barrier layer a to form a through hole, and performing ion implantation on the isolation layer 2 through the through hole to form a conductive channel; repeating the steps until all the conductive channel regions 5 are completed; for example: when 4 conductive channels are provided, a barrier layer a grows on the isolation layer 2 of the silicon carbide substrate 1, a through hole is formed by etching the barrier layer a, ion implantation is performed on the isolation layer 2 through the through hole to form a first conductive channel region 51, the barrier layer a grows on the isolation layer 2 of the silicon carbide substrate 1, a through hole is formed by etching the barrier layer a, ion implantation is performed on the isolation layer 2 through the through hole to form a second conductive channel region 52, the barrier layer a grows on the isolation layer 2 of the silicon carbide substrate 1, a through hole is formed by etching the barrier layer a, ion implantation is performed on the isolation layer 2 through the through hole to form a third conductive channel region 53, the barrier layer a grows on the isolation layer 2 of the silicon carbide substrate 1, a through hole is formed by etching the barrier layer a, and ion implantation is performed on the isolation layer 2 through the through hole to form a fourth conductive channel region 54.
As shown in fig. 10, the MOSFET obtained by the above manufacturing method includes:
a silicon carbide substrate 1;
the isolation layer 2 is arranged on the upper side face of the silicon carbide substrate 1, and the isolation layer 2 is of a P type;
the source region 3 is arranged on the upper side face of the isolation layer 2, and the source region 3 is of an N + type;
the drain source region 4 is arranged on the upper side face of the isolation layer 2, and the drain source region 4 is of an N + type;
the conductive channel region 5 is arranged on the upper side surface of the isolation layer 2, the left side surface of the conductive channel region 5 is connected to the right side surface of the source region 3, and the right side surface of the conductive channel region 5 is connected to the left side surface of the drain source region 4; the conductive channel region 5 comprises at least two conductive channels, the doping concentration of the left conductive channel is less than that of the right conductive channel, and the conductive channel region 5 is of a P type;
the insulating layer 6 is arranged on the upper side face of the conductive channel region 5, and the insulating layer 6 is provided with a groove 61;
a drain metal layer 7, the drain metal layer 7 being connected to the drain source region 4;
the gate metal layer 8 is arranged in the groove 61 of the insulating layer 6, and the gate metal layer 8 is arranged in the groove;
and a source metal layer 9, the source metal layer 9 being connected to the source region 3.
The conducting channel region 5 can be divided into at least two conducting channels, the doping concentration of the two conducting channels is gradually reduced from a drain metal layer 7 to a source metal layer 9 and used for balancing the conducting channel charge during the working of the two conducting channels, the MOSFET conducting channel has no withstand voltage requirement because the voltage during the working of a transverse logic device has a large margin from the breakdown voltage of the transverse logic device, and the withstand voltage requirement can be met even after the withstand voltage is reduced, the lowest doping concentration of the MOSFET conducting channel close to the source metal layer 9 is that the source metal layer 9 of the transverse logic device is connected with the lowest potential, the gate control electric field from a gate metal layer 8 to the source metal layer 9 is the largest, the generated inversion charge is the most, and the concentration of the inversion layer is high when the MOSFET conducting channel is opened compared with the drain metal layer 7, so that the p-type doping concentration needs to be increased, the carrier concentration of the inversion drain is reduced when the drain is subjected to high voltage, the charge distribution in the whole channel is more uniform, and the channel charge balance is realized; the doping concentration of the MOSFET conductive channel from the source electrode metal layer 9 to the drain electrode metal layer 7 is lower and lower, the voltage required for reaching the same inversion type charge concentration is lower and lower, and when the drain electrode metal layer 7 is increased with high voltage, the charge distribution is more balanced; therefore, the threshold voltage thereof can be adjusted by adjusting the doping concentration of the entire conductive channel.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (3)
1. A method of fabricating a silicon carbide MOSFET having a tunable charge balance threshold voltage, comprising the steps of:
step 1, growing a barrier layer on an isolation layer of a silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the isolation layer through the through hole to form a conductive channel; repeating the steps until all the conductive channels are completed, and finally forming a conductive channel region, wherein the conductive channel region comprises at least two conductive channels, the doping concentration of the conductive channel on the left side is smaller than that of the conductive channel on the right side, and the isolating layer is of a P type;
step 2, growing the barrier layer again, etching the barrier layer to form a through hole, and performing ion implantation on the isolation layer through the through hole to form a drain source region and a source region, wherein the left side surface of the conductive channel region is connected to the right side surface of the source region, and the right side surface of the conductive channel region is connected to the left side surface of the drain source region;
step 3, respectively depositing a drain metal layer and a source metal layer on the drain source region and the source region;
step 4, growing the barrier layer again, etching the barrier layer to form a through hole, and oxidizing to form an insulating layer;
step 5, growing the barrier layer again, etching the barrier layer to form a through hole, and continuously etching to form a groove;
and 6, growing the barrier layer again, etching the barrier layer to form a through hole, depositing on the groove to form a gate metal layer, and removing all the barrier layers.
2. The method of claim 1, wherein the conductive channel region is P-type.
3. The method of claim 1, wherein the drain source region and the source region are both N + type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211003446.0A CN115083920B (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of silicon carbide MOSFET with adjustable charge balance threshold voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211003446.0A CN115083920B (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of silicon carbide MOSFET with adjustable charge balance threshold voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115083920A CN115083920A (en) | 2022-09-20 |
| CN115083920B true CN115083920B (en) | 2022-11-15 |
Family
ID=83244201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211003446.0A Active CN115083920B (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of silicon carbide MOSFET with adjustable charge balance threshold voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115083920B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118924A (en) * | 2006-07-31 | 2008-02-06 | 中国科学院微电子研究所 | Silicon device structure of high puncture voltage insulators and method for making same |
| CN102412297A (en) * | 2011-08-16 | 2012-04-11 | 桂林电子科技大学 | Silicon-based power device structure based on substrate bias technology |
| CN102479718A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) |
| CN104701381A (en) * | 2015-03-03 | 2015-06-10 | 南京邮电大学 | Two-dimensional SJ/RESURF LDMOS apparatus with step doping in P column region and manufacturing method thereof |
| CN111987166A (en) * | 2020-09-07 | 2020-11-24 | 杰华特微电子（杭州）有限公司 | Method for manufacturing lateral double-diffused transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3881840B2 (en) * | 2000-11-14 | 2007-02-14 | 独立行政法人産業技術総合研究所 | Semiconductor device |
| US11605732B2 (en) * | 2019-11-06 | 2023-03-14 | Semiconductor Components Industries, Llc | Power device with graded channel |
-
2022
- 2022-08-22 CN CN202211003446.0A patent/CN115083920B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118924A (en) * | 2006-07-31 | 2008-02-06 | 中国科学院微电子研究所 | Silicon device structure of high puncture voltage insulators and method for making same |
| CN102479718A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) |
| CN102412297A (en) * | 2011-08-16 | 2012-04-11 | 桂林电子科技大学 | Silicon-based power device structure based on substrate bias technology |
| CN104701381A (en) * | 2015-03-03 | 2015-06-10 | 南京邮电大学 | Two-dimensional SJ/RESURF LDMOS apparatus with step doping in P column region and manufacturing method thereof |
| CN111987166A (en) * | 2020-09-07 | 2020-11-24 | 杰华特微电子（杭州）有限公司 | Method for manufacturing lateral double-diffused transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115083920A (en) | 2022-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111799322B (en) | Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method | |
| WO2017041268A1 (en) | Silicon carbide mosfet device and manufacturing method therefor | |
| CN102610641B (en) | High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN104617136A (en) | 4H-silicon carbide based N-channel accumulating high-voltage insulated gate bipolar transistor | |
| CN108682624A (en) | A kind of igbt chip production method with composite grid | |
| CN114512535B (en) | Manufacturing method of double-channel SiC transverse LDMOS power device | |
| CN115632031B (en) | Manufacturing method of planar gate silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with gate protection mechanism | |
| CN102479806B (en) | Super junction semiconductor device and manufacturing method thereof | |
| CN114496761B (en) | Manufacturing method of circular gate longitudinal MOSFET power device | |
| CN115360096A (en) | Manufacturing method of planar gate silicon carbide MOSFET integrated with heterojunction diode | |
| JP6250938B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN114744029A (en) | Manufacturing method of P-type SiC LDMOS power device | |
| CN109585445B (en) | Power MOSFET | |
| CN115083920B (en) | Manufacturing method of silicon carbide MOSFET with adjustable charge balance threshold voltage | |
| CN111916502B (en) | Split-gate power MOSFET device with high-doping layer and preparation method thereof | |
| CN116190438A (en) | AlGaN/GaN vertical high electron mobility transistor and manufacturing method thereof | |
| CN116722028A (en) | Silicon carbide MOSFET device structure and preparation method | |
| CN107452806B (en) | Longitudinal double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer and manufacturing method thereof | |
| CN107046062B (en) | Longitudinal double-diffusion metal oxide semiconductor field effect transistor with semi-insulating polycrystalline silicon layer | |
| CN108054215B (en) | Junction field effect transistor and manufacturing method thereof | |
| CN218215313U (en) | Plane gate silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with heterojunction diode | |
| CN206349369U (en) | A kind of silicon carbide thyristor | |
| CN115083919B (en) | Manufacturing method of silicon carbide MOSFET capable of increasing voltage endurance capacity | |
| CN206210802U (en) | A kind of carborundum electrostatic induction device | |
| CN116504841B (en) | High-reliability silicon carbide MOSFET device and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |