CN102479806B - Super junction semiconductor device and manufacturing method thereof - Google Patents
Super junction semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102479806B CN102479806B CN201010553535.3A CN201010553535A CN102479806B CN 102479806 B CN102479806 B CN 102479806B CN 201010553535 A CN201010553535 A CN 201010553535A CN 102479806 B CN102479806 B CN 102479806B
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Abstract
The invention discloses a super junction semiconductor device. P type and N type semiconductor thin layer structures are alternatively arranged on an N<+> silicon substrate, wherein P type impurity concentration varies along a groove direction; the impurity concentration of a part close to the upper surface of a P/N thin layer is higher than the concentration of P type impurities required by charge balance; the impurity concentration of a part close to the lower surface of the P/N thin layer is lower than the concentration of P type impurities required by charge balance; and the maximum concentration variation gradients of the part close to the lower surface of the P/N thin layer is higher than that of the part close to the upper surface of the P/N thin layer. The invention further discloses a manufacturing method of the super junction semiconductor device. According to the invention, the uniformity of the reverse breakdown voltage of the device and the reliability of the device can be enhanced.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of super junction-semiconductor device.The invention still further relates to a kind of manufacture method of super junction-semiconductor device.
Background technology
The device of super-junction structures replaces the N drift region in traditional VDMOS (vertical double-diffused MOS transistor) by the structure of utilizing P/N to replace assortment.It,, in conjunction with the VDMOS technique of knowing in the industry, just can make the MOSFET (metal oxide semiconductor field effect tube) that obtains super-junction structures; It can, in the case of reverse breakdown voltage is consistent with traditional VDMOS, by using the epitaxial loayer of low-resistivity, significantly reduce the conducting resistance of device.In P/N semiconductor lamella, the charge carrier distribution of the distribution of the charge carrier of N-type impurity and p type impurity and their coupling can affect the characteristic of device, comprise reverse breakdown voltage and current handling capability.
In general device design, all adopt the charge balance that reaches best in the P/N semiconductor lamella that makes to replace to obtain the maximum reverse breakdown voltage of device, but under such condition, the reverse breakdown of device may occur in N district and also may occur in P district, and from the requirement of current handling capability and the reliability of device, wish that the reverse breakdown of device occurs in the N+ substrate region of the close device in P district.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of super junction-semiconductor device, can improve the uniformity of device reverse breakdown voltage and the reliability of device; For this reason, the present invention also will provide a kind of manufacture method of super junction-semiconductor device.
For solving the problems of the technologies described above, super junction-semiconductor device of the present invention is to adopt following technical scheme to realize:
On N+ silicon substrate, there is P type and the N type semiconductor laminate structure of alternative arrangement, wherein, p type impurity concentration changes perpendicular to N+ silicon substrate direction on edge, the concentration of the impurity concentration that is distributed in the part that approaches P/N semiconductor lamella upper surface of p type impurity required p type impurity during higher than charge balance, the concentration of the impurity concentration of part that approaches P/N semiconductor lamella lower surface required p type impurity during lower than charge balance; The Cmax variable gradient that approaches P/N semiconductor lamella bottom surface section is greater than the Cmax variable gradient of the part that approaches P/N thin layer upper surface.
The p type impurity concentration of mid portion can be also can not changing of changing, when the p type impurity concentration of mid portion be change time, the Cmax variable gradient that approaches P/N semiconductor lamella bottom surface section is greater than the Cmax variable gradient of the p type impurity of mid portion.
The described upper surface portion that approaches refers to from upper surface and plays the part that the degree of depth is less than total p type impurity degree of depth 1/4; The described bottom surface section that approaches refers to from lower surface and plays the part that the degree of depth is less than total p type impurity degree of depth 1/4; Described mid portion refers in p type impurity and approaches upper surface portion and approach the part between upper surface portion above-mentioned.
The width of described P type semiconductor thin layer is less than or equal to the width of N type semiconductor thin layer.
The manufacture method of super junction-semiconductor device of the present invention is to adopt following technical scheme to realize, and forms P type and the N type semiconductor thin layer of alternative arrangement on N+ silicon substrate, wherein:
85% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of bottom ground floor reaches optimum balance lower than the N type semiconductor thin layer impurity concentration that makes same level position; 105% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of the bottom second layer equals to make the N type semiconductor thin layer impurity concentration of same level position to reach optimum balance; 115% of P type semiconductor thin layer impurity concentration when the P type semiconductor thin layer impurity concentration of top ground floor equals to make the N type semiconductor thin layer impurity concentration of same level position to reach optimum balance; P type impurity concentration when the P type semiconductor thin layer impurity concentration of the top second layer equals to make the N type semiconductor thin layer impurity concentration of same level position to reach optimum balance.
The 90%-110% of the P type semiconductor thin layer impurity concentration when P type semiconductor thin layer impurity concentration in intermediate layer equals to make the N-type impurity concentration of same level position to reach optimum balance.
The present invention adopts the impurities concentration distribution mode of non-uniform Distribution to realize the P/N semiconductor lamella of alternative arrangement, wherein, by the design of impurities concentration distribution inhomogeneous in P type semiconductor thin layer, make the reverse breakdown of device occur in P district, and can in the processing range of producing, make reverse breakdown occur in the region of the close N+ silicon substrate in P district, improve the large current handling capability (EAS) of device, the electric field strength of maximum while reducing the generation of device reverse breakdown, improve the reliability of device, reduce the sensitivity that device reverse breakdown voltage changes impurity concentration, improve the rate of finished products of device.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1-2 is the schematic flow sheet of embodiment of the method one of the present invention;
Fig. 3 is by the final super junction nmos device cellular construction schematic diagram forming of embodiment mono-;
Fig. 4-5th, the schematic flow sheet of embodiment of the method two of the present invention;
Fig. 6 is by the final super junction nmos device cellular construction schematic diagram forming of embodiment bis-;
Fig. 7 is the impurities concentration distribution schematic diagram adopting in the P/N thin layer that obtains of method of the present invention;
Fig. 8 is that p type impurity concentration edge is uniformly distributed perpendicular to N+ silicon substrate direction, under different p type impurity concentration, and electric field distribution map vertically in N type semiconductor thin layer when reverse breakdown occurs;
Fig. 9 is p type impurity concentration when being uniformly distributed perpendicular to N+ silicon substrate direction, under different p type impurity concentration, and electric field distribution map vertically in P type semiconductor thin layer when reverse breakdown occurs;
Figure 10 is that p type impurity concentration edge is that in situation about changing, several p type impurity concentration are along the distribution map (after whole thermal processs) perpendicular to N+ silicon substrate direction perpendicular to N+ silicon substrate direction;
Figure 11 be p type impurity concentration by the distribution shown in Figure 10, electric field distribution map vertically in N type semiconductor thin layer when reverse breakdown occurs;
Figure 12 be p type impurity concentration by the distribution shown in Figure 10, electric field distribution map vertically in P type semiconductor thin layer when reverse breakdown occurs;
Figure 13 occurs near near N+ silicon substrate time (p type impurity concentration is greater than 2.1E15/CM3) at reverse breakdown, the graph of a relation of puncture voltage and the variation of impurity concentration central value under the uniform P type semiconductor thin layer of impurity concentration and two kinds of conditions of P type semiconductor thin layer heterogeneous.
Embodiment
The device that is 600V for reverse breakdown voltage is in the following embodiments specifically described, N-type impurity concentration used is C2=1E15/CM3, in each P/N semiconductor lamella unit, the width D 2 of N type semiconductor thin layer is 12 microns, the width D 1 of P type semiconductor thin layer is 5 microns, and the best p type impurity concentration that reaches charge balance is that C2* (D2/D1) is 2.4E15/CM3.
Embodiment mono-
Described N-epitaxial loayer can be grown on described N+ silicon substrate, also can be grown on the N-epitaxial buffer layer being positioned on N+ silicon substrate.
Process in step 2, repeating step one (is that N-epitaxial loayer 2 is grown, form the figure of p type island region opening, P type Implantation), reach after the thickness needing, pass through again the annealing of high temperature thermal process and push away trap, just can obtain P type semiconductor thin layer and the N type semiconductor thin layer of alternative arrangement, as shown in Figure 2.In Fig. 2, the different p type impurity concentration of diverse location can obtain by different Implantations.In order to obtain uniform impurity concentration in a region, the injection after a photoetching can adopt the repeatedly injection of different-energy; The mode that also can reduce each epitaxially grown thickness (but need increase the number of times of total epitaxial growth-photoetching-P type Implantation) realizes.
Shown in Fig. 3, after above technological process, obtain the distribution of such p type impurity concentration: 85% of the p type impurity concentration when p type island region 52-1 impurity concentration of bottom ground floor reaches optimum balance lower than the N-type impurity concentration that makes same level position; 105% of p type impurity concentration when the p type island region 52-2 impurity concentration of the bottom second layer equals to make the N-type impurity concentration of same level position to reach optimum balance; The 90%-110% (not shown in the figures, intermediate layer can have, and also can not have) of the p type impurity concentration when p type island region impurity concentration in intermediate layer equals to make the N-type impurity concentration of same level position to reach optimum balance; 115% of p type impurity concentration when the p type island region 52-4 impurity concentration of top ground floor equals to make the N-type impurity concentration of same level position to reach optimum balance; P type impurity concentration when the p type island region impurity concentration of top second layer 52-3 equals to make the N-type impurity of same level position to reach optimum balance.
Shown in Fig. 3, afterwards, utilize ripe VDMOS processing technology to obtain corresponding super junction NMOS (N NMOS N-channel MOS N) device unit construction, comprise: the gate oxidation films 5 and the polysilicon electrode 6 that are positioned at N-epitaxial loayer 2 upper ends, be positioned at the P trap 7 on N-epitaxial loayer 2 and P type thin layer top, be arranged in the N+ source 8 of P trap 7, the inter-level dielectric film 9 of coated described polysilicon electrode 6, be arranged in the source metal electrode 12 of contact hole 10 and inter-level dielectric film 9 tops, in the middle of the contact hole and be positioned at the P+ contact implanted layer 11 on P type thin layer top, the polycrystalline electrodes (not shown) that polysilicon gate 6 is drawn, be positioned at the drain electrode 14 (back metal) of N+ silicon substrate 1 lower surface.
Embodiment bis-
The sidewall of described groove 41 can be vertical, also can tilt.The bottom of described groove 41 can be smooth, also can have crooked radian.
Described silicon oxide film 31 can obtain by thermal oxidation, also can realize by chemical vapor deposition (CVD).During etching groove, can be to utilize silicon oxide film 31 as mask, also can utilize photoresist as mask, the thickness of the silicon oxide film 31 after etching be advised more than 1000 dusts.
Shown in Fig. 6, the impurity in the P type silicon is here used for the N-type impurity of the N type semiconductor thin layer that balance is adjacent and has feature below: 85% of the p type impurity concentration when impurity concentration of the p type island region 42-1 of first area, bottom reaches optimum balance lower than the N-type impurity concentration that makes same level position; 105% of p type impurity concentration when the impurity concentration of p type island region 42-2 of bottom second area equals to make the N-type impurity concentration of same level position to reach optimum balance; The 90-110% (not shown in the figures, zone line can have, and also can not have) of the p type impurity concentration when impurity concentration of the p type island region of zone line equals to make the N-type impurity of same level position to reach optimum balance; 115% of p type impurity concentration when the impurity concentration of the p type island region 42-1/ of first area, top equals to make the N-type impurity concentration of same level position to reach optimum balance; P type impurity concentration when the impurity concentration of the p type island region in 42-2/ territory, Second Region, top equals to make the N-type impurity concentration of same level position to reach optimum balance.
Described P type silicon can be monocrystalline silicon, polysilicon or indefinite form silicon.The growth temperature of p type single crystal silicon can be 650 ℃ to 1200 ℃, and the growth temperature of P type polysilicon can be 580 ℃ to 650 ℃, and the growth temperature of P type indefinite form silicon can be 510 ℃ to 579 ℃.In the present embodiment, what in groove 41, fill is all P type silicon, utilizes cmp or returns to carve the P type silicon on groove 41 surfaces is removed; And silicon oxide film 31 is removed, just obtained the P type of alternative arrangement and the structure of N type semiconductor thin layer;
Shown in Fig. 6, afterwards, utilize ripe VDMOS processing technology to obtain corresponding super junction NMOS (N NMOS N-channel MOS N) device unit construction, comprise: the gate oxidation films 5 and the polysilicon electrode 6 that are positioned at N-epitaxial loayer 2 upper ends, be positioned at the P trap 7 on N-extension and P type thin layer top, be arranged in the N+ source 8 of P trap 7, the inter-level dielectric film 9 of coated described polysilicon electrode 6, be arranged in the source metal electrode 12 of contact hole 10 and inter-level dielectric film 9 tops, in the middle of the contact hole and be positioned at the P+ contact implanted layer 11 on P type thin layer top, the polycrystalline electrodes (not shown) that polysilicon gate 6 is drawn, be positioned at the drain electrode 14 (back metal) of N+ silicon substrate 1 lower surface.
In Fig. 3 and 6, A represents the position of tying between N type semiconductor in P trap 7 and N-epitaxial loayer 2 regions, and B represents the position of tying between P type semiconductor and N type semiconductor in P type semiconductor coating region.
Fig. 7 is the impurities concentration distribution schematic diagram in the P/N thin layer that obtains of the above-mentioned two kinds of embodiment of above-mentioned employing, wherein, in N-type thin layer, impurity concentration is evenly constant, in P type thin layer, impurity concentration is being the highest close to device front, is greater than the p type impurity concentration while making the N-type impurity of same level position reach best charge balance; In the region that approaches N+ silicon substrate 1 most, be minimum, be less than the p type impurity concentration while making the N-type impurity of same level position reach best charge balance; And, at the variable gradient of the p type island region impurity concentration in the positive region of proximity device, be less than the region that approaches N+ silicon substrate 1.
For implementing two, after thermal process below, p type impurity concentration in the distribution perpendicular in N+ silicon substrate 1 direction as shown in Figure 8, here the thickness of total N-epitaxial loayer 2 is 45 microns, the degree of depth of groove 41 is 40 microns, and the distance between the bottom of groove 41 and the top of N+ silicon substrate 1 is 5 microns.In Fig. 8, coordinate 0 place is the top of N+ silicon substrate 1, and-45 microns of places are N-epitaxial loayer 2 positive tops at device.
For p type island region impurity concentration, be equally distributed situation in the vertical direction, to different p type impurity concentration (1.3E15/CM3; 1.7E15/CM3; 2.1E15/CM3; 2.5E15/CM3; 2.9E15/CM3; Situation 3.3E15/CM3) has been carried out TCAD (Computer-aided Design Technology) simulation, what obtain punctures the maximum field point in HeNXing district, p type island region while occurring, and the size of the total electric field from this point along the direction perpendicular to N+ silicon substrate 1 is as shown in Fig. 8 (N district) and Fig. 9 (in P district).From figure, see, when p type impurity concentration is less than 2.1E15/CM3, punctures and occur in the position of device close to upper surface; When p type impurity concentration be greater than or etc. during 2.5E15/CM3, puncture and occur in the position of device close to N+ silicon substrate 1.
For p type island region impurity concentration, be the situation of uneven distribution in the vertical direction, get the impurity concentration C1=C*85%*D2/D1 of the one 1/4 caliper zones, bottom (as the 42-1 in Fig. 5), the impurity concentration C2=C*105%*D2/D1 of the 2 1/4 caliper zones, bottom (as the 42-2 in Fig. 5), the impurity concentration C2 '=C*115% × D2/D1 of the one 1/4 caliper zones, top (as the 42/-1 in Fig. 5), impurity concentration the C1 '=C*D2/D1 of the 2 1/4 caliper zones, top (as the 42/-2 in Fig. 5); To several different impurity concentration C (1.3E15/CM3; 1.7E15/CM3; 2.1E15/CM3; 2.5E15/CM3; 2.9E15/CM3; Situation 3.3E15/CM3), as shown in figure 10, in figure, coordinate 0 place is the top of N+ silicon substrate 1 to the distribution vertically of the p type impurity concentration after the thermal process needing through technique ,-45 microns of places are N-epitaxial loayer 2 positive tops at device.The situation of different p type impurity concentration has been carried out to TCAD simulation, what obtain punctures the maximum field point in HeNXing district, p type island region while occurring, and the size of the total electric field from this point along the direction perpendicular to N+ silicon substrate 1 is as shown in Figure 11 (N district) and Figure 12 (in P district); The centre concentration of the p type impurity here refers to the value of C1 ' is displaced to the value shown in figure from best C*D2/D1; From figure, see, when p type impurity concentration is less than 2.1E15/CM3, punctures and occur in the position of device close to upper surface; When p type impurity concentration be greater than or etc. during 2.5E15/CM3, puncture and occur in the position of device close to n+ substrate.
Data to the maximum field in two kinds of situations above contrast, obtain the data of following table 1, from table 1, see, basically identical with respect to the electric field maximum in N-type thin layer in situation in two, in P type thin layer, maximum field in non-homogeneous situation is less than the maximum field under being uniformly distributed, and occurs in P type thin layer the current handling capability and the reliability that improves device that reduce to improve device of this electric field owing to puncturing.
Table 1
Further, in order to improve the current handling capability of device, preferably make the occurrence positions puncturing not only in P type thin layer, and in approaching the position of N+ silicon substrate 1, puncture the electronics of the secondary electron-hole centering producing while occurring very soon for N+ silicon substrate 1 (high positive voltage) absorbs, the puncture voltage of device is not affected; During move toward the P+ contact hole of top device in the hole producing, because its top that will arrive is that negative fixed charge quantity is greater than desirable quantity when puncturing firm generation, the arrival in this hole has reduced this species diversity improves the puncture voltage of device, formed the negative feedback of puncture voltage and number of cavities, be conducive to reduce follow-up secondary electron-hole pair, improved the current handling capability of device; So wish the centre concentration of P type thin layer to use and be greater than 2.1E15/CM3;
Utilize TCAD to simulate, obtain in the situation of even and non-uniform doping, the relation that the puncture voltage of device and impurity concentration central value change, as shown in figure 13; As we can see from the figure, the in the situation that of non-homogeneous CONCENTRATION DISTRIBUTION, for same p type impurity change in concentration scope, little when even of the excursion of puncture voltage, has improved the stability of device electric breakdown strength.
In theory, impurities concentration distribution inhomogeneous in N-type thin layer also can have the similar effect of above-described embodiment, but the requirement of N impurities concentration distribution is different with above-described embodiment.
Owing to can making the impurity concentration in P type and N type semiconductor thin layer have a kind of impurity concentration at least along being inhomogeneous perpendicular to the distribution in the direction of N+ silicon substrate, can improve the uniformity of device reverse breakdown voltage and the reliability of device.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (13)
1. a super junction-semiconductor device, on N+ silicon substrate, there is P type and the N type semiconductor laminate structure of alternative arrangement, it is characterized in that: p type impurity concentration changes perpendicular to N+ silicon substrate direction on edge, the concentration of the impurity concentration that is distributed in the part that approaches P/N semiconductor lamella upper surface of p type impurity required p type impurity during higher than charge balance, the concentration of the impurity concentration of part that approaches P/N semiconductor lamella lower surface required p type impurity during lower than charge balance; The Cmax variable gradient that approaches the part of P/N semiconductor lamella lower surface is greater than the Cmax variable gradient of the part that approaches P/N semiconductor lamella upper surface; The p type impurity concentration of P/N semiconductor lamella mid portion can be also can not changing of changing, when the p type impurity concentration of mid portion be change time, the Cmax variable gradient that approaches P/N semiconductor lamella bottom surface section is greater than the Cmax variable gradient of the p type impurity of mid portion.
2. device as claimed in claim 1, is characterized in that: the described upper surface portion that approaches refers to from upper surface and plays the part that the degree of depth is less than total p type impurity degree of depth 1/4; The described bottom surface section that approaches refers to from lower surface and plays the part that the degree of depth is less than total p type impurity degree of depth 1/4; Described mid portion refers in p type impurity and approaches upper surface portion and approach the part between bottom surface section above-mentioned.
3. device as claimed in claim 1, is characterized in that: the width of P type semiconductor thin layer is less than or equal to the width of N type semiconductor thin layer.
4. a manufacture method for super junction-semiconductor device forms P type and the N type semiconductor thin layer of alternative arrangement on N+ silicon substrate, it is characterized in that:
85% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of bottom ground floor reaches optimum balance lower than the N type semiconductor thin layer impurity concentration that makes same level position; 105% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of the bottom second layer equals to make the N type semiconductor thin layer impurity concentration of same level position to reach optimum balance; 115% of P type semiconductor thin layer impurity concentration when the P type semiconductor thin layer impurity concentration of top ground floor equals to make the N type semiconductor thin layer impurity concentration of same level position to reach optimum balance; P type impurity concentration when the P type semiconductor thin layer impurity concentration of the top second layer equals to make the N type semiconductor thin layer impurity concentration of same level position to reach optimum balance.
5. manufacture method as claimed in claim 4, is characterized in that: the 90%-110% of the P type semiconductor thin layer impurity concentration when P type semiconductor thin layer impurity concentration in intermediate layer equals to make the N-type impurity concentration of same level position to reach optimum balance.
6. manufacture method as claimed in claim 4, is characterized in that, the P type of described alternative arrangement and N type semiconductor thin layer are adopted with the following method and obtained:
Step 1, on N+ silicon substrate growth regulation one deck N-epitaxial loayer;
Step 2, the P type semiconductor coating region that utilizes photoetching to open will to inject carry out P type Implantation;
Step 3, repetition above-mentioned steps obtain P type and the N type semiconductor thin layer of the alternative arrangement that needs thickness.
7. manufacture method as claimed in claim 6, is characterized in that: the N-of ground floor described in step 1 epitaxial loayer can be grown on described N+ silicon substrate, also can be grown on the N-epitaxial buffer layer being positioned on N+ silicon substrate.
8. manufacture method as claimed in claim 4, is characterized in that, the P type of described alternative arrangement and N type semiconductor thin layer are adopted with the following method and obtained:
Step 1, the N-epitaxial loayer of growing on N+ silicon substrate, then form deielectric-coating on this N-epitaxial loayer, utilize chemical wet etching to form groove;
Step 2, in described groove, fill P type silicon, or P type silicon adds medium, or P type silicon adds plain silicon, and fill up this groove, form P type semiconductor thin layer;
Step 3, utilize back and carve or cmp is removed the P type semiconductor thin layer of described flute surfaces and deielectric-coating.
9. manufacture method as claimed in claim 8, is characterized in that: the type of P described in step 2 silicon, the temperature of growth is 650 ℃-1200 ℃.
10. manufacture method as claimed in claim 8, is characterized in that: the type of P described in step 2 silicon is monocrystalline silicon, polysilicon or unformed silicon.
11. manufacture methods as claimed in claim 8, is characterized in that: the sidewall of groove described in step 1 can be vertical, also can tilt.
12. manufacture methods as claimed in claim 8, is characterized in that: the bottom of groove described in step 1 can be smooth, also can have crooked radian.
13. manufacture methods as claimed in claim 8, is characterized in that: groove described in step 1 can penetrate described N-epitaxial loayer, also can be parked in N-epitaxial loayer.
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| CN102760647B (en) * | 2012-07-26 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Super junction power device manufacture method and method, semi-conductor device manufacturing method |
| CN103050523B (en) * | 2012-12-14 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Insulated gate bipolar transistor and manufacture method thereof |
| CN105097932B (en) * | 2014-12-26 | 2019-02-26 | 杭州士兰微电子股份有限公司 | High voltage power device and forming method thereof |
| CN104733535A (en) * | 2015-03-17 | 2015-06-24 | 北京中科新微特科技开发股份有限公司 | Power MOSFET |
| CN106158642A (en) * | 2015-04-08 | 2016-11-23 | 北大方正集团有限公司 | The manufacture method of MOSFET element and MOSFET element |
| CN112117330B (en) * | 2020-09-21 | 2024-05-07 | 南京华瑞微集成电路有限公司 | Device structure for improving withstand voltage of deep-groove super-junction MOSFET and process method thereof |
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