CN116666456B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN116666456B CN116666456B CN202310953302.XA CN202310953302A CN116666456B CN 116666456 B CN116666456 B CN 116666456B CN 202310953302 A CN202310953302 A CN 202310953302A CN 116666456 B CN116666456 B CN 116666456B
- Authority
- CN
- China
- Prior art keywords
- region
- oxide layer
- substrate
- drain drift
- drift region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 210000000746 body region Anatomy 0.000 claims abstract description 65
- 150000002500 ions Chemical class 0.000 claims description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 230000007423 decrease Effects 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 135
- 230000005684 electric field Effects 0.000 description 22
- 229910021332 silicide Inorganic materials 0.000 description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 22
- 238000000151 deposition Methods 0.000 description 15
- 238000002955 isolation Methods 0.000 description 15
- 230000008021 deposition Effects 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 10
- -1 boron ion Chemical class 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005685 electric field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910010093 LiAlO Inorganic materials 0.000 description 1
- 238000005481 NMR spectroscopy Methods 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- YQNQTEBHHUSESQ-UHFFFAOYSA-N lithium aluminate Chemical compound [Li+].[O-][Al]=O YQNQTEBHHUSESQ-UHFFFAOYSA-N 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application relates to the technical field of semiconductor manufacturing, and discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device at least comprises: a substrate; a source body region disposed in the substrate; the drain drift region is arranged in the substrate, is arranged side by side with the source body region, and reduces the ion doping concentration of the drain drift region from the direction away from the source body region to the direction close to the source body region; the field oxide layer is arranged on the substrate and covers part of the drain drift region; and the grid electrode structure is arranged on the source electrode body region and covers part of the field oxide layer. The application provides a semiconductor device and a manufacturing method thereof, which can improve the stability and the electrical property of the device.
Description
Technical Field
The present application relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
High voltage laterally diffused metal oxide semiconductors (Laterally Diffused Metal Oxide Semiconductor, LDMOS) are often used in high voltage power integrated circuits to meet high voltage and power control requirements, and are often used in radio frequency power circuits.
In an LDMOS device, breakdown voltage is an important parameter for measuring the performance of the device, and higher breakdown voltage is beneficial to guaranteeing the stability of the device in actual operation. The ion implantation step for forming the drift region is complex, and the breakdown voltage of the LDMOS device can be directly influenced by improper ion implantation, so that the device performance is influenced.
Disclosure of Invention
The application aims to provide a semiconductor device and a manufacturing method thereof, which can improve the stability and the electrical performance of the device.
In order to solve the technical problems, the application is realized by the following technical scheme:
the present application provides a semiconductor device including at least:
a substrate;
a source body region disposed in the substrate;
the drain drift region is arranged in the substrate, is arranged side by side with the source electrode body region, and has ion doping concentration decreasing from the direction away from the source electrode body region to the direction close to the source electrode body region;
a field oxide layer disposed on the substrate, wherein the field oxide layer covers a part of the drain drift region;
and the grid electrode structure is arranged on the source electrode body region and covers part of the field oxide layer.
Further, a first type doped region is disposed in the drain drift region and the source body region, the first type doped region being located on a side of the drain drift region away from the source body region and on a side of the source body region away from the drain drift region.
Further, the gate structure comprises a gate oxide layer, wherein the gate oxide layer covers part of the source electrode body region, one side of the gate oxide layer is connected to the field oxide layer, and the other side of the gate oxide layer extends to the first type doped region.
Further, the gate structure comprises a polysilicon layer covering the gate oxide layer and a portion of the field oxide layer, wherein the polysilicon layer is connected to a sidewall and a portion of a top surface of the field oxide layer.
Further, a second type doped region is disposed in the source body region, the second type doped region is adjacent to the first type doped region, and the first type doped region is located between the second type doped region and the drain drift region.
Further, the doping type of the first type doping region is the same as the doping type of the drain drift region, and the doping type of the second type doping region is the same as the doping type of the source body region.
Further, a buried oxide layer is arranged in the substrate, the buried oxide layer is arranged at the bottom of the drain drift region, and the buried oxide layer is connected with the interface of the drain drift region.
Further, an island doped region is arranged in the drain drift region, the island doped region is located between the buried oxide layer and the first type doped region, the island doped region is in contact with the buried oxide layer, and orthographic projection of the island doped region on the buried oxide layer is located in the region of the buried oxide layer.
Further, the doping concentration of the island doping region is greater than the doping concentration of the drain drift region, and the doping concentration of the island doping region is less than the doping concentration of the first type doping region.
The application provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, implanting second type ions into the substrate, and forming a drain drift region;
implanting first type ions into the substrate to form a source electrode body region, wherein the drain electrode drift region and the source electrode body region are arranged side by side, and the ion doping concentration of the drain electrode drift region decreases from the direction away from the source electrode body region to the direction close to the source electrode body region;
forming a field oxide layer on the substrate, wherein the field oxide layer covers part of the drain drift region; and
and forming a gate structure on the source electrode body region, wherein the gate structure covers part of the field oxide layer.
Further, before forming the drain drift region, a photoresist pattern is arranged on the substrate, and the width of an etching window of the photoresist pattern increases gradually along the direction approaching to the source electrode body region.
As described above, the present application provides a semiconductor device and a method for manufacturing the same, and the unexpected technical effects of the present application are: the surface electric field of the semiconductor device is uniformly distributed, the breakdown voltage is high, and the working stability of the semiconductor device is good; in addition, the semiconductor device provided by the application can reduce the voltage of the electric fields at the two ends of the drift region and improve the voltage of the electric field in the center of the drift region, so that the stability of the semiconductor device is improved; according to the manufacturing method of the semiconductor device, the drift region with uniform electric field distribution can be formed only through one step, the process cost is low, and the doping of the formed drift region can be linearly distributed, so that the breakdown voltage of the semiconductor device is improved.
Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic cross-sectional view of a substrate and buried oxide layer according to an embodiment of the present application.
FIG. 2 is a schematic cross-sectional view of a first photoresist pattern and an island doped region according to an embodiment of the present application.
Fig. 3 is a schematic top view of a first photoresist pattern and a drain drift region according to an embodiment of the application.
Fig. 4 is a schematic top view of a first photoresist pattern and a drain drift region according to another embodiment of the present application.
Fig. 5 is a schematic top view of a first photoresist pattern and a drain drift region according to another embodiment of the present application.
Fig. 6 is a schematic cross-sectional view illustrating ion implantation at AA' to form a drain drift region according to an embodiment of the present application.
Fig. 7 is a schematic cross-sectional structure of a drain drift region formed by ion implantation at BB' in an embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of a drain drift region according to an embodiment of the present application.
Fig. 9 is a schematic cross-sectional view of a source body according to an embodiment of the application.
FIG. 10 is a schematic cross-sectional view of an oxygen layer according to an embodiment of the present application.
Fig. 11 is a schematic cross-sectional structure of forming a gate oxide layer according to an embodiment of the application.
Fig. 12 is a schematic cross-sectional view of a deposited polysilicon according to an embodiment of the application.
Fig. 13 is a schematic cross-sectional view illustrating formation of a polysilicon layer according to an embodiment of the present application.
Fig. 14 is a schematic cross-sectional structure of a first type doped region and a second type doped region according to an embodiment of the present application.
Fig. 15 is a schematic cross-sectional view of a silicide layer according to an embodiment of the present application.
FIG. 16 is a schematic cross-sectional view of a deposition channel formed by etching a dielectric layer according to an embodiment of the present application.
Fig. 17 is a schematic cross-sectional view of a contact post formed in accordance with an embodiment of the present application.
Fig. 18 is a schematic diagram showing the distribution of ion concentration at the cross section of the drain drift region in an embodiment of the present application.
Fig. 19 is a schematic diagram showing the surface electric field distribution at the cross section of the drain drift region of the comparison group according to an embodiment of the present application.
In the figure: 100. a substrate; 101. shallow trench isolation structure; 102. burying an oxide layer; 103. an island doped region; 104. a drain drift region; 105. a source body region; 106. a first type doped region; 106a, a drain first doped region; 106b, a source first doped region; 107. a second type doped region; 200. a first photoresist pattern; 201. etching the window; 300. a second photoresist pattern; 400. a field oxide layer; 401. a third photoresist pattern; 500. a gate oxide layer; 501. a fourth photoresist pattern; 600. a polysilicon layer; 700. a silicide layer; 700a, a gate silicide layer; 700b, a source drain silicide layer; 800. a dielectric layer; 801. a deposition channel; 900. and (5) a contact post.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The LDMOS device is a new-generation integrated solid microwave power semiconductor product formed by combining a semiconductor integrated circuit technology and a microwave electronic technology, has the advantages of good linearity, high gain, high voltage endurance, high output power, good thermal stability, high efficiency, good broadband matching performance, easiness in integration with MOS technology and the like, and the price of the LDMOS is far lower than that of a gallium arsenide device, so that the LDMOS device is a very competitive power device. The semiconductor device provided by the application can be an LDMOS device, and can be widely applied to power amplifiers of base stations such as a global system for mobile communication (Global System of Mobile munication, GSM), wideband code division multiple access (Wide band Code Division Multiple Access, W-CDMA) and the like, and wireless broadcasting, nuclear magnetic resonance and the like.
Referring to fig. 1, the present application provides a method for manufacturing a semiconductor device, which comprises providing a substrate 100, and forming a shallow trench isolation structure 101 in the substrate 100. The substrate 100 is, for example, a silicon substrate forming the semiconductor device. The substrate 100 may include a base material, such as silicon (Si), silicon carbide (SiC), sapphire (Al), and a silicon layer disposed over the base material 2 O 3 ) Gallium arsenide (GaAs), lithium aluminate (LiAlO) 2 ) And a silicon layer formed over the base material. The application is not limited to the material and thickness of the substrate 100. In this embodiment, a first type of ion may be implanted in the substrate 100, and the first type of ion may be boron ion to form a P-type semiconductor. A plurality of shallow trench isolation structures 101 are then formed in the substrate 100 by a shallow trench isolation process (Shallow Trench Isolation, STI). The shallow trench isolation structure 101 divides the substrate 100 into a plurality of active regions.
Referring to fig. 1, in an embodiment of the present application, after forming a shallow trench isolation structure 101 in a substrate 100, a buried oxide layer 102 is formed in the substrate 100. Specifically, oxygen ions are implanted into the active region to form the buried oxide layer 102. The buried oxide layer 102 may reduce the surface electric field of the substrate 100, and the buried oxide layer 102 may share a voltage in a vertical direction, thereby being advantageous for improving a breakdown voltage of the semiconductor device. Wherein the vertical direction is a direction perpendicular to the surface of the substrate 100. In this embodiment, the length of the buried oxide layer 102 may be, for example, 20 μm to 50 μm. The thickness of the buried oxide layer 102 may be, for example, 2.5 μm to 3 μm, and may specifically be, for example, 3 μm. In the present embodiment, the buried oxide layer 102 is disposed in the substrate 100, and a buried distance is provided between the top surface of the buried oxide layer 102 and the top surface of the substrate 100. In this embodiment, the buried distance may be, for example, 4 μm to 5 μm, and may specifically be, for example, 5 μm. In this embodiment, the buried depth of the buried oxide layer 102 is greater than the depth of the shallow trench isolation structure 101, and in particular, the bottom surface of the shallow trench isolation structure 101 may extend to the top surface of the buried oxide layer 102. In this embodiment, the depth of the shallow trench isolation structure 101 may be, for example, 4 μm to 5 μm.
Referring to fig. 1 and 2, in an embodiment of the present application, after forming a buried oxide layer 102 in a substrate 100, an island doped region 103 is formed in the substrate 100. Specifically, a second type of ion is vertically implanted into the active region to form an island doped region 103. Wherein the second type of ions may be phosphorus ions and the doping concentration of the phosphorus ions may be, for example, 1×10 16 cm -3 ~9×10 16 cm -3 . The projection of the island doped region 103 in the vertical direction, which is a direction perpendicular to the surface of the substrate 100, is located within the buried oxide layer 102. The length of the island doped region 103 is, for example, 1/5 to 1 time the length of the buried oxide layer 102. Specifically, the length of the island doped region 103 may be, for example, 10 μm to 20 μm. In this embodiment, the thickness of the island doped region 103 may be, for example, 0.1 μm to 0.5 μm, and the interface of the island doped region 103 is connected to the buried oxide layer 102. The semiconductor device has a surface electric field effect in operation. Specifically, under the action of an applied electric field, the space charge region, the surface potential, the band bending and the carrier concentration in the semiconductor surface layer all change with the applied electric field. The island doped region 103 can adjust the surface electric field distribution of the semiconductor device, thereby reducing the surface electric field effect and improving the electrical efficiency of the semiconductor device.
Referring to fig. 2 to 5, in an embodiment of the present application, after forming an island doped region 103 in an active region, a drain drift region 104 is formed in a substrate 100. Specifically, photoresist is spin-coated on the substrate 100 to form a first photoresist layer, and the first photoresist layer is patterned by means of exposure etching or the like to form a first photoresist pattern 200. Wherein the first photoresist pattern 200 includes an etching window 201. Wherein the active region is disposed in the coverage of the etch window 201. Specifically, the length of the etching window 201 is equal to the length of the active region, and the width of the etching window 201 is larger than the width of the active regionDegree. On the extension line of the drain drift region 104, and in the direction away from the island doped region 103, the width of the etching window 201 gradually decreases, and as shown in fig. 3 to 5, the minimum distance between the edge of the etching window 201 and the edge of the active region is the first distance D 1 . The maximum distance between the edge of the etched window 201 and the edge of the active region is the second distance D 4 . Wherein D is 1 ＜D 4 . As shown in fig. 3 to 5, in the etching window 201, at the AA' section line, the distance between the edge line of the etching window 201 and the edge of the active region is D 2 . In the etching window 201, at the BB' section line, the distance between the edge line of the etching window 201 and the edge of the active region is D 3 . In the present embodiment, D 1 ＜D 2 ＜D 3 ＜D 4 。
Referring to fig. 2 to 5, in an embodiment of the application, as shown in fig. 3, the etching window 201 may be trapezoidal, and a width of an end of the etching window 201 near the island doped region 103 is smaller than a width of an end far from the island doped region 103. In another embodiment of the present application, as shown in fig. 4, the etching window 201 may be a combination of multi-segment lines to more finely control the ion concentration gradient in the drain drift region 104. And the slope of the edge of the etching window 201 gradually decreases in a direction away from the island doped region 103 on the extension line of the drain drift region 104 with the horizontal line as a slope reference line. The edge of the etch window 201 as shown in fig. 4 includes, for example, 2 straight lines. And, with the horizontal line as a reference line, the slope of the straight line near the island doping region 103 is larger than the slope of the straight line far from the island doping region 103. In yet another embodiment of the present application, as shown in fig. 5, the edge line of the etching window 201 may be an arc line, and the width of the etching window 201 at the end near the island doping region 103 is smaller than the width at the end far from the island doping region 103. In other embodiments of the present application, the edge line of the etching window 201 may be a multi-segment arc. The shape of the edge line of the etching window 201 is a design shape, and the present application is not limited to the actual shape of the first photoresist pattern 200.
Referring to fig. 3 to 7, in an embodiment of the present application, a second type of ion is implanted into the substrate 100 to form a drain drift region 104. Wherein the second type of ions may be phosphorous ions. In this embodiment, the second type ions are implanted into the active region according to a preset tilt angle. The preset inclination angle is an included angle between the ion implantation direction and the normal line of the substrate 100, and as shown in fig. 6 and 7, the preset inclination angle is α. In this embodiment, the preset inclination angle is, for example, 2 ° to 10 °. Fig. 6 is a cross-sectional view of the semiconductor device at AA'. The second ions are implanted into the active region through the etched window 201, forming a drain drift region 104 within the active region, the drain drift region 104 being an N-doped region. At the AA' section, part of the second ions are implanted directly into the active region. Part of the second ions contacts the surface of the first photoresist pattern 200 and is implanted into the active region by reflection of the first photoresist pattern 200. In this embodiment, the thickness of the first photoresist pattern 200 may be, for example, 4 μm to 5 μm. The minimum distance between the edge of the etching window 201 and the drain drift region 104 is, for example, 20nm to 50nm. The maximum distance between the edge of the etching window 201 and the drain drift region 104 is, for example, 500nm to 1000nm.
Referring to fig. 3-7, fig. 7 is a cross-sectional view of a semiconductor device at BB' in an embodiment of the present application. At the BB ' section, part of the second ions are directly injected into the active region, and the concentration of the second ions which are directly injected into the active region at the BB ' section and the concentration of the second ions which are directly injected into the active region at the AA ' section are equal. At the BB 'cross section, part of the second ions contact the surface of the first photoresist pattern 200, and are reflected by the first photoresist pattern 200, limited by the distance D between the edge of the etched window 201 at the BB' cross section and the drain drift region 104 3 And a predetermined tilt angle α of ion implantation, as shown in fig. 7, a portion of the second ions contacting the first photoresist pattern 200 is reflected and then impinges on the shallow trench isolation structure 101. On the extension line of the drain drift region 104, the second ions reflected into the drain drift region 104 via the first photoresist pattern 200 are less and less in a direction away from the island doped region 103. The ion concentration of the drain drift region 104 is thus in a decreasing trend in the direction away from the island doping region 103 on the extension line of the drain drift region 104. Specifically, in the present embodiment, the ion concentration of the drain drift region 104 is along the length direction of the drain drift region 104, along the distance from the island dopingThe direction of the region 103 is linearly distributed and decreases.
Referring to fig. 6 to 8 and fig. 18, in an embodiment of the present application, the length of the drain drift region 104 is, for example, 50 μm to 60 μm, and the length of the drain drift region 104 is only shown in the drawings of the present embodiment. In the present embodiment, the ion concentration of the drain drift region 104 may be, for example, 1×10 15 cm -3 ~5×10 15 cm -3 . Wherein the concentration of the drain drift region 104 near the end of the island doped region 103 may be, for example, 5×10 15 cm -3 . The concentration of the drain drift region 104 at the end remote from the island doped region 103 may be, for example, 1×10 15 cm -3 . As shown in fig. 8 and 18, the horizontal direction is the X-axis, and the direction close to the island doped region 103 is the X-axis positive direction. Wherein the X-axis represents the length of the drain drift region 104 and the vertical axis represents the ion concentration of the drain drift region 104. In the present embodiment, the length of the drain drift region 104 is, for example, 40 μm to 60 μm, and may specifically be, for example, 60 μm. In the present embodiment, the concentration of the drain drift region 104 increases linearly along the positive X-axis direction as shown by the straight line c in fig. 18, and the ion concentration of the drain drift region 104 increases linearly. In another embodiment of the present application and in yet another embodiment, a non-linear incremental ion concentration profile may also be formed along the positive X-axis direction, as in the edge line profile of the etched window 201 of fig. 4 and 5.
Referring to fig. 6-8, and fig. 18, in one embodiment of the present application, the linear distributed ion concentration region of the drain drift region 104 is formed at one time. In the case of performing ion implantation a plurality of times, the concentration division is remarkable, it is difficult to form a good breakdown voltage, and the shape of the first photoresist pattern 200 needs to be adjusted correspondingly each time ion implantation is performed. As shown in fig. 18, the broken line a corresponds to ion implantation performed in 3 times, and ion implantation is performed when the length of the drain drift region 104 is, for example, 0 μm, for example, 13 μm, and for example, 27 μm, respectively. Corresponding to the broken line a, the concentration is smaller than 0.6E12/cm when the second ions are injected for the first time 3 And a drain drift region 104 of length, for example, 13 μm. At the time of the second ion injection, the concentration is formed as an exampleFor example 1.2E12/cm 3 And a drain drift region 104 of length 14 μm. On the third injection of the second ions, a concentration of more than, for example, 1.8E12/cm is formed 3 And a drain drift region 104 of length, for example, 13 μm. Corresponding to the broken line b, the concentration is 0.6E12/cm, for example, when the second ion is injected for the first time 3 And a drain drift region 104 of length 20 μm. At the time of the second ion injection, a concentration of, for example, 1.8E12/cm is formed 3 And a drain drift region 104 of length, for example, 20 μm. In the present embodiment, the second ion is implanted at one time corresponding to the broken line c, and the concentration is formed to be greater than 0 and less than or equal to 2.4E12/cm, for example 3 Thereby lowering the surface electric field of the substrate 100 and raising the breakdown voltage of the semiconductor device.
Referring to fig. 8 and 9, in one embodiment of the present application, after forming the drain drift region 104 in the substrate 100, a source body region 105 is formed in the substrate 100. Specifically, after the drain drift region 104 is formed, the first photoresist pattern 200 is removed. And spin-coating photoresist on the substrate 100 to form a second photoresist layer, and patterning the second photoresist layer by means of exposure etching or the like to form a second photoresist pattern 300. The active region is implanted with first ions in a direction perpendicular to the surface of the substrate 100 to form a source body region 105. In this embodiment, the first ions may be boron ions, and the source body region 105 may be a P-type body region. One side of the source body region 105 contacts the shallow trench isolation structure 101, and the other side of the source body region 105 contacts the drain drift region 104. The impurities in the source body region 105 and the drain drift region 104 are donor impurities and acceptor impurities to each other. In this embodiment, the length of the source body 105 may be, for example, 8 μm to 12 μm, and may specifically be, for example, 10 μm. The first ion concentration in the source body region 105 may be, for example, 1×10 17 cm -3 ~5×10 17 cm -3 . After forming the source body region 105, the second photoresist pattern 300 is removed. In this embodiment, the ion concentration of the source body region 105 is greater than the ion concentration of the drain drift region 104. In the drain drift region 104, the ion concentration increases in a horizontal direction, in a direction away from the source body region 105, to split the drain surface voltage, raising the breakdown voltage.
Referring to fig. 9 to 12, in an embodiment of the present application, after forming a source body region 105 in a substrate 100, a field oxide layer 400 and a gate oxide layer 500 are sequentially formed on the substrate 100. Wherein the field oxide layer 400 is disposed on the drain drift region 104. The gate oxide layer 500 is disposed on the source body region 105, and the gate oxide layer 500 is connected to the field oxide layer 400. In this embodiment, the field oxide layer 400 is deposited on the substrate 100 by Chemical vapor deposition (Chemical VaporDeposition, CVD). A third photoresist pattern 401 is formed on the field oxide layer 400 and the field oxide layer 400 is etched using the third photoresist pattern 401 as a mask, forming the field oxide layer 400 as shown in fig. 10. Next, an oxide such as silicon dioxide is deposited on the substrate 100 by chemical vapor deposition to form the gate oxide layer 500. A fourth photoresist pattern 501 is formed by spin-coating photoresist on the gate oxide layer 500, and the gate oxide layer 500 is etched using the fourth photoresist pattern 501 as a mask, thereby forming the gate oxide layer 500 as shown in fig. 12. After the gate oxide layer 500 is formed, the third and fourth photoresist patterns 401 and 501 are removed. In this embodiment, the thickness of the field oxide layer 400 is greater than the thickness of the gate oxide layer 500.
Referring to fig. 12 and 13, in an embodiment of the present application, after forming a field oxide layer 400 and a gate oxide layer 500 sequentially on a substrate 100, a polysilicon layer 600 is formed on the field oxide layer 400 and the gate oxide layer 500. Specifically, the polysilicon layer 600 is formed by depositing polysilicon on the substrate 100, the field oxide layer 400, and the gate oxide layer 500 by chemical vapor deposition. And patterning the polysilicon layer 600 by photolithography, etching to remove a portion of the polysilicon layer 600 located on the substrate 100, and a portion of the polysilicon layer 600 covering the top surface of the field oxide layer 400, to form the polysilicon layer 600 as shown in fig. 12. In this embodiment, the polysilicon layer 600 covers the gate oxide layer 500, a portion of the field oxide layer 400, and a sidewall of the field oxide layer 400 adjacent to the gate oxide layer 500. In this embodiment, the thickness of the polysilicon layer 600 is smaller than that of the field oxide layer 400. Wherein the gate oxide layer 500 and the polysilicon layer 600 form a gate structure.
Referring to fig. 13 to 15, in an embodiment of the present application, after forming a polysilicon layer 600 on the field oxide layer 400 and the gate oxide layer 500, a first type doped region 106 and a second type doped region 107 are formed in the substrate 100. Tool withA second ion is implanted into the active region to form a plurality of first type doped regions 106. In the present embodiment, the second ion may be a phosphorus ion to form the first type doped region 106 of N type, and the concentration of the first type doped region 106 is, for example, 1×10 20 cm -3 ~5×10 20 cm -3 . In the present embodiment, the second ions are simultaneously implanted into the drain drift region 104 and the source body region 105 along the direction perpendicular to the surface of the substrate 100, so as to form a plurality of first type doped regions 106. In this embodiment, the active region includes, for example, 2 first type doped regions 106, which are respectively a drain first doped region 106a in the drain drift region 104 and a source first doped region 106b in the source body region 105. Next, first ions are implanted into the source body region 105 to form a second type doped region 107. In this embodiment, the first ions may be boron ions to form the P-type second-type doped region 107. The second type doped region 107 is connected to the source first doped region 106b and the shallow trench isolation structure 101. The PN junction is formed at the connection interface between the source first doped region 106b and the source body region 105, at the connection interface between the second type doped region 107 and the source first doped region 106b, and at the connection interface between the source body region 105 and the drain drift region 104. In this embodiment, when forming the drain first doped region 106a in the drain drift region 104, one side of the drain first doped region 106a is connected to the shallow trench isolation structure 101, and the other side is diffused to the bottom of the field oxide layer 400. When forming the source first doped region 106b in the source body region 105, one side of the source first doped region 106b is connected to the second type doped region 107, and the other side is diffused to the bottom of the gate oxide layer 500.
Referring to fig. 14 to 16, in an embodiment of the present application, after forming the first type doped region 106 and the second type doped region 107 in the substrate 100, a silicide layer 700 is formed on the substrate 100 and on the polysilicon layer 600. Specifically, the silicide layer 700 overlies the polysilicon layer 600, portions of the source body region 105, and portions of the drain drift region 104. The silicide layer 700 includes a gate silicide layer 700a and a source-drain silicide layer 700b. The gate silicide layer 700a is covered on the polysilicon layer 600. The source drain silicide layer 700b overlies a portion of the drain first doped region 106a, as well as a portion of the source first doped region 106b and a portion of the second type doped region 107. In this embodiment, a silicon nitride film is deposited on the substrate 100, the polysilicon layer 600 and the field oxide layer 400 by chemical vapor deposition, and then etched through a photoresist mask to remove silicon nitride on the area where the silicide layer 700 is to be formed. Next, a metal such as cobalt, titanium, nickel, and the like is deposited by a physical vapor deposition method on the region where the silicide layer 700 is to be formed. The semiconductor structure is then annealed to react the metal with the silicon to form silicide layer 700. And then removing unreacted metal by wet etching, and removing the silicon nitride film. Wherein the silicon nitride film is used as a mask for the assisted etch deposition, fig. 14-16 are not shown.
Referring to fig. 15 and 16, in an embodiment of the present application, a silicide layer 700 is formed on a substrate 100 and a polysilicon layer 600, a dielectric layer 800 is formed on the substrate 100, a field oxide layer 400 and the silicide layer 700, and the dielectric layer 800 is etched to form a plurality of deposition channels 801. In this embodiment, dielectric layer 800 is deposited by chemical vapor deposition on shallow trench isolation structure 101, on first type doped region 106 and on second type doped region 107, and on silicide layer 700 and on field oxide layer 400. The dielectric layer 800 is etched with the aid of a photoresist mask to form a plurality of deposition channels 801, and the deposition channels 801 are disposed on the upper silicide layer 700. Specifically, the deposition channel 801 is disposed on the source-drain silicide layer 700b, and on the gate silicide layer 700 a. Wherein the deposition channel 801 on the gate silicide layer 700a is disposed on the gate oxide layer 500.
Referring to fig. 15 to 17, in an embodiment of the present application, after forming the silicide layer 700 and the deposition channel 801, the deposition channel 801 is filled to form the contact pillar 900. Specifically, the contact pillars 900 are formed by depositing a metal material, such as copper, aluminum, and tungsten, in the deposition channel 801 by chemical vapor deposition, until the metal material fills the deposition channel 801. Wherein, when filling the metal material, the metal material may overflow the deposition channel 801. After filling the metal material, the metal material and a portion of the dielectric layer 800 are subjected to chemical mechanical polishing (Chemical Mechanical Polishing, CMP) to level the surface of the contact pillars 900 with the surface of the dielectric layer 800, thereby forming the semiconductor device of the present application. After the contact pillars 900 are formed, metal interconnect structures may be provided on the dielectric layer 800 and on the contact pillars 900 to form integrated circuit wiring to form a semiconductor chip.
Referring to fig. 18 and 19, fig. 19 shows the change in surface electric field at the cross section of the drain drift region 104 of the semiconductor device in the present embodiment and the comparative example in the present embodiment. Curve 1 shows the change of the surface electric field of the drain drift region 104 in this embodiment. The abscissa corresponds to the length distance of the drain drift region 104, and the ordinate corresponds to the surface electric field strength of the drain drift region 104. Curve 1 is an example of a drain drift region 104 and the drain drift region 104 is linearly doped, and curve 2 is a control group of the drain drift region 104 uniformly doped. As can be seen from comparing the profiles of the curves 1 and 2, in the present embodiment, the surface electric field intensity at both ends of the drain drift region 104 is lower, while the surface electric field intensity at both ends of the drain drift region 104 in the control group is higher. In addition, in the present embodiment, the surface electric field intensity in the center of the drain drift region 104 is higher, while the surface electric field intensity in the center of the drain drift region 104 in the control group is lower. For the control group, the electric field strength of the drain drift region 104 is extremely large, and the uniformity is poor, so that it is easy to break down. In this embodiment, the pressure distribution of the entire drain drift region 104 is uniform, so that the breakdown voltage of the semiconductor device is improved.
The application provides a semiconductor device and a manufacturing method thereof. Wherein the source body region and the drain drift region are disposed in the substrate. The drain drift region is connected to the source body region, wherein the ion doping concentration of the drain drift region decreases along a direction approaching the source body region. Wherein the gate structure is disposed on the source body. The contact pillars are connected to the source body region, the drain drift region, and the gate structure. The unexpected effect of the application is that the surface electric field of the semiconductor device is distributed uniformly, the breakdown voltage is high, and the working stability of the semiconductor device is good. In addition, the semiconductor device provided by the application can reduce the voltage of the electric fields at the two ends of the drift region and improve the voltage of the electric field in the center of the drift region, so that the stability of the semiconductor device is improved. According to the manufacturing method of the semiconductor device, the drift region with uniform electric field distribution can be formed only through one step, the process cost is low, and the doping of the formed drift region can be linearly distributed, so that the breakdown voltage of the semiconductor device is improved.
The embodiments of the application disclosed above are intended only to help illustrate the application. The examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A semiconductor device, comprising at least:
a substrate;
a source body region disposed in the substrate;
the drain drift region is arranged in the substrate, is arranged side by side with the source electrode body region, and linearly reduces the ion doping concentration from the direction away from the source electrode body region to the direction close to the source electrode body region;
a first photoresist pattern disposed on the substrate in the step of forming the drain drift region, wherein the first photoresist pattern includes an etching window covering an active region of the substrate, wherein a length of the etching window is equal to a length of the active region, a width of the etching window is greater than a width of the active region, and the etching window width increases in a direction approaching the source body region;
a field oxide layer disposed on the substrate, wherein the field oxide layer covers a part of the drain drift region;
and the grid electrode structure is arranged on the source electrode body region and covers part of the field oxide layer.
2. A semiconductor device according to claim 1, characterized in that the drain drift region and the source body region are provided with a first type doped region, which is located on the side of the drain drift region remote from the source body region and on the side of the source body region remote from the drain drift region.
3. The semiconductor device of claim 2, wherein the gate structure comprises a gate oxide layer overlying a portion of the source body region, wherein one side of the gate oxide layer is connected to the field oxide layer and the other side of the gate oxide layer extends over the first type doped region.
4. A semiconductor device according to claim 3, wherein the gate structure comprises a polysilicon layer covering the gate oxide layer and a portion of the field oxide layer, wherein the polysilicon layer is connected to a sidewall and a portion of a top surface of the field oxide layer.
5. A semiconductor device according to claim 2, characterized in that a second type doped region is provided in the source body region, the second type doped region being adjacent to the first type doped region, and the first type doped region being located between the second type doped region and the drain drift region.
6. The semiconductor device of claim 5, wherein the doping type of the first type doped region is the same as the doping type of the drain drift region, and the doping type of the second type doped region is the same as the doping type of the source body region.
7. A semiconductor device according to claim 2, characterized in that a buried oxide layer is provided in the substrate, the buried oxide layer being provided at the bottom of the drain drift region, and the buried oxide layer being connected to the interface of the drain drift region.
8. A semiconductor device according to claim 7, characterized in that an island doped region is provided in the drain drift region, the island doped region being located between the buried oxide layer and the doped region of the first type, the island doped region being in contact with the buried oxide layer, and an orthographic projection of the island doped region on the buried oxide layer being located in the region of the buried oxide layer.
9. The semiconductor device of claim 8, wherein the island doping region has a doping concentration greater than the doping concentration of the drain drift region and the island doping region has a doping concentration less than the doping concentration of the first type doping region.
10. A method of manufacturing a semiconductor device, comprising the steps of:
a substrate is provided and a substrate is provided,
implanting second type ions into the substrate to form a drain drift region, wherein a first photoresist pattern is arranged on the substrate before the drain drift region is formed, the width of an etching window of the first photoresist pattern increases gradually along the direction close to the source body region, the etching window covers an active region of the substrate, the length of the etching window is equal to the length of the active region, and the width of the etching window is larger than the width of the active region;
implanting first type ions into the substrate to form a source electrode body region, wherein the drain electrode drift region and the source electrode body region are arranged side by side, and the ion doping concentration of the drain electrode drift region linearly decreases from the direction away from the source electrode body region to the direction close to the source electrode body region;
forming a field oxide layer on the substrate, wherein the field oxide layer covers part of the drain drift region; and
and forming a gate structure on the source electrode body region, wherein the gate structure covers part of the field oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310953302.XA CN116666456B (en) | 2023-08-01 | 2023-08-01 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310953302.XA CN116666456B (en) | 2023-08-01 | 2023-08-01 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116666456A CN116666456A (en) | 2023-08-29 |
| CN116666456B true CN116666456B (en) | 2023-10-31 |
Family
ID=87715760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310953302.XA Active CN116666456B (en) | 2023-08-01 | 2023-08-01 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116666456B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7964485B1 (en) * | 2009-10-23 | 2011-06-21 | National Semiconductor Corporation | Method of forming a region of graded doping concentration in a semiconductor device and related apparatus |
| CN105097936A (en) * | 2015-07-06 | 2015-11-25 | 深港产学研基地 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
| CN111785633A (en) * | 2020-06-11 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and preparation method thereof |
| CN111987166A (en) * | 2020-09-07 | 2020-11-24 | 杰华特微电子（杭州）有限公司 | Method for manufacturing lateral double-diffused transistor |
-
2023
- 2023-08-01 CN CN202310953302.XA patent/CN116666456B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7964485B1 (en) * | 2009-10-23 | 2011-06-21 | National Semiconductor Corporation | Method of forming a region of graded doping concentration in a semiconductor device and related apparatus |
| CN105097936A (en) * | 2015-07-06 | 2015-11-25 | 深港产学研基地 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
| CN111785633A (en) * | 2020-06-11 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and preparation method thereof |
| CN111987166A (en) * | 2020-09-07 | 2020-11-24 | 杰华特微电子（杭州）有限公司 | Method for manufacturing lateral double-diffused transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116666456A (en) | 2023-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7148540B2 (en) | Graded conductive structure for use in a metal-oxide-semiconductor device | |
| US6534367B2 (en) | Trench-gate semiconductor devices and their manufacture | |
| US6489204B1 (en) | Save MOS device | |
| KR100476816B1 (en) | Lateral diffused mos transistor with trench source contact | |
| US6365942B1 (en) | MOS-gated power device with doped polysilicon body and process for forming same | |
| US20230335640A1 (en) | Semiconductor structure and associated fabricating method | |
| US6660591B2 (en) | Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture | |
| JP2005503023A (en) | Trench gate semiconductor device and its manufacture | |
| US6087224A (en) | Manufacture of trench-gate semiconductor devices | |
| CN113053738A (en) | Split gate type groove MOS device and preparation method thereof | |
| CN112635540A (en) | LDMOS device and preparation method thereof | |
| KR100272051B1 (en) | Process for manufacture of a p-channel mos gated device with base implant through the contact window | |
| CN114361251A (en) | Preparation method of split gate power MOS device | |
| CN116666456B (en) | Semiconductor device and manufacturing method thereof | |
| US7087472B2 (en) | Method of making a vertical compound semiconductor field effect transistor device | |
| US11688805B2 (en) | Integrated circuit structure and method for forming the same | |
| US20230268421A1 (en) | Method for auto-aligned manufacturing of a trench-gate mos transistor, and shielded-gate mos transistor | |
| US20230420558A1 (en) | Semiconductor device and manufacturing method thereof | |
| TW201351642A (en) | Semiconductor device and method of fabricating the same | |
| JP2002505811A (en) | Method for manufacturing field effect semiconductor device | |
| CN110676173B (en) | Semiconductor device structure and forming method thereof | |
| KR20040002411A (en) | Trench-gate semiconductor devices and their manufacture | |
| KR20170137002A (en) | Combined gate trench and contact etch process and related structure | |
| CN116259542A (en) | Method for manufacturing planar SiC MOSFET device | |
| CN117690795A (en) | Novel shielded gate trench field effect transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |