CN105097936A - Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device - Google Patents
Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device Download PDFInfo
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- CN105097936A CN105097936A CN201510395176.6A CN201510395176A CN105097936A CN 105097936 A CN105097936 A CN 105097936A CN 201510395176 A CN201510395176 A CN 201510395176A CN 105097936 A CN105097936 A CN 105097936A
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- 239000004065 semiconductor Substances 0.000 title abstract description 9
- 239000012212 insulator Substances 0.000 title abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 115
- 239000010703 silicon Substances 0.000 claims abstract description 115
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 17
- 229910052760 oxygen Inorganic materials 0.000 claims description 17
- 239000001301 oxygen Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- 239000002210 silicon-based material Substances 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 238000011161 development Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
Abstract
The invention relates to a silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device, which comprises a substrate layer (7), a buried oxide layer (6) and a silicon film layer, wherein the silicon film layer comprises a drain region (5) at an upper corner of the right side, an N-type silicon island (4) at a lower corner of the right side, a drift region (3) in the residual part of the right side, a silicon body (2) at the left side and a source region (1), wherein the source region (1), except for the upper surface, is completely surrounded by the silicon body (2); a channel is provided by a part, between the source region and the drift region, in the silicon body; the doping concentration of the N-type silicon island is greater than that of the drift region; a gate oxidation layer (8) is arranged above the channel; an extended field plate (11) is arranged above the drift region; the thickness of the extended field plate is greater than that of the gate oxidation layer; the gate oxidation layer is completely covered by a gate electrode (9); and only the part, close to the channel, of the extended field plate is covered by a gate electrode field plate (10) to form a stair gate electrode. According to the power device, the capacity of the silicon film layer of the LDMOS device for accommodating a current carrier is relatively high; and relatively multiple electric fields are introduced into the buried oxide layer, so that the on-resistance is reduced; the breakdown voltage is improved; and further development of a semiconductor power integrated circuit is promoted.
Description
Technical field
The present invention relates to the power device field that semiconductor high-voltage power integrated circuit uses, be specifically related to one and there is N-type silicon island (N-island, NIS) silicon (Silicon-on-Insulator on insulating barrier, SOI) lateral double diffusion metal oxide semiconductor (LateralDouble-diffusedMetal-Oxide-Semiconductor, LDMOS) power device, english abbreviation NISSOILDMOS.
Background technology
Power integrated circuit is the important component part of semiconductor integrated circuit, simultaneously also for electric automobile, radar, base station and aerospace industry etc. provide safeguard.The today of making rapid progress, for power integrated circuit, its most crucial problem further developed is still the performance improving High voltage power device how further, is also two problems: 1. device power control capability: puncture voltage and operating current; 2. device parameter performance index: conducting resistance, operating frequency and switching speed etc.Therefore, multiple high-voltage LDMOS new construction is suggested, such as low-K dielectric buried regions LDMOS, buried charge layer LDMOS, carborundum LDMOS etc.On insulating barrier silicon (SOI) structure owing to having, electric current is large, medium isolation is good, switching speed is high and with the feature such as CMOS technology compatibility is good, soi structure is received much concern, and SOI-LDMOS can make the performances such as the puncture voltage of device, operating current, conducting resistance more superior.Therefore, the present invention is to improving High voltage power device performance and promoting that the development of semiconductor power integrated circuit has positive role.
Summary of the invention
The technical issues that need to address of the present invention are, how silicon LDMOS power device on a kind of insulating barrier is provided, there is more high-breakdown-voltage, more low on-resistance and more high driving ability, thus the performance of High voltage power device can be improved and promote further developing of semiconductor power integrated circuit.
Above-mentioned technical problem of the present invention solves like this: build silicon LDMOS power device on a kind of insulating barrier, it is characterized in that, described LDMOS power device comprises substrate layer, the middle oxygen buried layer formed by oxide and the silicon film formed by silicon materials that bottom is formed by silicon materials from top to bottom above; Described silicon film comprises the silicon body and source region that are positioned at left side and the drain region being positioned at right side, N-type silicon island and drift region; Described source region is all surrounded by described silicon body (2) outside except upper surface, described drain region is positioned at upper angle on the right side of described silicon film, described N-type silicon island is positioned at inferior horn on the right side of described silicon film, except the remainder of described drain region and N-type silicon island is drift region on the right side of described silicon film, the length of described drain region and N-type silicon island is all less than the length of described drift region, and the thickness sum of described drain region and N-type silicon island is also less than the thickness of described drift region; Raceway groove is provided by the part in described silicon body between described source region and drift region; Described N-type silicon island doping content is greater than described drift doping concentration; Being the gate oxide formed by oxide above described raceway groove, is the expansion field plate formed by oxide above described drift region, and the thickness of described expansion field plate is greater than the thickness of described gate oxide; Described gate oxide is all covered by the gate electrode formed by metal, and described expansion field plate only has the part near described raceway groove just to be covered by the gate electrode field plate formed by metal, forms ladder step gate electrode.
According to silicon LDMOS power device on insulating barrier provided by the invention, the numerous Parameter adjustable on this insulating barrier in silicon LDMOS power device:
1, its drain region adjustable length;
2, its source region adjustable length;
3, the adjustable length of its raceway groove;
4, its drift region total length is adjustable;
5, the gate electrode field plate length above its drift region is adjustable;
6, its source region dopant material, doping content is adjustable;
7, its drain region dopant material, doping content is adjustable;
8, its channel region (P-type silicon body) dopant material, doping content is adjustable;
9, its drift region dopant material, doping content is adjustable;
10, its substrate dopant material, doping content is adjustable;
11, its gate oxide material, thickness is adjustable;
12, its expansion field plate material, thickness is adjustable;
13, its oxygen buried layer material, thickness is adjustable;
14, its silicon film thickness is adjustable;
14, its silicon island dopant material, doping content, length, thickness is adjustable.
Silicon LDMOS power device on insulating barrier provided by the invention, in source region, drain region, silicon body, the length of drift region and substrate, material, doping type be all identical with doping content, top silicon surface is identical, oxygen buried layer thickness is identical, and under all consistent condition of all insulation oxide material parameters, compare with silicon LDMOS (ConventionalSilicon-on-InsulatorLDMOS, CSOILDMOS) on traditional insulating barrier.Introducing N-type silicon island makes the silicon film of high-voltage LDMOS device hold the ability of charge carrier more by force, thus electric current is increased, and causes the conducting resistance (On-resistance, Ron) of device to reduce; On the other hand, more electric field can be introduced in N-type silicon island in the oxygen buried layer below drain region, thus device proposed its puncture voltage (BreakdownVoltage, BV) be improved.Therefore, the present invention is the further performance optimization of high pressure SOILDMOS, and selects for high voltage integrated circuit design provides a new device architecture.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail further.
For the ease of describing, the LDMOS power device (NISSOILDMOS) below the LDMOS power device (CSOILDMOS) of silicon on traditional insulating barrier and the present invention with silicon on the insulating barrier of N-type silicon island is respectively referred to as CSOI and NISSOI.
Fig. 1 is the schematic cross-section of NISSOILDMOS of the present invention;
Fig. 2 is the silicon island length of NISSOI is 25 microns, and thickness is 0.5 micron, other parameters of fixed L DMOS transistor, the impact that the insulating barrier silicon-on with N-type silicon island distributes on device drain terminal longitudinal electric field;
Fig. 3 is the silicon island length of NISSOI is 25 microns, and thickness is 0.5 micron, other parameters of fixed L DMOS transistor, the impact that the insulating barrier silicon-on with N-type silicon island distributes on device drain terminal longitudinal voliage;
Fig. 4 is the silicon island length of NISSOI is 10 microns, other parameters of fixed L DMOS transistor, changes silicon island thickness to the impact of device electric breakdown strength BV;
Fig. 5 is the silicon island thickness of NISSOI is 0.5 micron, other parameters of fixed L DMOS transistor, changes silicon island thickness to the impact of device electric breakdown strength BV;
Fig. 6 is other parameters of fixed L DMOS, compares the puncture voltage of two kinds of device architectures and the tradeoff of conducting resistance.
Wherein Reference numeral: 1-source, 2-silicon body, 3-drift region, 4-silicon island, 5-leakage, 6-buried oxide region, 7-substrate, 8-gate oxide, 9-gate electrode, 10-gate electrode field plate, 11-expand field plate.
Embodiment
The present invention includes but be not restricted to following five specific embodiments:
First, the common trait of the present invention's five specific embodiments is described:
As shown in Figure 1, on the partial insulative layer with N-type silicon buried layer of the present invention, the ldmos transistor (BNLPSOI-LDMOS) of silicon comprises source region 1, silicon body 2, drift region 3, silicon island 4, drain region 5, oxygen buried layer 6, substrate 7, gate oxide 8, gate electrode 9, gate electrode field plate, expansion field plate 11; These parts are that silicon materials, oxide or metal are formed, white corresponding silicon materials in figure, the corresponding oxide of grey, the corresponding metal of black.
These parts are mainly divided into four layers again: substrate layer, oxygen buried layer, silicon film and device top layer:
(1) bottom transistor be substrate layer 7, doping type is P type, and doping content is the silicon materials of 2 × 1014cm-3.
(2) above substrate layer be oxygen buried layer 6, adopt thickness to be the silicon dioxide of 3m.
(3) on oxygen buried layer be silicon film, thickness is 5m, and wherein all regions are all silicon materials.Silicon film top left side is the cingens source region 1 of silicon body 2, and upper right comer region is drain region 5, and the lower right corner is N-type silicon island 4, remainder is then drift region 3, and wherein, raceway groove is provided by the silicon body between source region and drift region, raceway groove length is 5 μm, and silicon island doping content is greater than drift region.Source region 1 and long 5 μm of drain region 5, doping type is N-type, and doping content is 1 × 10
20cm
-3; Silicon body 2 doping type is P type, and doping content is 1 × 10
17cm
-3; Drift region 3 length is 55 μm, and doping type is N-type, and doping content is 3.2 × 10
15cm
-3.
(4) be thin gate oxide 8 above raceway groove, adopt the silicon dioxide of thick 40nm, be thick expansion field plate 11 above drift region, adopt the silicon dioxide of thick 0.8 μm; Gate oxide is all covered by gate electrode 9, and expansion field plate 11 only has a part for close raceway groove just to be covered by gate electrode field plate 10, and gate electrode field plate 11 length is 4 μm, thus forms ladder step gate electrode.
Ldmos transistor (NISSOILDMOS) performance with silicon on the insulating barrier of N-type silicon island of the present invention be based on three-dimensional SentaurusTCAD software simulation research obtain, and substrate and source are all ground connection in analog simulation research, under the test of relevant conducting resistance, grid voltage and leakage pressure are respectively 5V and 10V.
The second, describe the present invention's five specific embodiments in detail respectively:
First embodiment
The N-type silicon island doping content of NISSOI is 2.5 × 10
16cm
-3, length is 25 μm, and thickness is 0.5 μm, other parameters of fixed L DMOS transistor, the impact that the insulating barrier silicon-on with N-type silicon island distributes on device drain terminal longitudinal electric field;
As shown in Figure 2, have the NISSOI structure of N-type silicon island, the electric field in oxygen buried layer is up to arriving about 1.5 × 10
16v/cm, and only have an appointment 1 × 10 in the oxygen buried layer of traditional CSOI
16the electric field of V/cm, this is because the N-type silicon island of NISSOI has the doping content higher than drift region, so can introduce more electric field in oxygen buried layer.Thus NISSOI can improve device electric breakdown strength.
Second embodiment
The N-type silicon island doping content of NISSOI is 2.5 × 10
16cm
-3, length is 25 μm, and thickness is 0.5 μm, other parameters of fixed L DMOS transistor, has the insulating barrier silicon-on of N-type silicon island to the impact of the longitudinal Potential Distributing of device drain terminal;
As shown in Figure 3, because NISPSOI has the electric field higher than CSOI in oxygen buried layer, so the voltage that oxygen buried layer (between lengthwise position 5-8 μm) is born also can be much higher, about 450V.And the substrate of two kinds of devices does not bear voltage, and the voltage difference that silicon film (between lengthwise position 0-5 μm) is born is little.Therefore, in the LDMOS of these two kinds of structures, NISSOI obtains higher puncture voltage.
3rd embodiment
The N-type silicon island length of NISSOI is 10 μm, other parameters of fixed L DMOS transistor, changes thickness and the doping content of silicon island, has the insulating barrier silicon-on of N-type silicon island to the impact of device electric breakdown strength;
As shown in Figure 4, along with the increase of silicon island thickness, the maximum breakdown voltage of NISSOI only has faint increase, more stable.Under each silicon island thickness, puncture voltage is all first increase rear reduction, this is because before maximum, because the raising of silicon island doping content can introduce higher electric field, so puncture increase in oxygen buried layer; After maximum, when silicon island doping content again raising can cause the premature breakdown of device, so puncture start decline.
4th embodiment
The N-type silicon island thickness of NISSOI is 0.5 μm, other parameters of fixed L DMOS transistor, changes length and the doping content of silicon island, has the insulating barrier silicon-on of N-type silicon island to the impact of device electric breakdown strength;
As shown in Figure 5, along with the increase of silicon island length, the maximum breakdown voltage of device first increases rear reduction, and the change of the opening of curve is more and more less, and after curve opening is too little, the clearance spaces leaving device layout for then diminishes, and is unfavorable for design and the processing of device.Under each silicon island length, puncture voltage is all first increase rear reduction, and its reason is then identical with Fig. 4.
5th embodiment
The silicon island thickness degree of NISSOI is 0.5 μm, and length is 5 μm, 10 μm, 25 μm, 30 μm respectively, and other parameters of fixed L DMOS, compare the puncture voltage of two kinds of device architectures and the relation of conducting resistance.
As shown in Figure 6, can know under seeing four conditionals, the puncture voltage of NISSOI and the tradeoff of conducting resistance good many.The optimization voltage 395V of the CSOI compared and conducting resistance 14.59 Ω mm
2, not only puncture voltage is more much higher, maximumly can reach 524V, can obtain less conducting resistance 12.95 Ω mm simultaneously
2(reducing about 11.24%), conducting resistance is less is because the doping content of silicon island is higher than drift region a lot, can provide more electronics, cause electric current to increase for electric current, thus conducting resistance.Therefore the device performance of NISSOI improves a lot than CSOI.
From above 1-5 embodiment, on the partial insulative layer with N-type silicon buried layer proposed by the invention, the ldmos transistor (BNLPSOI-LDMOS) of silicon can introduce higher electric field strength in oxygen buried layer, thus improves the puncture voltage of device; By the more electronics that N-type silicon buried layer provides, strengthen the current driving ability of transistor, and the conducting resistance of device can be reduced; Due to the material impact of silicon island, need to consider to select the parameter of silicon island to obtain more excellent device performance comprehensively.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention scope change and modify, and all should belong to the covering scope of the claims in the present invention.
Claims (4)
1. silicon LDMOS power device on an insulating barrier, it is characterized in that, described LDMOS power device comprises substrate layer (7), the middle oxygen buried layer (6) formed by oxide and the silicon film formed by silicon materials that bottom is formed by silicon materials from top to bottom above, described silicon film comprises the silicon body (2) and source region (1) that are positioned at left side and the drain region (5) on the right side of being positioned at, N-type silicon island (4) and drift region (3), described source region (1) is all surrounded by described silicon body (2) outside except upper surface, described drain region (5) is positioned at upper angle on the right side of described silicon film, described N-type silicon island (4) is positioned at inferior horn on the right side of described silicon film, except the remainder of described drain region (5) and N-type silicon island (4) is drift region (3) on the right side of described silicon film, the length of described drain region (5) and N-type silicon island (4) is all less than the length of described drift region (3), the thickness sum of described drain region (5) and N-type silicon island (4) is also less than the thickness of described drift region (3), raceway groove is provided by the part in described silicon body (2) between described source region and drift region, described N-type silicon island (4) doping content is greater than described drift region (3) doping content, be the gate oxide (8) formed by oxide above described raceway groove, be the expansion field plate (11) formed by oxide above described drift region, the thickness of described expansion field plate is greater than the thickness of described gate oxide, described gate oxide is all covered by the gate electrode (9) formed by metal, and described expansion field plate only has the part near described raceway groove just to be covered by the gate electrode field plate (10) formed by metal, forms ladder step gate electrode.
2. silicon LDMOS power device on insulating barrier according to claim 1, is characterized in that, the length of described source region, drain region, raceway groove, drift region, N-type silicon island and gate electrode field plate requires different and different according to specific design.
3. silicon LDMOS power device on insulating barrier according to claim 1, is characterized in that, the dopant material of described source, leakage, raceway groove, drift region, N-type silicon island and substrate layer, doping content require different and different according to specific design; Described raceway groove is P-type silicon body.
4. silicon LDMOS power device on insulating barrier according to claim 1, is characterized in that, the material of described gate oxide, expansion field plate, silicon island and oxygen buried layer, thickness require different and different according to specific design.
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|---|---|---|---|
| CN201510395176.6A CN105097936A (en) | 2015-07-06 | 2015-07-06 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
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|---|---|---|---|
| CN201510395176.6A CN105097936A (en) | 2015-07-06 | 2015-07-06 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598167A (en) * | 2018-05-02 | 2018-09-28 | 杭州电子科技大学 | Silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers |
| CN112466955A (en) * | 2020-12-04 | 2021-03-09 | 重庆邮电大学 | Thin-layer SOI-LDMOS device with in-vivo conductive channel |
| WO2023124902A1 (en) * | 2021-12-31 | 2023-07-06 | 无锡华润上华科技有限公司 | Trench dmos device and manufacturing method therefor |
| CN116666456A (en) * | 2023-08-01 | 2023-08-29 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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| CN1841775A (en) * | 2005-03-30 | 2006-10-04 | 松下电器产业株式会社 | High breakdown voltage semiconductor device and fabrication method of the same |
| CN1983632A (en) * | 2005-10-25 | 2007-06-20 | 三星电子株式会社 | Lateral double diffusion metal oxide semiconductor transistor and method of fabricating thereof |
| WO2007072655A2 (en) * | 2005-12-21 | 2007-06-28 | Toyota Jidosha Kabushiki Kaisha | Lateral soi semiconductor devices and manufacturing method thereof |
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| CN1841775A (en) * | 2005-03-30 | 2006-10-04 | 松下电器产业株式会社 | High breakdown voltage semiconductor device and fabrication method of the same |
| CN1983632A (en) * | 2005-10-25 | 2007-06-20 | 三星电子株式会社 | Lateral double diffusion metal oxide semiconductor transistor and method of fabricating thereof |
| WO2007072655A2 (en) * | 2005-12-21 | 2007-06-28 | Toyota Jidosha Kabushiki Kaisha | Lateral soi semiconductor devices and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598167A (en) * | 2018-05-02 | 2018-09-28 | 杭州电子科技大学 | Silicon ldmos transistor on a kind of insulating layer with a variety of part buried layers |
| CN108598167B (en) * | 2018-05-02 | 2021-02-09 | 杭州电子科技大学 | Silicon-on-insulator LDMOS transistor with multiple partial buried layers |
| CN112466955A (en) * | 2020-12-04 | 2021-03-09 | 重庆邮电大学 | Thin-layer SOI-LDMOS device with in-vivo conductive channel |
| WO2023124902A1 (en) * | 2021-12-31 | 2023-07-06 | 无锡华润上华科技有限公司 | Trench dmos device and manufacturing method therefor |
| CN116666456A (en) * | 2023-08-01 | 2023-08-29 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN116666456B (en) * | 2023-08-01 | 2023-10-31 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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Application publication date: 20151125 |