TW201351642A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type being adjacent to the outside of the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a trench structure and a method of fabricating the same.

A double-diffused MOS (DMOS) has two branches, one is a laterally diffused MOS (LDMOS) and the other is a vertically diffused MOS device (Vertical double- Diffused MOS, VDMOS). Among them, DMOS has been widely used in high-voltage operating environments due to its high operating bandwidth and operating efficiency, such as CPU power supply, power management system, DC/ AC/DC converters and power amplifiers in high or high frequency bands.

For LDMOS, it generally comprises a substrate of a first conductivity type (for example, P type), a source of a second conductivity type (for example, N type) disposed in the substrate, and a drain, wherein the source is buried in the source. A P-type well and a gate structure disposed on the field oxide layer. When the component is in the on state, the current between the source and the drain flows through the low-doping concentration, large-area lateral diffusion drift region set at the 汲 terminal to the source terminal. Therefore, the high voltage between the source and drain terminals is mitigated, allowing the LDMOS to achieve a higher breakdown voltage (V _bd ).

However, since conventional LDMOS devices have a large cell pitch, it is difficult to meet the trend of miniaturization of electronic products and their peripheral products. Therefore, it is necessary to develop a novel semiconductor device and a method of fabricating the same to effectively reduce the area occupied by the device and maintain the same electrical performance.

It is an object of the present invention to provide a semiconductor device having a trench structure and a method of fabricating the same to save a horizontal area occupied by the semiconductor device.

According to a preferred embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a buried layer, a deep well region having a first conductivity type, disposed in the semiconductor substrate, and the deep well region is located in the buried layer a first doped region having a first conductivity type disposed in the deep well region, and the first doped region contacts the buried layer, a conductive region having a first conductivity type, and adjacent to the first doped region And the dopant concentration of the conductive region is higher than the dopant concentration of the first doping region, a first heavily doped region having the first conductivity type, disposed in the first doping region, and having a well of the second conductivity type a second heavily doped region having a first conductivity type disposed in the deep well region, disposed in the well region and having a gate disposed between the first heavily doped region and the second heavily doped region a first trench structure on the semiconductor substrate is disposed in the semiconductor substrate on the gate side, and the first trench structure contacts the buried layer and a second trench structure, and is disposed on the gate opposite to the first trench structure One side of the semiconductor substrate, wherein the second trench structure is deep Based substantially greater than the depth of the buried layer.

According to another preferred embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a buried layer, a deep well region having a first conductivity type, disposed in the semiconductor substrate, and the deep well region is buried a first doped region having a first conductivity type disposed in the deep well region, and the first doped region contacts the buried layer, a conductive region having a first conductivity type, adjacent to the first doping And a conductive region comprising a metal composition, a first heavily doped region having a first conductivity type, disposed in the first doped region, a well region having a second conductivity type, disposed in the deep well region, and having a second heavily doped region of the first conductivity type is disposed in the well region, a gate, and is disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region, and a first trench structure. Provided in the semiconductor substrate on the gate side, and the first trench structure contacts the buried layer and a second trench structure, and is disposed in the semiconductor substrate opposite to the gate of the first trench structure, wherein the second The depth of the trench structure is substantially larger than the buried Of depth.

According to still another preferred embodiment of the present invention, a method of fabricating a semiconductor device is provided, comprising the following steps. First, a semiconductor substrate is provided and a buried layer and a deep well region are respectively formed in the semiconductor substrate, wherein the deep well region is located on the buried layer. An opening is then formed in the deep well region, wherein a portion of the buried layer is exposed at the bottom of the opening. A conductive region is formed on the sidewall of the opening. The opening is filled with a first doped region having a first conductivity type. Finally, at least one first trench structure and at least one second trench structure are respectively formed in the deep well region, wherein the first trench structure extends into the buried layer and the depth of the second trench structure is substantially greater than the depth of the buried layer.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

The present invention first provides a semiconductor device, please refer to FIG. 1 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 1, the semiconductor device 20 of the present invention comprises a semiconductor substrate 22, a buried layer 24, a deep well region 26, a first doped region 28, a conductive region 62, a well region 30, and a The first heavily doped region 32, a second heavily doped region 34, a third heavily doped region 36, a gate 38, a first trench structure 40, and a second trench structure 42. The semiconductor substrate 22 may comprise, for example, a substrate composed of a gallium arsenide, a blanket insulating (SOI) layer, an epitaxial layer, a germanium layer or other semiconductor substrate material. The buried layer 24 is disposed in the semiconductor substrate 22. In this embodiment, the buried layer 24 can be a heavily doped first conductivity type buried layer 24, but not limited thereto. In order to prevent the current signal from being transmitted downward to the semiconductor substrate 22 having the second conductivity type, leakage is caused. The deep well region 26 having the first conductivity type is disposed in the semiconductor substrate 22 and on the buried layer 24, wherein the semiconductor substrate 22 may further include an epitaxial layer (not shown), and the deep well region 26 is disposed on the epitaxial layer In the layer, for example, the deep well region 26 can be disposed in an epitaxial layer having a thickness of substantially about 5 micrometers (um).

A well region 30 having a second conductivity type and a first doping region 28 having a first conductivity type are disposed in the deep well region 26, wherein the well region 30 preferably does not contact the buried layer 24, but does not This is limited. The top and bottom of the first doped region 28 are respectively in contact with a first heavily doped region 32 and a buried layer 24. In addition, a conductive region 62 is disposed at Between the deep well region 26 and the first doped region 28, preferably adjacent to and surrounding the periphery of the first doped region 28. In the present invention, the conductive region 62 is used as a path for the carrier to flow, which is lower with respect to the adjacent deep well region 26 having the first conductivity type and the first doping region 28 having the first conductivity type. Resistivity. According to various embodiments, the conductive region 62 may comprise a dopant of a first conductivity type, a metal halide or a metal component, but is not limited thereto. In addition, the conductive region 62 may have a doping concentration gradient or a metal telluride concentration gradient whose concentration decreases from the interface between the conductive region 62 and the first doped region 28 to the interface between the conductive region 62 and the deep well region 26. The first conductivity type may be one of N type or P type, and the second conductivity type is the other of P type or N type. In the preferred embodiment, the first conductivity type is N type. The second conductivity type is P type for explanation.

The first heavily doped region 32 and the second heavily doped region 34 each have a first conductivity type, the first heavily doped region 32 is disposed in the first doped region 28, and the second heavily doped region 34 is disposed in the well In area 30. In the present embodiment, the first heavily doped region 32 is used as a drain of the semiconductor device 20, and the second heavily doped region 34 is used as a source of the semiconductor device 20. The third heavily doped region 36 is disposed in the well region 30 having the same second conductivity type as the well region 30, and the third heavily doped region 36 can be used to regulate the potential of the well region 30. The gate 38 is disposed on the semiconductor substrate 22 between the first heavily doped region 32 and the second heavily doped region 34. The gate 38 may include a gate dielectric layer 44, a gate electrode 46, and a cap layer. 48 and a sidewall 50, and the gate 38 may be a conductive material such as polysilicon, metal halide or metal. The materials and processes are well known to those skilled in the art, and therefore will not be described herein. Among them, part of the well area 30 is located below the gate 38.

In addition, the first trench structure 40 is disposed in the semiconductor substrate 22 on one side of the gate 38 between the first heavily doped region 32 and the second heavily doped region 34. More specifically, the first trench structure 40 is disposed. In the deep well region 26 between the first doped region 28 and the well region 30. The first trench structure 40 contacts at least the buried layer 24 and preferably extends into the buried layer 24 but does not penetrate the buried layer 24. The second trench structure 42 is disposed in the semiconductor substrate 22 on the other side of the gate 38 of the first trench structure 40. The first trench structure 40 and the second trench structure 42 may each comprise an insulating material, and the second trench structure 42 is used to provide a semiconductor device 20 and other semiconductor devices (not shown) disposed in the semiconductor substrate 22. Isolated effect. The insulating materials and processes of the first trench structure 40 and the second trench structure 42 are also well known to those skilled in the art, and the first trench structure 40 and the second trench structure 42 may be separately fabricated or borrowed. The width of one of the first trench structures 40 is substantially smaller than the width of one of the second trench structures 42 , and the depth of one of the second trench structures 42 is substantially larger than the first trench structure 40 . A depth is preferably greater than a depth of the buried layer 24.

A feature of the semiconductor device 20 of the present invention is that a first trench structure 40 is provided to increase the path of the carrier flow, and a conductive region 62 is provided to provide a lower on-resistance (R _on ), which is applicable to various types. The high voltage component, for example, is applied to a vertical double-diffused MOS (VDMOS). When the semiconductor device 20 is in an on state, a high voltage current flows through the path R1 and flows through the first heavily doped region 32. The conductive region 62 having a lower resistivity enters the buried layer 24. And passing through one of the path R2 of the buried layer 24 and the path R3 of the first trench structure 40 to the gate channel (not shown) below the gate 38. It is to be noted that the present invention provides a conductive region 62 as a path for carriers to flow. Compared to conventional semiconductor devices, the present invention can provide a lower on-resistance (R _on ), thereby reducing component operation. The power consumed. It should be noted here that the flow sequence of the high voltage current is not limited to the path R1 to the path R3, and it may also flow through the path R3 and finally the path R1. . For example, the high voltage current may flow laterally from the well region 30 to the periphery of the first trench structure 40 and down the periphery of the first trench structure 40 to the buried layer 24. Subsequent to the bottom of the first trench structure 40, the buried layer 24 flows laterally to the conductive region 62. Finally, it flows up the conductive region 62 to the first heavily doped region 32.

The present invention also provides a method of fabricating a semiconductor device, please refer to Figures 2 through 10. 2 to 10 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 2, a semiconductor substrate 22 having a second conductivity type is provided, and an ion implantation process P1 is performed to form a buried layer 24 having a first conductivity type in the semiconductor substrate 22. The semiconductor substrate 22 can comprise, for example, a substrate of gallium arsenide, a germanium-clad insulating layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material, and the buried layer 24 can include an N ⁺ buried layer. Next, as shown in FIG. 3, after the buried layer 24 is formed, an epitaxial layer 52 having a second conductivity type may be further formed to thicken the semiconductor substrate 22, for example, by selective epitaxial growth. The SEG process forms an epitaxial layer 52 having a thickness of substantially 5 microns above the buried layer 24. A mask layer 60 is then formed in its entirety. As shown in FIG. 4, after the mask layer 60 is patterned, an ion implantation process P2 is performed under the cover of the mask layer 60 to form a first conductivity type in the epitaxial layer 52. The deep well region 26, that is, the deep well region 26 is located in the semiconductor substrate 22 on the buried layer 24. It should be noted here that there is no need for the sides of the deep well region 26 and the buried layer 24 to be aligned.

After forming the deep well region 26 and removing the mask layer 60, a mask layer is formed over the epitaxial layer 52 as shown in FIG. 5 and patterned. The process may be to first form a stacked multi-layer structure, for example, sequentially forming an oxide underlayer 70, a nitride underlayer 72, and a photoresist layer 76, and then patterning by lithography and etching. According to different process requirements, another oxide layer 74 may be formed before the photoresist layer 76 is formed, for example, a TEOS layer over the nitride layer 72. An etch process is then performed to transfer the pattern of photoresist layer 76 into deep well region 26 to form an opening 78 that exposes buried layer 24. The bottom of the opening 78 is preferably aligned with the surface of the buried layer 24, but is not limited thereto. For example, the bottom of the opening 78 may also partially extend into the interior of the buried layer 24.

Following a doping process P3 as shown in FIG. 6, a conductive region 62 having a first conductivity type is formed on the sidewall of the opening 78. According to a preferred embodiment of the present invention, the doping process P3 is an ion implantation process, such as an oblique ion implantation process, such that the first conductivity type dopant can be implanted into the deep well exposed to the opening 78. In the region 26, a conductive region 62 having a lower resistivity is formed in the deep well region 26 as a main path for subsequent carrier circulation.

In addition to the ion implantation process, the doping process P3 described above can be equally replaced with other processes, such as solid-phase diffusion (SPD). Process or vapor-phase diffusion (VPD) process, but is not limited thereto. For example, in the solid phase diffusion process portion, the process may be followed by a deposition process after the opening 78 is formed, and a dopant source layer (not shown) having a first conductivity type fills the opening 78. A heat drive-in process is then performed to diffuse the first conductivity type dopant in the dopant source layer into the deep well region 26. Wherein, the component of the dopant source layer comprises epitaxial germanium, polycrystalline germanium, amorphous germanium or arsenic silicate glass (ASG), but is not limited thereto. The thermal drive process described above may include a rapid thermal process (RTP), a spike thermal annealing, a laser thermal annealing (LTA) or a laser spike annealing (laser spike annealing). LSA), but not limited to this. In addition, if the doping process is a gas phase diffusion process, the dopant having the first conductivity type can be diffused into the deep well region 26 by the gas phase.

Moreover, the manner in which the conductive regions 62 are formed is not limited to the doping process, and may be replaced by a germanium metallization process. That is, the composition of the conductive region 62 may be a doped region having a first conductivity type dopant, which may also include a metal halide. The detailed process is as follows: First, as shown in FIG. 7, according to the second preferred embodiment of the present invention, after the opening 78 is formed, a metal layer 80 is entirely deposited on the surfaces of the nitride layer 72 and the opening 78. Next, a metallization heat treatment process, such as a rapid thermal processing process, is performed under an inert gas (for example, nitrogen) to diffuse metal atoms in the metal layer 80 into the deep well region 26 to form a conductive region 62. The unreacted metal layer 80 is removed again. The metal layer 80 may include a metal such as titanium, nickel, platinum, cobalt, chromium, or tungsten or an alloy thereof. It should be noted here that the composition of the metal telluride in the conductive region 62 corresponds to gold. The composition of the layer 80. For example, when the composition of the metal layer 80 is nickel, the metal telluride is a nickel silicide. Furthermore, in a preferred embodiment of the present invention, after the opening 78 is formed and the metal layer 80 is completely deposited, the metal layer 80 is directly subjected to an etching process to remove most of the metal layer 80. A side wall surface of the opening 78 is formed with a metal sidewall (not shown) as the conductive region 62. In addition, according to other preferred embodiments, the conductive region 62 may further include an epitaxial layer, and its position and function are substantially similar to those of the above embodiment, and will not be further described below for the sake of brevity.

Therefore, in each of the above embodiments, the conductive region 62 is preferably a structure distributed along the sidewall of the opening 78, such as an annular solid structure. According to other embodiments, the conductive region 62 may be located at the interface of the opening 78 and the buried layer 24, such as the conductive region 62 in FIG. 7, partially on the surface of the buried layer 24.

Finally, as shown in FIG. 8, a deposition and planarization process is performed to fill a cavity 78 with a semiconductor material having a first conductivity type, such as a polysilicon material, to form a first doped region 28 in the deep well region 26. . And according to various embodiments, the bottom of the first doping region 28 may directly contact the buried layer 24 or directly contact the conductive region (not shown).

It should be noted here that regardless of whether the main body of the conductive region 62 is a dopant of a first conductivity type or a metal halide, it has a concentration gradient distribution. For example, if the conductive region 62 has a doping concentration gradient, the doping concentration decreases from the interface between the conductive region 62 and the first doping region 28 to the interface between the conductive region 62 and the deep well region 26; Zone 62 has a metal telluride concentration gradient, and the metal telluride concentration will be from conductive zone 62 and The interface of a doped region 28 decreases toward the interface of the conductive region 62 and the deep well region 26.

Thereafter, a trench isolation process is performed using the oxide underlayer 70, the nitride underlayer 72 as a mask layer, or alternatively another hard mask can be formed thereon. As shown in Fig. 9, the first trench 40' and the second trench 42' are formed in the semiconductor substrate 22, and then the first trench 40' and the second trench 42' are filled with an insulating material. The method of filling the first trench 40' and the second trench 42' may include the following steps: first, using a chemical deposition process, such as high density plasma CVD (HDPCVD), sub-normal pressure A process such as a sub-gas CVD (SACVD) or a spin-on dielectric (SOD), forming an oxide dielectric layer (not shown) to fill the first trench 40' and the first Two ditches 42'. Next, a chemical mechanical polishing process is performed to remove the excess oxide layer, the excess oxide dielectric layer, and the remaining patterned mask layer to complete the first trench structure 40 and the second trench structure as shown in FIG. 42. The first trench structure 40 and the second trench structure 42 may be separately fabricated, so that the width and depth of the two trenches may be the same or different, or may be simultaneously fabricated by different opening sizes, so that the first trench structure 40 A width is substantially smaller than a width of the second trench structure 42 and a depth of one of the second trench structures 42 is substantially greater than a depth of the first trench structure 40, preferably greater than a depth of the buried layer 24. At this time, the first trench structure 40 contacts the buried layer 24 but does not pass through the buried layer 24, and one of the bottom surfaces of the second trench structure 42 is located below one of the bottom surfaces of the buried layer 24.

Subsequently, an ion implantation process is performed to form at least one well region 30 in the deep well region 26 on the side of the first trench structure 40, wherein the well region 30 has a second conductivity type and The system is not in contact with the buried layer 24. The first conductivity type is one of N type or P type, and the second conductivity type is the other of P type or N type. In the present embodiment, the first trench structure 40 is located between the well region 30 and the first doped region 28, the first trench structure 40 surrounds the first doped region 28, and the second trench structure 42 surrounds the deep well region 26, A trench structure 40 and a first doped region 28 are not limited thereto. The step of the ion implantation process includes first implanting a dopant having a second conductivity type into the deep well region 26, and further driving the dopant by a heat treatment process. The doping concentration of the well region 30 is substantially equal to the doping concentration of the deep well region 26 and less than the doping concentration of the buried layer 24, but is not limited thereto.

Finally, at least one gate 38 is formed on the semiconductor substrate 22. The gate 38 may include a gate dielectric layer 44, a gate electrode 46, a cap layer 48 and a sidewall spacer 50. The skilled person is well known and will not be described here. The gate 38 overlaps a portion of the deep well region 26 between the first trench structure 40 and the second trench structure 42 and partially overlaps the first trench structure 40. Thereafter, at least one first heavily doped region 32 is formed in the first doped region 28, and at least a second heavily doped region 34 is formed in the well region 30, the first heavily doped region 32 and the second heavily doped region. The doping region 34 has a first conductivity type, and the method for forming the first heavily doped region 32 and the second heavily doped region 34 includes: using the gate 38 and a patterned mask (not shown) as a mask. An ion implantation process P5 is performed to form a first heavily doped region 32 and a second heavily doped region 34 in the semiconductor substrate 22 on both sides of the gate 38, respectively. The doping concentration of the first heavily doped region 32 and the doping concentration of the second heavily doped region 34 are substantially greater than the doping concentration of the deep well region 26, the doping concentration of the first doping region 28, and the well. The doping concentration of zone 30. At this time, the first trench structure 40 is located between the first heavily doped region 32 and the second heavily doped region 34, and the second trench structure 42 is located at the opposite In the semiconductor substrate 22 on the other side of the gate 38 of a trench structure 40. Additionally, an ion implantation process P6 can be further performed to form at least one third heavily doped region 36 in the well region 30, the third heavily doped region 36 having the same second conductivity type as the well region 30. In the present embodiment, the first heavily doped region 32 includes a common drain, the second heavily doped region 34 includes a source, and the third heavily doped region 36 can be used to regulate the potential of the well region 30. So far, the structure of the semiconductor device 56 such as VDMOS is completed.

As shown in FIG. 10, in another preferred embodiment, the semiconductor device 56 of the present invention may additionally form a shallow trench isolation 58 around it to provide an insulating effect of the semiconductor device 56, avoiding the semiconductor device 56 and other semiconductor substrates. The components (not shown) interfere with each other. The formation of the shallow trench isolation 58 can be integrated into the processes of the first trench structure 40 and the second trench structure 42, that is, the shallow trench isolation 58, the first trench structure 40, and the second trench structure 42 can be simultaneously completed, Save production costs, but not limited to this. One of the depth d4 of the shallow trench isolation 58 is substantially smaller than the depth d1 of the first trench structure 40 and the depth d2 of the second trench structure 42.

In addition to the first trench structure and the second trench structure, the semiconductor device of the present invention further forms a low-resistivity conductive region of an annular solid structure at the junction between the deep well region and the first doped region, and the conductive region resists The rate is less than the characteristics of the adjacent deep well region and the first doped region, so that the carrier is more likely to flow between the first heavily doped region and the buried layer to improve the on-resistance and power consumption of the device.

The above description is only a preferred embodiment of the present invention, and the patent application scope according to the present invention Equivalent changes and modifications made are intended to be within the scope of the present invention.

20‧‧‧Semiconductor device

22‧‧‧Semiconductor substrate

24‧‧‧ buried layer

26‧‧‧Shenjing District

28‧‧‧First doped area

30‧‧‧ Well Area

32‧‧‧First heavily doped area

34‧‧‧Second heavily doped area

36‧‧‧ Third heavily doped area

38‧‧‧ gate

40‧‧‧First ditches structure

40’‧‧‧First Ditch

42‧‧‧Second ditches structure

42’‧‧‧Second Ditch

44‧‧‧ gate dielectric layer

46‧‧‧gate electrode

48‧‧‧ cover

50‧‧‧ Sidewall

52‧‧‧ epitaxial layer

54‧‧‧ patterned mask layer

56‧‧‧Semiconductor device

58‧‧‧Shallow trench isolation

60‧‧‧mask layer

62‧‧‧Conducting area

70‧‧‧Oxide cushion

72‧‧‧Nitride blanket

74‧‧‧Oxide layer

76‧‧‧Photoresist layer

78‧‧‧ openings

80‧‧‧metal layer

D1, d2, d4‧‧ depth

P1, P2, P3, P5, P6‧‧‧ ion implantation process

R1, R2, R3‧‧‧ path

1 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention.

2 to 10 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.

20‧‧‧Semiconductor device

22‧‧‧Semiconductor substrate

24‧‧‧ buried layer

26‧‧‧Shenjing District

28‧‧‧First doped area

30‧‧‧ Well Area

32‧‧‧First heavily doped area

34‧‧‧Second heavily doped area

36‧‧‧ Third heavily doped area

38‧‧‧ gate

40‧‧‧First ditches structure

42‧‧‧Second ditches structure

44‧‧‧ gate dielectric layer

46‧‧‧gate electrode

48‧‧‧ cover

50‧‧‧ Sidewall

62‧‧‧Conducting area

R1, R2, R3‧‧‧ path

Claims (22)

A semiconductor device comprising: a semiconductor substrate; a buried layer disposed in the semiconductor substrate; a deep well region having a first conductivity type disposed in the semiconductor substrate, wherein the deep well region is located on the buried layer; a first doped region having the first conductivity type is disposed in the deep well region, and the first doped region contacts the buried layer; a conductive region having the first conductivity type is adjacent to the first doped region a doped region, wherein a dopant concentration of the conductive region is higher than a dopant concentration of the first doped region; a first heavily doped region having the first conductivity type is disposed in the first doped region; a well region having a second conductivity type disposed in the deep well region; a second heavily doped region having the first conductivity type disposed in the well region; and a gate disposed on the first heavily doped region a semiconductor substrate between the impurity region and the second heavily doped region; a first trench structure disposed in the semiconductor substrate on the gate side, and the first trench structure contacting the buried layer; a second trench structure disposed on the gate opposite to the first trench structure The semiconductor substrate, wherein the second trench depth is substantially greater than the depth of the structure of the buried layer. The semiconductor device of claim 1, wherein the conductive region is an annular solid structure. The semiconductor device of claim 1, wherein the conductive region has a doping concentration gradient, and the doping concentration is from the interface between the conductive region and the first doped region to the conductive region and the deep well region. The direction of the interface is decreasing. The semiconductor device of claim 1, wherein the conductive region is disposed between the first trench structure and the first doped region. The semiconductor device of claim 1, wherein the first trench structure is disposed between the first doped region and the well region. The semiconductor device of claim 1, wherein the semiconductor substrate further comprises an epitaxial layer, and the deep well region is disposed in the epitaxial layer. The semiconductor device of claim 1, wherein the width of the first trench structure is substantially smaller than the width of the second trench structure. The semiconductor device according to claim 1, wherein the first conductivity type is one of an N type or a P type, and the second conductivity type is different from the first conductivity type. A semiconductor device comprising: a semiconductor substrate; a buried layer disposed in the semiconductor substrate; a deep well region having a first conductivity type disposed in the semiconductor substrate, wherein the deep well region is located on the buried layer; a first doped region having the first conductivity type disposed in the deep well region, and The first doped region contacts the buried layer; a conductive region comprising a metal layer adjacent to the first doped region; and a first heavily doped region having the first conductivity type disposed at the first doping region a well region having a second conductivity type disposed in the deep well region; a second heavily doped region having the first conductivity type disposed in the well region; a gate disposed at the a semiconductor substrate between the first heavily doped region and the second heavily doped region; a first trench structure disposed in the semiconductor substrate on the gate side, and the first trench structure contacts the buried And a second trench structure disposed in the semiconductor substrate opposite to the gate of the first trench structure, wherein the second trench structure has a depth substantially greater than a depth of the buried layer. The semiconductor device of claim 9, wherein the conductive region is an annular three-dimensional structure. The semiconductor device of claim 9, wherein the conductive region comprises a metal halide. The semiconductor device of claim 9, wherein the conductive region has A metal telluride concentration gradient, and the metal telluride concentration decreases from the interface between the conductive region and the first doped region to the interface between the conductive region and the deep well region. The semiconductor device of claim 9, wherein the conductive region is disposed between the first trench structure and the first doped region. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well region having a first conductivity type in the semiconductor substrate, and the deep well region is located in the buried Forming an opening in the deep well region, wherein a portion of the buried layer is exposed at the bottom of the opening; forming a conductive region on the sidewall of the opening; filling the opening with a first conductivity type a first doped region; forming at least one first trench structure in the deep well region, wherein the first trench structure extends into the buried layer; and forming at least one second trench structure in the semiconductor substrate, wherein the first doped region One of the depths of the two trench structures is substantially larger than one of the buried layers. The method of fabricating a semiconductor device according to claim 14, wherein the step of forming the conductive region is selected from at least one of the following steps: forming an epitaxial layer on a sidewall of the opening; Forming a metal telluride layer on the sidewall of the opening; forming a metal layer on the sidewall of the opening; performing an ion implantation process on the sidewall of the opening; performing a gas diffusion process on the sidewall of the opening; A dopant source layer fills the opening and performs a thermal drive in process. The method of fabricating a semiconductor device according to claim 14, wherein the composition of the conductive region comprises a metal halide or a dopant having the first conductivity type. The method of fabricating a semiconductor device according to claim 14, wherein the conductive region has a doping concentration gradient, and the doping concentration is from the interface between the conductive region and the first doped region to the conductive region The direction of the interface of the deep well area is decreasing. The method of fabricating a semiconductor device according to claim 14, wherein the conductive region has a metal telluride concentration gradient, and the metal telluride concentration is from the interface between the conductive region and the first doped region to the conductive The direction of the interface between the area and the deep well area decreases. The semiconductor device of claim 14, wherein the conductive region is disposed between the first trench structure and the first doped region. The method of fabricating a semiconductor device according to claim 14, wherein the width of the first trench structure is substantially smaller than the width of the second trench structure. The method of fabricating the semiconductor device of claim 14, further comprising: forming at least one gate on the semiconductor substrate, and the gate overlap is between the first trench structure and the second trench structure Part of the deep well region; forming at least one first heavily doped region in the first doped region, and the first heavily doped region has the first conductivity type; and forming at least one second heavily doped region In the well region, the second heavily doped region has the first conductivity type. The method of fabricating a semiconductor device according to claim 14, wherein the first trench structure is located between the first heavily doped region and the second heavily doped region.