CN103035728B - Be applied to LDMOS device and the manufacture method thereof of RF application - Google Patents
Be applied to LDMOS device and the manufacture method thereof of RF application Download PDFInfo
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Abstract
This application discloses a kind of LDMOS device being applied to RF application, adopt silicon-on-insulator, described silicon-on-insulator is made up of bottom silicon from bottom to top, insulating barrier, top layer silicon; Described LDMOS device is positioned in described top layer silicon.Disclosed herein as well is its manufacture method.Due to by device manufacture on silicon-on-insulator, the application while acquisition high-breakdown-voltage, can reduce the parasitic capacitance between source electrode and drain electrode.
Description
Technical field
The application relates to a kind of semiconductor device, particularly relates to a kind of LDMOS device being applied to RF application.
Background technology
Radio frequency LDMOS (laterally diffused MOS transistor) device is the conventional device being applied to radio-frequency (RF) base station and broadcasting station, and its performance index pursued comprise high-breakdown-voltage, low on-resistance and low parasitic capacitance etc.
Refer to Fig. 6, this is a kind of existing radio frequency LDMOS device.For N-shaped radio frequency LDMOS device, p-type heavy doping bottom silicon 1 has p-type light dope top layer silicon 2.There is the N-shaped heavy doping source region 8 of contacts side surfaces successively, p-type channel doping district 7 and N-shaped drift region 3 in top layer silicon 2.There is N-shaped heavy doping drain region 7 in drift region 3.There is successively gate oxide 4 and polysilicon gate 5 on channel doping district 7 and drift region 3.Directly over polysilicon gate 5 and directly over part drift region 3, there is silica 10.There is grid masking layer (G-shield) 11 above partial oxidation silicon 10.Grid masking layer 11 at least to be separated by silica 10 and part drift region 3 above.Sink structures 12 penetrates source region 8, top layer silicon 2 downwards from surface, source region 8, and arrives among bottom silicon 1.
In this existing radio frequency LDMOS device, described grid masking layer 11 is metal or N-shaped heavily doped polysilicon, its RESURF (Reduced SURfsce Field, reducing surface field) effect can increase the puncture voltage of device effectively, effectively reduces the parasitic capacitance between grid and drain electrode simultaneously.So just, the doping content of drift region 3 suitably can be increased thus the conducting resistance of reduction device.
But the major issue that grid masking layer 11 brings is the increase in the parasitic capacitance between source electrode 8 and drain electrode 9, and the height of size to the power added efficiency (PAE) of device of this parasitic capacitance is most important.Parasitic capacitance between described source electrode 8 and drain electrode 9 mainly comes from the junction capacitance between drain electrode 9 and bottom silicon 1 and the junction capacitance between drift region 3 and channel doping district 7.Although longer grid masking layer 11 can obtain higher device electric breakdown strength, also make the parasitic capacitance between source electrode and drain electrode significantly increase simultaneously, make the power added efficiency of device occur declining, affect the radio-frequency performance of device.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of LDMOS device being applied to RF application, while acquisition high-breakdown-voltage, can reduce the parasitic capacitance between source electrode and drain electrode.For this reason, the application also to provide described in be applied to the manufacture method of the LDMOS device of RF application.
For solving the problems of the technologies described above, the LDMOS device that the application is applied to RF application adopts silicon-on-insulator, and described silicon-on-insulator is made up of bottom silicon from bottom to top, insulating barrier, top layer silicon; Described LDMOS device is positioned in described top layer silicon; Above the polysilicon gate of described LDMOS device He above part drift region, there is the 3rd silica; The top of the 3rd part or all of silica has the grid masking layer of metal or polysilicon material.
The described manufacture method being applied to the LDMOS device of RF application is: in the top layer silicon of the silicon-on-insulator be made up of bottom silicon from bottom to top, insulating barrier, top layer silicon, manufacture described LDMOS device; Described LDMOS device first forms drift region during fabrication, form polysilicon gate again, also above polysilicon gate and above the drift region of part, form the 3rd silica, above the 3rd part or all of silica, also form the grid masking layer of metal or polysilicon material.
The application's radio frequency LDMOS device is owing to changing base material into silicon-on-insulator by body silicon, and tool has the following advantages:
One, is produced on radio frequency LDMOS device in top layer silicon, and the body silicon overcoming traditional devices has the shortcoming of larger body capacitance, reduce further the parasitic capacitance that device is total.
Its two, top layer silicon is thinner, thus the junction capacitance effectively reduced between source electrode and bottom silicon and draining and junction capacitance between bottom silicon, eventually reduces the parasitic capacitance between source electrode and drain electrode.
They are three years old, by controlling the thickness of top layer silicon suitably, channel doping district and drift region can be made to be complete depletion type, the junction area in drift region and channel doping district can minimize by this, thus the parasitic capacitance farthest reduced between the source electrode of device and drain electrode, improve the power added efficiency of device.
Accompanying drawing explanation
Fig. 1 a ~ Fig. 1 c is the schematic diagram of the drift region of three kinds of radio frequency LDMOS device;
Fig. 2 is parasitic capacitance between the source electrode of three kinds of radio frequency LDMOS device and drain electrode and the relation curve of drain terminal voltage;
Fig. 3 a ~ Fig. 3 j is each step schematic diagram of the manufacture method one of the application's radio frequency LDMOS device;
Fig. 4 a, Fig. 4 b are the part steps schematic diagrames of the manufacture method two of the application's radio frequency LDMOS device;
Fig. 5 a, Fig. 5 b are the schematic diagrames of the application's complete depletion type radio frequency LDMOS device;
Fig. 6 is the schematic diagram of existing radio frequency LDMOS device.
Description of reference numerals in figure:
1 is bottom silicon; 2 is top layer silicon; 3 is drift region; 4 is gate oxide; 5 is polysilicon gate; 6 is photoresist; 7 is channel doping district; 8 is source region; 9 is drain region; 10 is silica; 11 is grid masking layer; 12 is sink structures; 100 is insulating barrier.
Embodiment
Refer to Fig. 3 i, this is the embodiment one of the radio frequency LDMOS device described in the application.For N-shaped radio frequency LDMOS device, the bottom silicon 1 stacked gradually from bottom to top, insulating barrier 100 and top layer silicon 2 constitute silicon-on-insulator (SOI, silicon on insulator), wherein the doping content of bottom silicon 1 is greater than the doping content of top layer silicon 2.Bottom silicon 1 can be identical doping type with top layer silicon 2, may also be different doping type.Bottom silicon 1 is such as attached most importance to doped silicon substrate, and insulating barrier 100 is such as silica, and top layer silicon 2 is low-doped silicon substrate or epitaxial loayer in being such as.There is the N-shaped heavy doping source region 8 of contacts side surfaces successively, p-type channel doping district 7 and N-shaped drift region 3 in top layer silicon 2.There is N-shaped heavy doping drain region 9 in drift region 3.There is successively gate oxide 4 and polysilicon gate 5 on channel doping district 7 and drift region 3.There is directly over polysilicon gate 5 and directly over part drift region 3 one piece of silica 10 continuously.There is continuous print one piece of grid masking layer (G-shield) 11 above part or all of silica 10.Grid masking layer 11 at least to be separated by silica 10 and part drift region 3 above.Sink structures 12 penetrates source region 8, top layer silicon 2, insulating barrier 100 downwards from surface, source region 8, and arrives among bottom silicon 1.Metal silicide is formed on source region 8 and sink structures 12, polysilicon gate 5, grid masking layer 11 and drain region 9.Or source region 8 and sink structures 12 also can be drawn from silicon chip back side with metal silicide.
Refer to Fig. 3 j, this is the embodiment two of the radio frequency LDMOS device described in the application.The difference of itself and embodiment one is only: sink structures 12 penetrates source region 8, top layer silicon 2 downwards from surface, source region 8, and among the upper surface arriving at insulating barrier 100 or insulating barrier 100.Source region 8 and sink structures 12 can only be drawn from front side of silicon wafer with metal silicide.
If p-type radio frequency LDMOS device, the doping type of each part mentioned above structure is become on the contrary.
Compared with existing radio frequency LDMOS device, the main innovation of the application is: use silicon-on-insulator as base material, instead of traditional body silicon.In SOI, the thickness of insulating barrier 100 determined by the puncture voltage of device, and the thicker then puncture voltage of insulating barrier 100 is higher.If insulating barrier 100 adopts silica, then its thickness (unit is micron) at least should be set to 1/20th of puncture voltage (unit is volt), such as, puncture voltage for reaching 20V then require insulating barrier 100 to be at least silica that thickness is 1 μm.Top layer silicon 2 is thinner, thus the junction capacitance effectively reduced between source electrode 8 and bottom silicon 1 and the junction capacitance drained between 9 and bottom silicon 1.By controlling the thickness of this top layer silicon 2 suitably, channel doping district 7 and drift region 3 can be made to be complete depletion type, the junction area of drift region 3 with channel doping district 7 can minimize by this, thus the parasitic capacitance farthest reduced between the source electrode 8 of device and drain electrode 9, improve the power added efficiency of device.
Fig. 1 a ~ Fig. 1 c indicates the drift region of three kinds of radio frequency LDMOS device.Wherein, Fig. 1 a is the traditional radio frequency LDMOS device shown in Fig. 6, and Fig. 1 b is the radio frequency LDMOS device of Fig. 3 i or the application shown in Fig. 3 j, and Fig. 1 c is the complete depletion type radio frequency LDMOS device of Fig. 5 a or the application shown in Fig. 5 b.Obviously, by reducing the thickness of top layer silicon 2, drift region 3 can be made to occupy top layer silicon 2 completely in the vertical.
Refer to Fig. 2, this is the relation curve of three kinds of radio frequency LDMOS device.Wherein abscissa is the bias voltage of drain terminal, and ordinate is the parasitic capacitance between the source electrode of device and drain electrode.Obviously, the parasitic capacitance between the source electrode of the application's radio frequency LDMOS device and drain electrode is comparatively close, and they are all markedly inferior to the parasitic capacitance between the source electrode of existing radio frequency LDMOS device and drain electrode.
The manufacture method one of the radio frequency LDMOS device described in the application is as described below, for N-shaped radio frequency LDMOS device:
1st step, refers to Fig. 3 a, and the bottom silicon 1 stacked gradually from bottom to top, insulating barrier 100 and top layer silicon 2 constitute SOI.
If top layer silicon 2 is p-type doping, then adopts photoetching process to utilize photoresist as masking layer, and with one or many implant n-type ion, in top layer silicon 2, form N-shaped drift region 3.
If top layer silicon 2 is N-shaped doping, then can directly using the drift region 3 of top layer silicon 2 as device.Or, photoetching process also can be adopted to utilize photoresist as masking layer, and with one or many implant n-type ion, in top layer silicon 2, form N-shaped drift region 3.
2nd step, refers to Fig. 3 b, first goes out silica 4 with thermal oxidation technology in the superficial growth of silicon materials (comprising top layer silicon 2 and drift region 3), then at whole silicon chip surface depositing polysilicon 5.Then polysilicon 5 is carried out to the ion implantation of N-shaped impurity.N-shaped impurity is preferably phosphorus, and the dosage of ion implantation is preferably 1 × 10
15~ 1 × 10
16atom per square centimeter.
3rd step, refers to Fig. 3 c, adopts photoetching and etching technics, and silica 4 and polysilicon 5 are formed the top layer silicon 2 that a window A, this window A only expose part.The top layer silicon 2 of whole drift region 3 and remainder still oxidized silicon 4 and polysilicon 5 and photoresist 6 covered.
4th step, refers to Fig. 3 d, to top layer silicon 2 implanted with p-type impurity in window A, is preferably boron, thus forms the channel doping district 7 contacted with the side of drift region 3.During ion implantation, photoresist 6 is also as masking layer, removes photoresist 6 again after ion implantation.
Preferably, ion implantation has certain angle of inclination, thus the easier below to silica 4, groove doped region 7 is extended, and contacts with the side of drift region 3.
Preferably, ion implantation is carried out several times, each Implantation Energy and implantation dosage incomplete same.Wherein, high-octane implantation dosage is higher than low-energy implantation dosage.
5th step, refers to Fig. 3 e, adopts photoetching and etching technics, silica 4 and polysilicon 5 is etched respectively as gate oxide 4 and polysilicon gate 5.A part for gate oxide 4 is above channel doping district 7, and remainder is above drift region 3.
6th step, refers to Fig. 3 f, adopts photoetching process, forms window B and window C using photoresist as masking layer, they lay respectively at gate oxide 4 away from outside that one end of drift region 3, drift region 3 is away from outside that one end of gate oxide 4.The source and drain injection technology of N-shaped impurity is adopted to form source region 8 and drain region 9 respectively to these two windows.Now, channel doping district 7 is contracted to only in the below of gate oxide 4.The dosage that described source and drain is injected is 1 × 10
15on atom per square centimeter.
7th step, refers to Fig. 3 g, at whole wafer deposition one deck silica 10, adopts photoetching and etching technics to etch this layer of silica 10, makes it only remain in the top of the top of polysilicon gate 5 and the exposed surface of drift region 3 continuously.
8th step, refers to Fig. 3 h, in whole wafer deposition layer of metal 11, adopts photoetching and etching technics to carry out etching to this layer of metal 11 and forms grid masking layer (G-shield) 11.Grid masking layer 11 is continuous print one piece, covers on silica 10 partly.Grid masking layer 11 at least to be separated by silica 10 and part drift region 6 above.
Or grid masking layer 11 also can be N-shaped heavily doped polysilicon.Now, the ion implantation of N-shaped impurity can be carried out again by first depositing polysilicon, also can direct deposit N-shaped doped polycrystalline silicon (namely in-situ doped).
9th step, has two kinds of implementations.
The first implementation refers to Fig. 3 i, adopts photoetching and etching technics, in source region 8, etches deep hole.Described deep hole passes through source region 8, top layer silicon 2, insulating barrier 100, and arrives among bottom silicon 1, therefore claims " deeply " hole.In this deep hole, fill metal, be preferably tungsten, form (sinker) structure 12 of sinking.Described deep hole also can change groove structure into.This implementation allows source region 8 and sink structures 12 to draw from front side of silicon wafer or the back side.
The second implementation refers to Fig. 3 j, adopts photoetching and etching technics, etches and portal in source region 8.Source region 8 and top layer silicon 2 are passed through in described hole, and arrive at the upper surface of insulating barrier 100 or arrive among insulating barrier 100.In this hole, fill metal, be preferably tungsten, form (sinker) structure 12 of sinking.Described hole also can change groove structure into.This implementation only allows source region 8 and sink structures 12 to draw from front side of silicon wafer.
The manufacture method two of the radio frequency LDMOS device described in the application is as described below, for N-shaped radio frequency LDMOS device:
1st ' step is to the 2nd ' step is identical to the 2nd step with the 1st step respectively.
3rd ' step, refers to Fig. 4 a, adopts photoetching and etching technics, silica 4 and polysilicon 5 is etched respectively as gate oxide 4 and polysilicon gate 5.A part for gate oxide 4 is above top layer silicon 2, and remainder is above drift region 3.
4th ' step, refers to Fig. 4 b, adopts photoetching process, covers the drift region 3 of polysilicon gate 5 side with photoresist 6.Using photoresist 6 and polysilicon gate 5 as masking layer, to the top layer silicon 2 implanted with p-type impurity of polysilicon gate 5 opposite side, be preferably boron, thus form the channel doping district 7 contacted with the side of drift region 3.
Preferably, ion implantation has certain angle of inclination, thus the easier below to silica 4, groove doped region 7 is extended, and contacts with the side of drift region 3.
Preferably, ion implantation is carried out several times, each Implantation Energy and implantation dosage incomplete same.Wherein, high-octane implantation dosage is higher than low-energy implantation dosage.
5th ' step is to the 8th ' step is identical to the 9th step with the 6th step respectively.
The subsequent technique of above-mentioned two kinds of manufacture methods comprises: in whole wafer deposition layer of metal, then carry out high-temperature thermal annealing, thus forms metal silicide on the surface of metal and silicon metallic surface, metal and polysilicon contact.Metal silicide is distributed on source region 8 and sink structures 12, polysilicon gate 5, grid masking layer 11 and drain region 9.Or when the 9th step adopts the first implementation, source region 8 and sink structures 12 also can be drawn from silicon chip back side with metal silicide.
As p-type radio frequency LDMOS device will be manufactured, the doping type in each for said method step is become on the contrary.Such as: the 2nd step ion implantation p-type impurity, boron is preferably.4th step, the 4th ' step ion implantation N-shaped impurity, be preferably phosphorus or arsenic.
No matter adopt above-mentioned any manufacture method, can by the thickness of thinning top layer silicon 2, and realize the channel doping district 7 of radio frequency LDMOS device and drift region 3 is complete depletion type.Refer to Fig. 5 a, Fig. 5 b, this is two embodiments of complete depletion type radio frequency LDMOS device respectively.Wherein, channel doping district 7 and drift region 3 longitudinally occupy whole top layer silicon 2, and contact with the upper surface of insulating barrier 100.Now, top layer silicon 2 disappears.The parasitic capacitance between source electrode 8 and drain electrode 9 can be reduced so further.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (9)
1. be applied to a LDMOS device for RF application, it is characterized in that: adopt silicon-on-insulator, described silicon-on-insulator is made up of bottom silicon from bottom to top, insulating barrier, top layer silicon; Described LDMOS device is positioned in described top layer silicon; Above the polysilicon gate of described LDMOS device He above part drift region, there is silica; The top of part or all of described silica has the grid masking layer of metal or polysilicon material.
2. the LDMOS device being applied to RF application according to claim 1, also has sink structures; It is characterized in that: described sink structures penetrates source region, top layer silicon, insulating barrier downwards from area surface, and arrive among bottom silicon;
Or described sink structures penetrates source region, top layer silicon downwards from area surface, and among the upper surface arriving at insulating barrier or insulating barrier.
3. the LDMOS device being applied to RF application according to claim 1, also has channel doping district and drift region; It is characterized in that: described channel doping district and drift region directly contact with insulating barrier in the vertical, described top layer silicon disappears, and now described LDMOS device is complete depletion type.
4. the LDMOS device being applied to RF application according to claim 1, is characterized in that: the puncture voltage that described LDMOS device requires is a volt, then the silica of insulating barrier to be thickness be 20/a micron.
5. be applied to a manufacture method for the LDMOS device of RF application, it is characterized in that: in the top layer silicon of the silicon-on-insulator be made up of bottom silicon from bottom to top, insulating barrier, top layer silicon, manufacture described LDMOS device; Described LDMOS device first forms drift region during fabrication, form polysilicon gate again, also above polysilicon gate and above the drift region of part, form silica, above part or all of described silica, also form the grid masking layer of metal or polysilicon material.
6. the manufacture method being applied to the LDMOS device of RF application according to claim 5, is characterized in that, comprise the steps:
1st step, if top layer silicon is the first conduction type, then forms the drift region of the second conduction type in top layer silicon with ion implantation technology;
If top layer silicon is the second conduction type, or using the drift region of top layer silicon as device; Or in top layer silicon, the drift region of the second conduction type is formed with ion implantation technology;
2nd step, goes out silica with thermal oxidation technology in silicon materials superficial growth, is called the second silica, then depositing polysilicon, polysilicon is carried out to the ion implantation of the second conductive type impurity;
3rd step, forms first window with photoetching and etching technics on the second silica and polysilicon, and this first window only exposes the top layer silicon of part;
4th step, in first window with angle of inclination to injecting the first conductive type impurity in top layer silicon, thus form the channel doping district that contacts with the side of drift region;
5th step, etches the second silica and polysilicon respectively as gate oxide and polysilicon gate;
6th step, with source and drain injection technology at gate oxide away from the source region forming the second conduction type outside that one end of drift region, in drift region away from the drain region forming the second conduction type outside that one end of gate oxide;
7th step, whole wafer deposition silica, is called the 3rd silica, adopts photoetching and etching technics to make it only remain in the top of the top of polysilicon gate and the exposed surface of drift region;
8th step, whole wafer deposition layer of metal or polysilicon, form grid masking layer to its etching; Grid masking layer covers on the 3rd part or all of silica;
9th step, etches and passes through source region, top layer silicon, insulating barrier the hole arrived in bottom silicon or groove in source region, fills metal and form sink structures in this hole or groove;
Or, etch in source region and pass through source region, top layer silicon the hole arrived in insulating barrier upper surface or insulating barrier or groove, in this hole or groove, fill metal form sink structures.
7. the manufacture method being applied to the LDMOS device of RF application according to claim 6, is characterized in that, each step becomes:
1st ' step is to the 2nd ' step is identical to the 2nd step with the 1st step respectively;
3rd ' step, etches the second silica and polysilicon respectively as gate oxide and polysilicon gate;
4th ' step, covers the drift region of polysilicon gate side with photoresist, inject the first conductive type impurity to the top layer silicon of polysilicon gate opposite side, thus forms the channel doping district contacted with the side of drift region;
5th ' step is to the 8th ' step is identical to the 9th step with the 6th step respectively.
8. the manufacture method being applied to the LDMOS device of RF application according to claim 6, is characterized in that, in described method the 2nd step, p-type impurity comprises boron, and N-shaped impurity comprises phosphorus or arsenic, and the dosage of ion implantation is 1 × 10
15~ 1 × 10
16atom per square centimeter.
9. the manufacture method being applied to the LDMOS device of RF application according to claim 6, is characterized in that, in described method the 8th step, grid masking layer be at least separated by the 3rd silica and part drift region above.
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|---|---|---|---|---|
| CN1890815A (en) * | 2003-10-03 | 2007-01-03 | 英飞凌科技股份公司 | LDMOS transistor |
| CN101083278A (en) * | 2006-10-25 | 2007-12-05 | 电子科技大学 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
| CN102593170A (en) * | 2011-01-14 | 2012-07-18 | 中国科学院微电子研究所 | Radio frequency LDMOS (Lateral-Double-diffused Metal Oxide Semiconductor) transistor structure based on SOI (Silicon on Insulator) |
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| US8384184B2 (en) * | 2010-09-15 | 2013-02-26 | Freescale Semiconductor, Inc. | Laterally diffused metal oxide semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890815A (en) * | 2003-10-03 | 2007-01-03 | 英飞凌科技股份公司 | LDMOS transistor |
| CN101083278A (en) * | 2006-10-25 | 2007-12-05 | 电子科技大学 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
| CN102593170A (en) * | 2011-01-14 | 2012-07-18 | 中国科学院微电子研究所 | Radio frequency LDMOS (Lateral-Double-diffused Metal Oxide Semiconductor) transistor structure based on SOI (Silicon on Insulator) |
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