CN102593170A - Radio frequency LDMOS transistor structure based on silicon on insulator - Google Patents
Radio frequency LDMOS transistor structure based on silicon on insulator Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 45
- 239000010703 silicon Substances 0.000 title claims abstract description 45
- 239000012212 insulator Substances 0.000 title claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 144
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 34
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 60
- 150000002500 ions Chemical class 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000002459 sustained effect Effects 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 7
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Abstract
The invention relates to a radio frequency LDMOS transistor structure based on silicon on an insulator, belonging to the field of semiconductor devices. The radio-frequency LDMOS transistor structure comprises a back gate metal layer, bottom silicon, a buried oxide layer, top silicon, a positive gate oxide layer, a positive gate polycrystalline silicon layer, a side wall region, a source region, a drain region, a P well region, an N drift region, a silicide layer, an isolation oxide region, a partial isolation oxide region and a body contact region. The LDMOS transistor is manufactured on the SOI substrate, a silicide on a drift region is masked by utilizing a partial isolation oxide region in the silicification process, and a similar RESURF structure can be formed, so that the breakdown voltage of the LDMOS can be obviously improved, the electric leakage when the device is turned off and the on-resistance when the device is turned on are reduced; meanwhile, a low-barrier body contact region is formed by utilizing a partial isolation oxide region and a heavily doped region of the same type as the N well region, so that the body extraction efficiency can be improved, and the limitation of the width-to-length ratio of the device is avoided.
Description
Technical field
The present invention relates to a kind of silicon-on-insulator (SOI) device, relate in particular to a kind of radio frequency ldmos transistor structure, belong to field of semiconductor devices based on silicon-on-insulator.
Background technology
Scaled down along with device; Performances such as the frequency of cmos device, noise continue to improve; Become a serious day by day problem but its power-performance is degenerated, breakdown potential is forced down the principal element that becomes the extensive use in the radio-frequency power field of restriction CMOS technology with the power-performance difference.Power MOS (Metal Oxide Semiconductor) device has just in time remedied the deficiency of conventional cmos device power-performance; It has good radio-frequency power performance, and is big like linear dynamic range, linear gain is high, power output is big, power density is high, be convenient to device inside forms input and output match circuit etc., and the existence of high resistant drift region has improved puncture voltage; Make the parasitic capacitance between drain-source the two poles of the earth be able to reduce; And technology is succinct, and is with low cost, well is compatible with CMOS technology.At present, along with popularizing gradually of 1.8GHz～2.2GHz PCS Personal Communications System, base station utmost point power amplifier presses for low cost, high linearity, high-gain, powerful RF power transistor.LDMOS (Lateral-Double-diffused) MOSFET satisfies this demand; Be widely used in radio-frequency power amplifier (below the 2GHz); It both can be made category-A in the smaller power level and use; Also can make the AB class and use, become the main flow of mobile communication base station power amplifier element, and get into the portable terminal application in high-power level.Power amplifier in GSM and the mobile phone needs the RF power transistor of excellent performance; And in all successful use of systems such as wideband frequency modulation emitter, TV and radio emission machine, airborne transponder RF LDMOS, the performance of system is greatly improved; Silicon RF LDMOS power transistor is the radio-frequency power device that a kind of market demand is huge, development prospect is wide, and each big semiconductor manufacturer of the world competitively conducts a research and develops, and the LDMOS new product continues to bring out.
Body silicon LDMOS has the high output capacitance that changes along with drain voltage; This can reduce power efficiency and gain; Especially can make the design of output coupling more difficult, in addition the complete electricity isolation between the logical integrated circuit of also realizing high-tension power device and low-voltage on the body silicon substrate than difficulty.And SOI LDMOS not only has good full dielectric isolation performance, less parasitic capacitance and leakage current; Eliminated crosstalking and latch-up that substrate brings simultaneously, and manufacturing LDMOS power device can obtain higher power gain and bandwidth on the SOI substrate.The appearance of SOI technology just; Make the high-quality passive device of on high resistant Si substrate, making with the CMOS technical compatibility become possibility; And can further reduce capacitance to substrate coupling and substrate cross-talk; In addition, buried oxidation layer has also reduced the capacitive coupling to substrate with the existence of full dielectric isolation, can increase the power added efficiency of device.But because the inherent shortcoming that itself exists, as be vulnerable to the influence of floater effect, self-heating effect and ionization total dose irradiation, also limited the SOI technology and in RF application, used widely.
Summary of the invention
The present invention is directed to the deficiency that the SOI technology can not broader applications in RF application, a kind of radio frequency ldmos transistor structure based on silicon-on-insulator is provided.
The technical scheme that the present invention solves the problems of the technologies described above is following: a kind of radio frequency ldmos transistor structure based on silicon-on-insulator; Comprise the bottom silicon of carrying on the back the grid metal level, being arranged at said back of the body grid metal level; Be arranged at the buried oxidation layer on the said bottom silicon; Be arranged at the first isolation oxide district, top layer silicon and the second isolation oxide district on the said buried oxidation layer, said top layer silicon is characterized in that between the said first isolation oxide district and the second isolation oxide district; Said top layer silicon comprises a N well region, P well region and the 2nd N well region; A said N well region is between said first isolation oxide district and P well region, and said P well region is between a said N well region and the 2nd N well region, and said the 2nd N well region is between the said P well region and the second isolation oxide district;
A said N well region is the mesa structure with first table top and second table top; Said first table top is provided with first drain region; Said first drain region is provided with the first drain region silicide layer; Said second table top is provided with a N drift region, and a said N drift region is provided with first isolation oxide district, and said first isolation oxide district is provided with the first side wall district and the first positive gate polysilicon layer;
Said the 2nd N well region is the mesa structure with first table top and second table top; Said first table top is provided with second drain region; Said second drain region is provided with the second drain region silicide layer; Said second table top is provided with the 2nd N drift region, and said the 2nd N drift region is provided with second portion isolation oxide district, and said second portion isolation oxide district is provided with the 3rd side wall district and the second positive gate polysilicon layer;
Said P well region is the mesa structure with first table top, second table top, the 3rd table top, the 4th table top and the 5th table top; Said first table top is provided with the first positive gate oxide; The top of the said first positive gate oxide is provided with the first positive gate polysilicon layer and the second side wall district, and the top of the said first positive gate polysilicon layer is provided with the first positive gate polysilicon thing layer; Said second table top is provided with first source region and third part isolation oxide district, and the top in said first source region is provided with the first source region silicide layer; Said the 3rd table top is provided with the body contact zone, and the top of said body contact zone is provided with body contact zone silicide layer; Said the 4th table top is provided with second source region and the 4th part isolation oxide district, and the top in said second source region is provided with the second source region silicide layer; Said the 5th table top is provided with the second positive gate oxide, the top of the said second positive gate oxide be provided with the second positive gate polysilicon layer and with the 4th side wall district, the top of the said second positive gate polysilicon layer is provided with the second positive gate polysilicon thing layer.
On the basis of technique scheme, the present invention can also do following improvement.
Further, the height of second table top of a said N well region is less than the height of first table top of a said N well region, and first table top of a said N well region is provided with near the first isolation oxide district, and second table top of a said N well region is provided with near the P well region; The height of second table top of said the 2nd N well region is less than the height of first table top of said the 2nd N well region; First table top of said the 2nd N well region is provided with near the second isolation oxide district, and second table top of said the 2nd N well region is provided with near the P well region.
Further; In said P well region; Said first table top and the 5th table top are positioned at the sustained height place; Said second table top and the 4th table top are positioned at the sustained height place, and said second table top and the 4th table top are between first table top and the 5th table top, and the height of said second table top and the 4th table top is less than the height of said first table top and the 5th table top; Said the 3rd table top is between second table top and the 4th table top, and the height of said the 3rd table top is less than the height below of said second table top and the 4th table top.
Further, first table top in the said N well region, first table top in the 2nd N well region and second table top in the P well region, the 4th table top all are positioned at the sustained height place; Second table top in the said N well region, second table top in the 2nd N well region and the 3rd table top in the P well region all are positioned at the sustained height place.
Further, said first source region and the first source region silicide layer are arranged in the side of said P well region second table top near first table top, and said third part isolation oxide district is arranged in the side of said P well region second table top near the 3rd table top; Said second source region and the second source region silicide layer are arranged in the side of said P well region the 4th table top near the 5th table top, and said the 4th part isolation oxide district is arranged in the side of said P well region the 4th table top near the 3rd table top.
Further; Said first drain region, second drain region, the first positive gate polysilicon layer, the second positive gate polysilicon layer, first source region, second source region, body are equipped with contact hole on the contact zone; Said first drain region and second drain region are made as a whole drain electrode and are connected to peripheral circuit through contact hole and metal interconnected; The said first positive gate polysilicon layer and the second positive gate polysilicon layer are made as a whole gate electrode and are connected to peripheral circuit through contact hole and polysilicon interconnection; Said first source region and second source region are made as a whole source electrode and are connected to peripheral circuit through contact hole and metal interconnected.
Further, the doping type of said top layer silicon and bottom silicon is that P type semiconductor mixes, and is light dope; The doping type of a said N well region and the 2nd N well region is that N type semiconductor mixes, and is light dope; The doping type of said P well region is that P type semiconductor mixes, and is light dope; The doping type of a said N drift region and the 2nd N drift region is that N type semiconductor mixes, and is light dope; The doping type in said first drain region, second drain region, the first positive gate polysilicon layer, the second positive gate polysilicon layer, first source region, second source region is that N type semiconductor mixes, and is heavy doping; Said body contact zone doping type is that P type semiconductor mixes, and is heavy doping; The doping type of a said N drift region, the 2nd N drift region is that N type semiconductor mixes, and is light dope; The said first side wall district, the second side wall district, the 3rd side wall district and the 4th side wall district are silicon nitride; The said first isolation oxide district, the second isolation oxide district, first isolation oxide district, second portion isolation oxide district, third part isolation oxide district and the 4th part isolation oxide district are silicon dioxide; The said first drain region silicide layer, the second drain region silicide layer, the first source region silicide layer, the second source region silicide layer, body contact zone silicide layer, the first positive gate polysilicon thing layer, the second positive gate polysilicon thing layer are cobalt silicide; The said first positive gate oxide and the second positive gate oxide are silicon dioxide.
Further, all the thickness with said top layer silicon is identical for the thickness in the said first isolation oxide district and the second isolation oxide district.
Further; Said first isolation oxide district, second portion isolation oxide district, third part isolation oxide district are identical with the thickness in the 4th part isolation oxide district; And the thickness that said first isolation oxide district is positioned at the first N well region equals the thickness that said second portion isolation oxide district is positioned at the second N well region, and the thickness that said third part isolation oxide district is positioned at the P well region equals the thickness that said the 4th part isolation oxide district is positioned at the P well region.
Further; Said first isolation oxide district is positioned at the thickness of the thickness of the first N well region less than said top layer silicon; And said first isolation oxide district is positioned at the thickness of the thickness of the first N well region upper surface less than the said first positive gate polysilicon layer, and said third part isolation oxide district is positioned at the thickness of the thickness of P well region less than said top layer silicon.
Further, the width in said third part isolation oxide district is identical with the width in the 4th part isolation oxide district, and greater than one times channel length and less than ten times channel length; And the width in said first isolation oxide district is identical with the width in second portion isolation oxide district.
Further, the thickness of a said N drift region is identical with the thickness of said the 2nd N drift region, and the thickness that equals said top layer silicon deducts the thickness in said first isolation oxide district; And the width of a said N drift region is identical with said the 2nd N drift region width, and equals the width in said first isolation oxide district.
Further, it is identical with the ion injection degree of depth in second source region that the ion in said first source region injects the degree of depth, and less than said top layer silicon thickness; It is identical with the thickness of said top layer silicon that the ion of said body contact zone injects the degree of depth.
Further; The width that the said first positive gate polysilicon layer covers first's isolation oxide district part equals the width of the second positive gate polysilicon layer covering second portion isolation oxide district part, and greater than 1/2 times channel length and less than the width in first isolation oxide district.
The invention has the beneficial effects as follows: the radio frequency ldmos transistor structure that the present invention is based on silicon-on-insulator is made in ldmos transistor on the SOI substrate; Utilize part isolation oxide district in silicatization process, to shelter the silicide on the drift region; And can type of formation RESURF structure; The influence of floater effect can be effectively suppressed, static state and dynamic breakdown performance can be significantly improved simultaneously, the conducting resistance when electric leakage when the reduction device turn-offs and unlatching SOI LDMOS device performance; Utilize part isolation oxide district simultaneously and form low potential barrier body contact zone with the heavily doped region of N well region homotype; Can improve the body ejection efficiency, and not limited by the device breadth length ratio, manufacture process and SOI CMOS process compatible; Can effectively improve integrated level, reduce production costs and technology difficulty.
Description of drawings
Fig. 1 is the front view of the embodiment of the invention based on the radio frequency ldmos transistor structure of silicon-on-insulator;
Fig. 2 is the vertical view of the embodiment of the invention based on the radio frequency ldmos transistor structure of silicon-on-insulator;
Fig. 3 is the cross-sectional view one of Fig. 2 along the A-A direction;
Fig. 4 is the cross-sectional view two of Fig. 2 along the A-A direction;
Fig. 5 is the breakdown characteristic sketch map of the embodiment of the invention based on the radio frequency ldmos transistor of silicon-on-insulator;
Fig. 6 is the frequency characteristics sketch map of the embodiment of the invention based on the radio frequency ldmos transistor of silicon-on-insulator.
Embodiment
Below in conjunction with accompanying drawing principle of the present invention and characteristic are described, institute gives an actual example and only is used to explain the present invention, is not to be used to limit scope of the present invention.
Shown in Fig. 1 and 2, through simultaneously first doped region 37 and 39 overlay areas of second doped region being carried out the doping that ion injects synchronous formation the one N well region 4 and the 2nd N well region 34; Ion is carried out in 38 overlay areas of the 3rd doped region inject the doping that forms P well region 18.First doped region 37 and the 3rd doped region 38, second doped region 38 and the 3rd doped region 38 can not overlap.Can obtain Fig. 3 and the radio frequency ldmos transistor structural profile sketch map based on silicon-on-insulator shown in Figure 4 along A-A direction rip cutting among Fig. 2.
In this specific embodiment, provided by the present invention that a kind of radio frequency ldmos transistor structure based on silicon-on-insulator is followed successively by top layer silicon, buried oxidation layer 3 and bottom silicon 2 from top to bottom, this ldmos transistor structure comprises:
Be arranged at and be followed successively by a N well region 4, P well region 18 and the 2nd N well region 34 in the top layer silicon from left to right; Be arranged at first drain region 6 in the N well region 4, be arranged at the first drain region silicide layer 7 of first drain region, 6 upper surfaces; Be arranged at the first isolation oxide district 5 of first drain region, 6 one sides, and the first isolation oxide district 9 that is arranged at first drain region, 6 opposite sides, be arranged at the first light dope N drift region 8 of 9 bottoms, first isolation oxide district; Be arranged at second drain region 32 in the 2nd N well region 34, be arranged at the second drain region silicide layer 31 of second drain region, 32 upper surfaces; Be arranged at the second isolation oxide district 33 of second drain region, 32 1 sides, and the second portion isolation oxide district 29 that is arranged at second drain region, 32 opposite sides, be arranged at the second light dope N drift region 30 of 29 bottoms, second portion isolation oxide district; Be arranged at the first positive gate oxide 10 and the second positive gate oxide 28 of P well region 18 upper surfaces; Be arranged at the first positive gate polysilicon layer 12 on first positive gate oxide 10 upper surfaces and first isolation oxide district 9 upper surface at least a portion, be arranged at the first positive gate polysilicon thing layer 13 of first positive gate polysilicon layer 12 upper surface; Be arranged at the first side wall district 11 of first positive gate polysilicon layer 12 1 side, and the second side wall district 14 that is arranged at first positive gate polysilicon layer 12 opposite side; Be arranged at the second positive gate polysilicon layer 26 on second positive gate oxide 28 upper surfaces and second portion isolation oxide district 29 upper surface at least a portion, be arranged at the second positive gate polysilicon thing layer 25 of second positive gate polysilicon layer 26 upper surface; Be arranged at the 3rd side wall district 27 of second positive gate polysilicon layer 26 1 side, and the 4th side wall district 24 that is arranged at second positive gate polysilicon layer 26 opposite side; Be arranged at first source region 15 of P well region 18 inside near first positive gate oxide 10 1 sides; Be arranged at the first source region silicide layer 16 of first source region, 15 upper surfaces, and be arranged at the third part isolation oxide district 17 of 15 next doors, first source region towards second positive gate oxide 28 1 sides; Be arranged at second source region 23 of P well region 18 inside near second positive gate oxide 28 1 sides; Be arranged at the second source region silicide layer 22 of second source region, 23 upper surfaces, and be arranged at the four part isolation oxide district 21 of 23 next doors, second source region towards first positive gate oxide 10 1 sides; Be arranged at the body contact zone 19 between third part isolation oxide district 17 and the 4th part isolation oxide district 21, be arranged at the body contact zone silicide layer 20 of body contact zone 19 upper surfaces;
Be arranged at the back of the body grid metal level 1 of bottom silicon 2 lower surfaces.
The first positive gate oxide 10 and the second positive gate oxide 28 have covered the zone that P well region 18 upper surfaces equal channel length L1 in the design rule.
In first drain region 6, the central authorities of the positive gate polysilicon layer of the positive gate polysilicon layer in second drain region 32, first 12, second 26, first source region 15, second source region 23, body contact zone 19 upper surfaces further are provided with contact hole 36.
First drain region 6 and second drain region 32 are made as a whole drain electrode and are connected to peripheral circuit through contact hole and metal interconnected; The said first positive gate polysilicon layer 12 and the second positive gate polysilicon layer 26 are made as a whole gate electrode and are connected to peripheral circuit through contact hole and polysilicon interconnection; Said first source region 15 and second source region 23 are made as a whole source electrode and are connected to peripheral circuit through contact hole and metal interconnected.
Side wall district, part isolation oxide district and isolation oxide district are respectively the first side wall district 11, the second side wall district 14, the 3rd side wall district 27, the 4th side wall district 24, first isolation oxide district 9, second portion isolation oxide district 29, third part isolation oxide district 17, the 4th part isolation oxide district 21 and the first isolation oxide district 5, the second isolation oxide district 33.
The first light dope N drift region 8 is positioned at a N well region 4; First's isolation oxide district 9 at least a portion be positioned at a N well region 4 and at least another part be positioned at a N well region 4 upper surfaces, promptly the height of the end face in first's isolation oxide district 9 is higher than the height of the end face of a N well region 4; The said second light dope N drift region 30 is positioned at the 2nd N well region 34; Second portion isolation oxide district 29 at least a portion be positioned at the 2nd N well region 34 and at least another part be positioned at the 2nd N well region 34 upper surfaces, promptly the height of the end face in second portion isolation oxide district 29 is higher than the height of the end face of the 2nd N well region 34.
The doping type of top layer silicon and bottom silicon 2 is that P type semiconductor mixes, and is light dope.The doping type of the one N well region 4 and the 2nd N well region 34 is that N type semiconductor mixes, and is light dope; The doping type of said P well region 18 is that P type semiconductor mixes, and is light dope.The doping type in the positive gate polysilicon layer of the positive gate polysilicon layer in first drain region 6, second drain region 32, first 12, second 26, first source region 15, second source region 23 is that N type semiconductor mixes, and is heavy doping; Said body contact zone 19 doping types are that P type semiconductor mixes, and are heavy doping.
The first isolation oxide district 5 and the second isolation oxide district, 33 thickness are identical with said top layer silicon thickness t 4.First isolation oxide district 9, second portion isolation oxide district 29, third part isolation oxide district 17 are identical with the 4th part isolation oxide district 21 thickness, and the thickness that said first isolation oxide district 9 is positioned at a N well region 4 equals the thickness that said second portion isolation oxide district 29 is positioned at the 2nd N well region 34.First isolation oxide district 9 is positioned at the thickness t 2 of a N well region 4 less than said top layer silicon thickness t 4, and the thickness t 3 that said first isolation oxide district 9 is positioned at a N well region 4 upper surfaces is less than said first positive gate polysilicon layer 12 thickness.Third part isolation oxide district 17 is identical with the 4th part isolation oxide district 21 width L3, and greater than one times channel length L1 and less than ten times channel length L1; And said first isolation oxide district 9 is identical with second portion isolation oxide district 29 width.The first light dope N drift region 8 is identical with the said second light dope N drift region 30 thickness t 5, and equals the value t4-t2 that said top layer silicon thickness deducts said first isolation oxide district thickness; And the said first light dope N drift region 8 is identical with the said second light dope N drift region, 30 width L4, and equal said first isolation oxide district 9 width.It is identical with the ion injection degree of depth in second source region 23 that the ion in first source region 15 injects degree of depth t1, and less than said top layer silicon thickness t 4; It is identical with said top layer silicon thickness t 4 that the ion of said body contact zone 19 injects degree of depth t6.The width L5 that the first positive gate polysilicon layer 12 covers first's isolation oxide district 9 parts equals the width of the second positive gate polysilicon layer, 26 covering second portion isolation oxide district, 29 parts, and greater than 1/2 times channel length L1 and less than the width in first isolation oxide district 9.
Utilize provided by the inventionly can significantly improve the puncture voltage of device based on the radio frequency ldmos transistor of silicon-on-insulator, as shown in Figure 5, Fig. 5 is the breakdown characteristic of the embodiment of the invention based on the radio frequency ldmos transistor of silicon-on-insulator.Visible by figure, device drain-source breakdown characteristics is very precipitous, and puncture voltage is about 13.61V, and the anti-electric leakage partially of pn knot is very low; Utilize and provided by the inventionly also can obviously improve the frequency characteristic of device based on the radio frequency ldmos transistor of silicon-on-insulator, as shown in Figure 6, Fig. 6 is the frequency characteristics of the embodiment of the invention based on the radio frequency ldmos transistor of silicon-on-insulator.Can observe, device has obtained good frequency characteristic, f
T(cut-off frequency) and fmax (maximum frequency of oscillation) obtain maximum at 1.04 V and the positive gate voltage of 1.12V place respectively, are respectively 25.68 GHz and 67.6 GHz; Utilize the radio frequency ldmos transistor based on silicon-on-insulator provided by the invention also can effectively suppress floater effect.The conventional bulk lead-out mode is generally on the device widths direction and draws; Its validity increases along with the device breadth length ratio and weakens to some extent, utilizes the body deriving structure of the radio frequency ldmos transistor that the present invention obtains to draw for side direction, and its inhibition to floater effect does not receive the device size restrictions; Manufacture process and SOI CMOS process compatible; Can a plurality of similar ldmos transistors are shared draw, thereby effectively improve integrated level, reduce production costs with one.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1. radio frequency ldmos transistor structure based on silicon-on-insulator; Comprise the bottom silicon of carrying on the back the grid metal level, being arranged at said back of the body grid metal level; Be arranged at the buried oxidation layer on the said bottom silicon; Be arranged at the first isolation oxide district, top layer silicon and the second isolation oxide district on the said buried oxidation layer, said top layer silicon is characterized in that between the said first isolation oxide district and the second isolation oxide district; Said top layer silicon comprises a N well region, P well region and the 2nd N well region; A said N well region is between said first isolation oxide district and P well region, and said P well region is between a said N well region and the 2nd N well region, and said the 2nd N well region is between the said P well region and the second isolation oxide district;
A said N well region is the mesa structure with first table top and second table top; Said first table top is provided with first drain region; Said first drain region is provided with the first drain region silicide layer; Said second table top is provided with a N drift region, and a said N drift region is provided with first isolation oxide district, and said first isolation oxide district is provided with the first side wall district and the first positive gate polysilicon layer;
Said the 2nd N well region is the mesa structure with first table top and second table top; Said first table top is provided with second drain region; Said second drain region is provided with the second drain region silicide layer; Said second table top is provided with the 2nd N drift region, and said the 2nd N drift region is provided with second portion isolation oxide district, and said second portion isolation oxide district is provided with the 3rd side wall district and the second positive gate polysilicon layer;
Said P well region is the mesa structure with first table top, second table top, the 3rd table top, the 4th table top and the 5th table top; Said first table top is provided with the first positive gate oxide; The top of the said first positive gate oxide is provided with the first positive gate polysilicon layer and the second side wall district, and the top of the said first positive gate polysilicon layer is provided with the first positive gate polysilicon thing layer; Said second table top is provided with first source region and third part isolation oxide district, and the top in said first source region is provided with the first source region silicide layer; Said the 3rd table top is provided with the body contact zone, and the top of said body contact zone is provided with body contact zone silicide layer; Said the 4th table top is provided with second source region and the 4th part isolation oxide district, and the top in said second source region is provided with the second source region silicide layer; Said the 5th table top is provided with the second positive gate oxide, the top of the said second positive gate oxide be provided with the second positive gate polysilicon layer and with the 4th side wall district, the top of the said second positive gate polysilicon layer is provided with the second positive gate polysilicon thing layer.
2. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; The height of second table top of a said N well region is less than the height of first table top of a said N well region; First table top of a said N well region is provided with near the first isolation oxide district, and second table top of a said N well region is provided with near the P well region; The height of second table top of said the 2nd N well region is less than the height of first table top of said the 2nd N well region; First table top of said the 2nd N well region is provided with near the second isolation oxide district, and second table top of said the 2nd N well region is provided with near the P well region.
3. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; In said P well region, said first table top and the 5th table top are positioned at the sustained height place, and said second table top and the 4th table top are positioned at the sustained height place; Said second table top and the 4th table top are between first table top and the 5th table top; The height of said second table top and the 4th table top is less than the height of said first table top and the 5th table top, and said the 3rd table top is between second table top and the 4th table top, and the height of said the 3rd table top is less than the height below of said second table top and the 4th table top.
4. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that first table top in the said N well region, first table top in the 2nd N well region and second table top in the P well region, the 4th table top all are positioned at the sustained height place; Second table top in the said N well region, second table top in the 2nd N well region and the 3rd table top in the P well region all are positioned at the sustained height place.
5. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; Said first source region and the first source region silicide layer are arranged in the side of said P well region second table top near first table top, and said third part isolation oxide district is arranged in the side of said P well region second table top near the 3rd table top; Said second source region and the second source region silicide layer are arranged in the side of said P well region the 4th table top near the 5th table top, and said the 4th part isolation oxide district is arranged in the side of said P well region the 4th table top near the 3rd table top.
6. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; Said first drain region, second drain region, the first positive gate polysilicon layer, the second positive gate polysilicon layer, first source region, second source region, body are equipped with contact hole on the contact zone; Said first drain region and second drain region are made as a whole drain electrode and are connected to peripheral circuit through contact hole and metal interconnected; The said first positive gate polysilicon layer and the second positive gate polysilicon layer are made as a whole gate electrode and are connected to peripheral circuit through contact hole and polysilicon interconnection; Said first source region and second source region are made as a whole source electrode and are connected to peripheral circuit through contact hole and metal interconnected.
7. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1 is characterized in that, the doping type of said top layer silicon and bottom silicon is that P type semiconductor mixes, and is light dope; The doping type of a said N well region and the 2nd N well region is that N type semiconductor mixes, and is light dope; The doping type of said P well region is that P type semiconductor mixes, and is light dope; The doping type of a said N drift region and the 2nd N drift region is that N type semiconductor mixes, and is light dope; The doping type in said first drain region, second drain region, the first positive gate polysilicon layer, the second positive gate polysilicon layer, first source region, second source region is that N type semiconductor mixes, and is heavy doping; Said body contact zone doping type is that P type semiconductor mixes, and is heavy doping; The doping type of a said N drift region, the 2nd N drift region is that N type semiconductor mixes, and is light dope; The said first side wall district, the second side wall district, the 3rd side wall district and the 4th side wall district are silicon nitride; The said first isolation oxide district, the second isolation oxide district, first isolation oxide district, second portion isolation oxide district, third part isolation oxide district and the 4th part isolation oxide district are silicon dioxide; The said first drain region silicide layer, the second drain region silicide layer, the first source region silicide layer, the second source region silicide layer, body contact zone silicide layer, the first positive gate polysilicon thing layer, the second positive gate polysilicon thing layer are cobalt silicide; The said first positive gate oxide and the second positive gate oxide are silicon dioxide.
8. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1 is characterized in that all the thickness with said top layer silicon is identical for the thickness in the said first isolation oxide district and the second isolation oxide district.
9. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; Said first isolation oxide district, second portion isolation oxide district, third part isolation oxide district are identical with the thickness in the 4th part isolation oxide district; And the thickness that said first isolation oxide district is positioned at the first N well region equals the thickness that said second portion isolation oxide district is positioned at the second N well region, and the thickness that said third part isolation oxide district is positioned at the P well region equals the thickness that said the 4th part isolation oxide district is positioned at the P well region.
10. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 9; It is characterized in that; Said first isolation oxide district is positioned at the thickness of the thickness of the first N well region less than said top layer silicon; And said first isolation oxide district is positioned at the thickness of the thickness of the first N well region upper surface less than the said first positive gate polysilicon layer, and said third part isolation oxide district is positioned at the thickness of the thickness of P well region less than said top layer silicon.
11. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; The width in said third part isolation oxide district is identical with the width in the 4th part isolation oxide district, and greater than one times channel length and less than ten times channel length; And the width in said first isolation oxide district is identical with the width in second portion isolation oxide district.
12. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; The thickness of a said N drift region is identical with the thickness of said the 2nd N drift region, and the thickness that equals said top layer silicon deducts the thickness in said first isolation oxide district; And the width of a said N drift region is identical with said the 2nd N drift region width, and equals the width in said first isolation oxide district.
13. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1 is characterized in that, it is identical with the ion injection degree of depth in second source region that the ion in said first source region injects the degree of depth, and less than said top layer silicon thickness; It is identical with the thickness of said top layer silicon that the ion of said body contact zone injects the degree of depth.
14. the radio frequency ldmos transistor structure based on silicon-on-insulator according to claim 1; It is characterized in that; The width that the said first positive gate polysilicon layer covers first's isolation oxide district part equals the width of the second positive gate polysilicon layer covering second portion isolation oxide district part, and greater than 1/2 times channel length and less than the width in first isolation oxide district.
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| CN111162115A (en) * | 2018-11-08 | 2020-05-15 | 旺宏电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN112349782A (en) * | 2020-11-05 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN112349784A (en) * | 2020-11-05 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113192987A (en) * | 2021-04-27 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | SOI (silicon on insulator) body contact device structure and forming method thereof |
| CN113192987B (en) * | 2021-04-27 | 2023-11-03 | 上海华虹宏力半导体制造有限公司 | SOI body contact device structure and forming method thereof |
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