CN111933714A - Method for manufacturing three-section type oxide layer shielding grid groove MOSFET structure - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000005388 borosilicate glass Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 35
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052796 boron Inorganic materials 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 58
- 238000005530 etching Methods 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 13
- 238000000407 epitaxy Methods 0.000 claims description 13
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000009423 ventilation Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000010992 reflux Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention relates to a manufacturing method of a three-section type oxide layer shielding grid groove MOSFET structure. The source-drain breakdown voltage of the traditional SGT device is controlled by the thickness of an oxide layer, the higher the breakdown voltage is, the thicker the oxide layer is required to be, but in order to obtain lower Rsp, the unit cell size needs to be reduced as much as possible. According to the invention, the deep trench is filled with the borosilicate glass BSG material through a CVD (chemical vapor deposition) process, then the Boron in the borosilicate glass BSG material is diffused into the Si material at the periphery of the deep trench through a thermal process to form the P column, the BSG concentration and the annealing temperature are changed so as to adjust the high width and concentration of the P column, and the charge balance with the N-type epitaxial layer is realized. According to the invention, a thick shielding electrode dielectric layer does not need to be grown in the groove, the BSG has good high-temperature reflux characteristic and good groove filling capacity, and the CD of the groove can be greatly reduced, so that the unit cell size can be reduced, the same breakdown voltage can be realized by adopting an epitaxial wafer with higher doping concentration, and the Rsp of a device can be reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a manufacturing method of a three-section type oxide layer shielding grid groove MOSFET structure.
Background
The SGT (shielded-Gate-Trench) structure has a charge coupling effect, and introduces horizontal depletion on the basis of the vertical depletion (P-Body/N-Epi junction) of the traditional Trench MOSFET, so that the electric field of the device is changed from triangular distribution to approximately rectangular distribution. Under the condition of adopting the epitaxial specification with the same doping concentration, the device can obtain higher breakdown voltage, and the structure is widely applied to the field of medium and low voltage power devices.
Fig. 15 shows a conventional SGT (shielded-Gate-Trench) structure, in which a Trench is formed by etching, and then a Shield electrode dielectric layer, typically a thick oxide layer, is grown in the Trench to balance charges. The source-drain breakdown voltage of the SGT with the structure is controlled by the thickness of the oxide layer, the higher the breakdown voltage is, the thicker the oxide layer needs to be, and the thickness of the oxide layer reaches about 6000A for a 100V device. Therefore, the trench CD needs to be defined to be relatively wide in device design (the trench CD needs to be 1um or more for a 100V device). However, a mainstream direction of current SGT device design is to obtain a lower Rsp (on-resistance per unit area), and the size of a unit cell needs to be reduced as much as possible, and the traditional SGT structural features obviously hinder its development.
Fig. 14 shows a more advanced SGT (shielded-Gate-Trench) structure, which can further reduce Rsp (on-resistance per unit area), and is implemented by first forming a Trench by etching, then injecting ions opposite to the epitaxy into the bottom of the Trench to form an inversion junction of a certain shape, and then constructing a conventional SGT structure on the basis, wherein the junction formed by the thick oxide layer beside the source polysilicon and the boron diffusion layer at the bottom of the Trench can achieve charge balance with the N-type epitaxy as much as possible. Under the same source-drain breakdown voltage as that of the conventional SGT structure in the figure 13, the SGT of the structure increases the charge balance between the inversion junction and the epitaxy due to the introduction of the bottom inversion junction, further increases the source-drain breakdown voltage, and can further reduce the thick oxide layer and the epitaxy resistivity on the basis of the increased source-drain breakdown voltage. The ideal shape of the trench bottom junction is narrow width, high height and uniform width. The ideal junction shape cannot be achieved by single or multiple non-equal energy implantations, which hinders the further development of advanced SGTs.
Disclosure of Invention
The invention aims to provide a manufacturing method of a three-section type oxide layer shielding grid groove MOSFET structure, which overcomes the defects of the prior art.
The technical scheme adopted by the invention is as follows:
the manufacturing method of the three-section type oxide layer shielding grid groove MOSFET structure is characterized in that:
according to the method, a deep groove is filled with a borosilicate glass BSG material through a CVD (chemical vapor deposition) process, a P column is formed by diffusing Boron in the borosilicate glass BSG material into a Si material on the periphery of the deep groove through a thermal process, the BSG concentration and the annealing temperature are changed so as to adjust the high width and concentration of the P column, and the charge balance between the P column and an N-type epitaxial layer is realized.
The method specifically comprises the following steps:
the method comprises the following steps: growing an N-type epitaxial layer on the surface of the Si substrate slice;
step two: sequentially forming a thin oxide layer, thin silicon nitride and a thick oxide layer on the surface of the epitaxial layer to form a hard mask;
step three: carrying out a photoetching process by using a groove photoetching plate, exposing the position of the groove, and etching the exposed position into a deep groove by dry etching;
step four: filling the deep trench with BSG material by CVD process, and planarizing the surface by reflow process;
step five: corroding the borosilicate glass BSG material in the deep groove to the specified position of the groove by using dry corrosion;
step six: forming a thermal oxide layer by utilizing a high-temperature oxidation process, and simultaneously diffusing Boron in a borosilicate glass BSG material into a Si material at the periphery of the deep groove to form a P column;
step seven: backfilling polycrystalline silicon in the groove and etching back to the specified position of the groove;
step eight: backfilling the oxide layer by using high-density plasma chemical vapor deposition (HDP CVD);
step nine: polishing the backfill oxide layer to the surface of the nitrogen oxide by using chemical mechanical polishing;
step ten: removing nitrogen oxide and thin oxide on the surface layer by using a wet method, and etching back the oxide layer to the specified position of the trench;
step eleven: forming a gate oxide layer using a thermal oxidation process;
step twelve: and backfilling the polysilicon and etching back to the designated position of the groove to form the grid electrode of the device.
In the first step, the thickness of the epitaxial layer is set according to the source-drain withstand voltage required by the device, and the range is from 5 micrometers to 20 micrometers.
In the third step, the dry etching forms the groove with the depth of 3 microns to 20 microns and the width of 0.3 microns to 2 microns.
And step five, etching the borosilicate glass BSG material in the groove to 2-17 microns below the surface of the Si by using dry etching.
In the sixth step, Boron diffusion in the borosilicate glass BSG material and thick oxide layer growth are carried out synchronously, and the temperature, time and ventilation conditions are consistent;
when the temperature of the oxidation condition is low and the time is short, an annealing boron diffusion process is additionally added, the high-temperature annealing temperature is between 800 ℃ and 1150 ℃, and only nitrogen is introduced in the annealing process.
And seventhly, backfilling polycrystalline silicon in the groove and back etching to 1-1.5 microns.
In the tenth step, the HDP oxide is etched back to 0.8-1.2 microns in the trench.
In the twelfth step, the gate polysilicon is backfilled and etched back to a depth of 0.1 to 0.2 microns in the trench.
The MOSFET structure formed by the method is positioned on an epitaxial substrate, a region is arranged below a source electrode groove of the MOSFET structure, the region is filled with a material which is inverse to the epitaxy, and the charge balance is realized by a P column and the epitaxy formed by diffusion source diffusion, and the MOSFET grid electrode and the source electrode groove are self-aligned with a borosilicate glass groove below the MOSFET grid electrode and the source electrode groove;
the filler is a P-type oxide film, namely a borosilicate glass BSG material.
The invention has the following advantages:
according to the invention, BSG (borosilicate glass) material is filled in the trench through a CVD (chemical vapor deposition) process, and then Boron is automatically diffused into the silicon material at the periphery of the trench through a thermal process to form the P column, so that the high width and concentration of the P column can be effectively adjusted by changing the concentration of BSG and the annealing temperature, and the charge balance with the N-type epitaxial layer is realized. By adopting the SGT MOSFET structure and the process manufacturing method, a thick shielding electrode dielectric layer does not need to be grown in the groove, and meanwhile, the BSG has good high-temperature reflux characteristic and good groove filling capacity, and can greatly reduce the CD of the groove, so that the unit cell size can be reduced, the same breakdown voltage can be realized by adopting an epitaxial wafer with higher doping concentration, the device Rsp is reduced, and the market competitiveness is enhanced.
Drawings
FIG. 1 is a schematic diagram of a first step of the present invention;
FIG. 2 is a schematic view of step two of the present invention;
FIG. 3 is a schematic view of step three of the present invention;
FIG. 4 is a schematic view of step four of the present invention;
FIG. 5 is a schematic view of step five of the present invention;
FIG. 6 is a schematic representation of step six of the present invention;
FIG. 7 is a schematic view of step seven of the present invention;
FIG. 8 is a schematic representation of step eight of the present invention;
FIG. 9 is a diagram illustrating a ninth step of the present invention.
FIG. 10 is a diagram illustrating step ten of the present invention.
FIG. 11 is a schematic representation of step eleven of the present invention.
FIG. 12 is a diagram illustrating a twelfth step of the present invention.
FIG. 13 is a schematic diagram of a more perfect advanced SGT structure;
FIG. 14 is a schematic diagram of a more advanced SGT architecture;
fig. 15 is a schematic diagram of a conventional SGT structure.
Detailed Description
The present invention will be described in detail with reference to specific embodiments.
The invention relates to a manufacturing method of a three-section type oxide layer shielding gate trench MOSFET structure, which fills borosilicate glass BSG material in a deep trench through a CVD (chemical vapor deposition) process, diffuses Boron in the borosilicate glass BSG material into Si material at the periphery of the deep trench through a thermal process to form a P column, and changes BSG concentration and annealing temperature so as to adjust the high width and concentration of the P column and realize charge balance with an N-type epitaxial layer.
The method specifically comprises the following steps:
the method comprises the following steps: and (3) growing an N-type epitaxial layer on the surface of the Si substrate slice, wherein the thickness of the epitaxial layer is set according to the source-drain withstand voltage required by the device, and ranges from 5 micrometers to 20 micrometers, as shown in figure 1.
Step two: and sequentially forming a thin oxide layer, thin silicon nitride and a thick oxide layer on the surface of the epitaxial layer, and forming an ONO (silicon oxide-silicon nitride-silicon oxide) film as a hard mask. As shown in fig. 2.
Step three: and (3) carrying out a photoetching process by using a groove photoetching plate, exposing the position where the groove needs to be dug, masking without photoresist, masking the rest part by using photoresist, etching the position without the photoresist masking into a deep groove by dry etching, and then removing the photoresist, wherein the step is shown in figure 3. The trenches have a depth of between 3 microns and 20 microns and a width of between 0.3 microns and 2 microns.
Step four: and filling BSG material in the deep trench by using a CVD (chemical vapor deposition) process, and refluxing to ensure that the deep trench is filled and the surface is flat, as shown in FIG. 4.
Step five: the BSG in the trench is etched to 2 to 17 microns below the Si surface using a dry etch, as shown in fig. 5.
Step six: a thick thermal oxide layer is formed by a high-temperature oxidation process, and Boron in the borosilicate glass BSG material is diffused into the Si material at the periphery of the deep trench to form a P-pillar with a uniform width, as shown in fig. 6.
The boron diffusion process in the borosilicate glass BSG is synchronously carried out with the growth of the thick oxide layer, and the temperature, the time and the ventilation condition are consistent. If the temperature of the oxidation condition is low and the time is short, an annealing boron diffusion process can be additionally added, the high-temperature annealing temperature is between 800 ℃ and 1150 ℃, and only nitrogen is introduced in the annealing process.
Step seven: the gate trench is backfilled with polysilicon and etched back to 1 micron to 1.5 microns as shown in fig. 7.
Step eight: high density plasma vapor deposited HDP oxide in the gate trench is shown in fig. 8.
Step nine: the HDP oxide was planarized to the oxynitride silicon nitride surface using chemical mechanical polishing CMP as shown in fig. 9.
Step ten: the HDP oxide is etched back to 0.8 to 1.2 microns into the trench as shown in fig. 10.
Step eleven: a gate oxide layer is grown using a thermal oxidation process as shown in fig. 11.
Step twelve: the gate polysilicon is backfilled and etched back to a depth of 0.1 to 0.2 microns into the trench as shown in fig. 12.
The final metal level is the same as the conventional MOSFET process, and the final device structure is shown in fig. 13 after completion.
The MOSFET structure obtained by the method is positioned on an epitaxial substrate, and a region is arranged below a source electrode groove of the MOSFET structure, and the region is filled with a material which is in an inverse shape with the epitaxy, so that charge balance is realized by a P column formed by diffusion source diffusion and the epitaxy. The area under the source trench of the MOSFET is a deep trench.
And filling a deep groove below the MOSFET source groove with a doped oxide which is in an inverse type with the epitaxy. The epitaxial material of the MOSFET is N-type, and the filler in the deep groove below the source groove is a P-type oxide film: borosilicate glass BSG. The MOSFET gate, source trench and borosilicate glass trench below the MOSFET gate and source trench are self-aligned. The depth of the deep trench is less than the thickness of the epitaxy of the MOSFET.
The SGT MOSFET provided by the invention is characterized in that BSG material is filled in a groove, and then Boron is diffused to the periphery of the groove to form a P column through a high-temperature process of a furnace tube, so that charge balance with N-type epitaxy is realized, and an additional charge coupling effect except a thick oxide layer is increased. The SGT MOSFET manufactured by the manufacturing method can realize smaller device size on the basis of the traditional SGT MOSFET, and meanwhile, the implanted borosilicate glass BSG can flexibly adjust the width and the concentration of a P column, so that the charge balance area is increased, the epitaxial resistivity is reduced, the on-resistance of a chip in unit area is greatly reduced, the device parameters and performance are optimized, and the process controllability is strong.
The invention is not limited to the examples, and any equivalent changes to the technical solution of the invention by a person skilled in the art after reading the description of the invention are covered by the claims of the invention.
Claims (9)
1. The manufacturing method of the three-section type oxide layer shielding grid groove MOSFET structure is characterized in that:
filling a borosilicate glass BSG material in the deep trench by a CVD (chemical vapor deposition) process, diffusing Boron in the borosilicate glass BSG material into a Si material at the periphery of the deep trench to form a P column through a thermal process, and changing the concentration of BSG and the annealing temperature so as to adjust the high width and the concentration of the P column and realize charge balance with the N-type epitaxial layer;
the method specifically comprises the following steps:
the method comprises the following steps: growing an N-type epitaxial layer on the surface of the Si substrate slice;
step two: sequentially forming a thin oxide layer, thin silicon nitride and a thick oxide layer on the surface of the epitaxial layer to form a hard mask;
step three: carrying out a photoetching process by using a groove photoetching plate, exposing the position of the groove, and etching the exposed position into a deep groove by dry etching;
step four: filling the deep trench with BSG material by CVD process, and planarizing the surface by reflow process;
step five: corroding the borosilicate glass BSG material in the deep groove to the specified position of the groove by using dry corrosion;
step six: forming a thermal oxide layer by utilizing a high-temperature oxidation process, and simultaneously diffusing Boron in a borosilicate glass BSG material into a Si material at the periphery of the deep groove to form a P column;
step seven: backfilling polycrystalline silicon in the groove and etching back to the specified position of the groove;
step eight: backfilling the oxide layer by using high-density plasma chemical vapor deposition (HDP CVD);
step nine: polishing the backfill oxide layer to the surface of the nitrogen oxide by using chemical mechanical polishing;
step ten: removing nitrogen oxide and thin oxide on the surface layer by using a wet method, and etching back the oxide layer to the specified position of the trench;
step eleven: forming a gate oxide layer using a thermal oxidation process;
step twelve: and backfilling the polysilicon and etching back to the designated position of the groove to form the grid electrode of the device.
2. The method of claim 1, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET comprises:
in the first step, the thickness of the epitaxial layer is set according to the source-drain withstand voltage required by the device, and the range is from 5 micrometers to 20 micrometers.
3. The method of claim 2, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET comprises:
in the third step, the dry etching forms the groove with the depth of 3 microns to 20 microns and the width of 0.3 microns to 2 microns.
4. The method of claim 3, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET structure comprises:
and step five, etching the borosilicate glass BSG material in the groove to 2-17 microns below the surface of the Si by using dry etching.
5. The method of claim 4, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET structure comprises:
in the sixth step, Boron diffusion in the borosilicate glass BSG material and thick oxide layer growth are carried out synchronously, and the temperature, time and ventilation conditions are consistent;
when the temperature of the oxidation condition is low and the time is short, an annealing boron diffusion process is additionally added, the high-temperature annealing temperature is between 800 ℃ and 1150 ℃, and only nitrogen is introduced in the annealing process.
6. The method of claim 5, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET structure comprises:
and seventhly, backfilling polycrystalline silicon in the groove and back etching to 1-1.5 microns.
7. The method of claim 6, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET structure comprises:
in the tenth step, the HDP oxide is etched back to 0.8-1.2 microns in the trench.
8. The method of claim 7, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET comprises:
in the twelfth step, the gate polysilicon is backfilled and etched back to a depth of 0.1 to 0.2 microns in the trench.
9. The method of claim 8, wherein the step of forming the three-segment oxide layer shielded gate trench MOSFET comprises:
the MOSFET structure formed by the method is positioned on an epitaxial substrate, a region is arranged below a source electrode groove of the MOSFET structure, the region is filled with a material which is inverse to the epitaxy, and the charge balance is realized by a P column and the epitaxy formed by diffusion source diffusion, and the MOSFET grid electrode and the source electrode groove are self-aligned with a borosilicate glass groove below the MOSFET grid electrode and the source electrode groove;
the filler is a P-type oxide film, namely a borosilicate glass BSG material.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112382572A (en) * | 2021-01-15 | 2021-02-19 | 龙腾半导体股份有限公司 | SGT structure of ONO shielded gate and manufacturing method thereof |
| CN113990931A (en) * | 2021-10-28 | 2022-01-28 | 电子科技大学 | Trench MOSFET device with adjustable breakdown voltage temperature coefficient and preparation method thereof |
| CN113990930A (en) * | 2021-10-28 | 2022-01-28 | 电子科技大学 | SGT-MOSFET device with adjustable breakdown voltage temperature coefficient and preparation method thereof |
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| CN112382572B (en) * | 2021-01-15 | 2021-11-02 | 龙腾半导体股份有限公司 | SGT structure of ONO shielded gate and manufacturing method thereof |
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