CN101621072A - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN101621072A CN101621072A CN200810127254A CN200810127254A CN101621072A CN 101621072 A CN101621072 A CN 101621072A CN 200810127254 A CN200810127254 A CN 200810127254A CN 200810127254 A CN200810127254 A CN 200810127254A CN 101621072 A CN101621072 A CN 101621072A
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Abstract
The invention discloses a kind of semiconductor device and manufacture method thereof, be applicable to high voltage operation, described device comprises: a substrate has one first conductivity; A plurality of isolation structures are arranged at the surface of substrate; One trap is arranged in the described substrate between isolation structure, has one second conductivity and an exposing surface in contrast to described first conductivity; One matrix area is arranged in the part of trap, has first conductivity and the recessed surface that are same as substrate; One grid stacking material is arranged on the part of substrate, and part covers the described recessed surface of the described exposing surface and the described matrix area of described trap; One drain region is arranged in another part of described trap and is not covered by described grid stacking material, has described second conductivity; The one source pole district is arranged in the part of described matrix area, has described second conductivity; And a matrix contact zone, be arranged in another part of described matrix area, have described first conductivity and contiguous described source area.
Description
Technical field
The invention relates to production of integrated circuits, and particularly about a kind of semiconductor device and manufacture method thereof that is applicable to high voltage operation.
Background technology
In recent years, development along with the semiconductor integrated circuit manufacturing technology, also increase for the demand that is formed at the members such as controller, memory, low voltage operating circuit and high voltage operation circuit on the one chip thereupon, use the more one chip system of high integration that produces.
In the one chip system, usually adopted as double-diffused metal oxide semiconductor (double-diffused metal oxide semiconductor, DMOS) device and power semiconductor high voltage members such as (IGBT) are to improve power conversion efficiency and to reduce the loss of electric weight.The DMOS device has advantages such as low-power consumption and high speed operation, thereby becomes one of high voltage member application choice.
DMOS device style is that (lateral DMOS, LDMOS) (vertical DMOS, VDMOS) device waits two classes to lateral type DMOS for device and vertical-type DMOS.The preparation of VDMOS device involves the use of epitaxy technique usually, and the preparation of LDMOS device then not necessarily needs to use epitaxy technique can adopt standard CMOS (Complementary Metal Oxide Semiconductor) (CMOS) technology, therefore has preferable process integration.Yet compared to the VDMOS device, the LDMOS device has higher conducting resistance (Rds_on) and needs bigger device pitch (pitch).Therefore along with the trend of dwindling of one chip system dimension, just need improve, to promote its application at the high conducting resistance and the device pitch of LDMOS device.
Please refer to Fig. 1, shown the section situation of a kind of known water flat pattern double-diffused metal oxide semiconductor (LDMOS) device.
As shown in Figure 1, the LDMOS device mainly comprises a P type silicon substrate 100, is provided with a N type trap 102 in its part.Then be respectively arranged with a field oxide (field oxide, FOX) 104, thereby defined the active region that the LDMOS device is set substantially by these field oxides 104 in the surface of N type trap 102 and P type silicon substrate 100 junctions.These field oxides 104 are to form by known field oxide method.The N type trap 102 that is positioned at 104 of field oxides then is provided with a P mold base (body) district 106, and it is to be formed in the part of N type trap 102 and the juxtaposition field oxide 104 in left side relatively substantially.In P mold base district 106, be provided with a N-district 113, a N+ district 114S and a P+ district 116 in addition, wherein N-district 113 is a shallow doped region (lightly doped region), and P+ district 116 be adjacent to N+ district 114S and this two zone be for 106 surface exposes of P mold base district with contact zone as source electrode and matrix.In the N type trap 102 of 104 of the field oxides on P mold base district 106 and right side, then be provided with a N+ district 114D in addition, with as drain electrode.Then be formed with a grid stacking material G on the part on the surface of the N of field oxide 104 type trap 102, with the usefulness as a grid, it comprises and is stacked in N type trap 102 lip-deep gate dielectric layers 110, gate electrode 108 in regular turn.Then be provided with sept 112 on the gate dielectric layer 110 in grid stacking material G and the symmetrical side of gate electrode 108.Grid stacking material G covers P mold base district 106 and has covered N-district 113 in this part.
At this, in LDMOS device shown in Figure 1, label L has shown passage length (channellength), is to be defined as the distance of N-district 113 to P mold base district 106 1 sides that are positioned at grid stacking material G below.Label P display device spacing (pitch) in addition is to be defined as N+ district 114S and 116 junctions, P+ district to the distance between the mid point of another N+ district 114D.Yet the grid stacking material G that so flatly is arranged on P type substrate 100 upper surfaces probably is unfavorable for the reduction of device pitch P, so also is unfavorable for the reduction of the conducting resistance (Rds_on) of LDMOS device.
Summary of the invention
The invention provides a kind of semiconductor device and manufacture method thereof, be suitable for the application and the preparation of high voltage member.
According to an embodiment, semiconductor device of the present invention comprises:
One substrate has one first conductivity; A plurality of isolation structures are arranged at the surface of described substrate; One trap is arranged in the described substrate between described isolation structure, has one second conductivity and an exposing surface in contrast to described first conductivity; One matrix area is arranged in the part of described trap, has described first conductivity and the recessed surface that are same as described substrate; One grid stacking material is arranged on the part of described substrate, and part covers the described recessed surface of the described exposing surface and the described matrix area of described trap; One drain region is arranged in another part of described trap and is not covered by described grid stacking material, has described second conductivity; The one source pole district is arranged in the part of described matrix area, has described second conductivity; And a matrix contact zone, be arranged in another part of described matrix area, have described first conductivity and contiguous described source area.
According to another embodiment, the manufacture method of semiconductor device of the present invention comprises:
Semi-conductive substrate is provided, is provided with a trap in it, wherein said Semiconductor substrate has one first conductivity, and described trap has one second conductivity and an exposing surface in contrast to described first conductivity; Form a plurality of isolation structures on the surface of described Semiconductor substrate, one of wherein said isolation structure is on the described Semiconductor substrate that is formed in the described trap; A screen that forms patterning is on described Semiconductor substrate, to expose the described isolation structure that is positioned at described trap; Carry out an ion implantation step, as etch mask, form a matrix area with the below of the described isolation structure in described trap with described screen, described matrix area has one first conductivity; Carry out an etching step, as etch mask, etching is removed the described isolation structure in the described trap with described screen, and to expose described matrix area, wherein said matrix area has a recessed surface that is lower than contiguous described Semiconductor substrate; Remove described screen; Form a grid stacking material of patterning, part covers the described recessed surface of described matrix area and the surface that is close to the described trap of described matrix area; Form an one source pole district and a drain region in the part of described matrix area and in the part of described trap respectively, wherein said source area and described drain region are not covered by described grid stacking material and are had described second conductivity; And in another part of described matrix area, forming a matrix contact zone, described matrix contact zone is adjacent to described source area and do not covered by described grid stacking material and have described first conductivity.
Scheme of the present invention helps the reduction of device pitch P, therefore also helps the reduction of the conducting resistance (Rds_on) of LDMOS device.
Description of drawings
Fig. 1 has shown the section situation of known horizontal type double-diffused metal oxide semiconductor (LDMOS) device; And
Fig. 2～Fig. 7 is a series of schematic diagrames, has shown that respectively horizontal type double-diffused metal oxide semiconductor (LDMOS) according to one embodiment of the invention is installed on the section situation in the different making steps.
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
Please refer to Fig. 2～a series of schematic diagrames shown in Figure 7, shown respectively, use and prepare the LDMOS device that has than low on-resistance according to the making situation of horizontal type double-diffused metal oxide semiconductor (LDMOS) device of one embodiment of the invention.
Please refer to Fig. 2, semi-conductive substrate 200 at first is provided, be provided with a trap 202 in it, the conductivity of trap 202 is different from the conductivity of substrate 200, and its doping content is for example between 10
12～10
13Atom/every square centimeter.At this, Semiconductor substrate 200 for example is epitaxial loayer substrate one silicon-on-insulator (SOI) substrate or bulk silicon substrate.Semiconductor substrate 200 has one first conductivity, for example is P type or N type conductivity, and preferably is P-type conduction, and its doping content is for example between 10
11～10
13Atom/every square centimeter.Trap 202 can and adopt suitable shade (not shown) to form by the known ion method for implanting.Then, a smooth pad oxide skin(coating) 204 and the pad nitride layer 206 of forming on Semiconductor substrate 200 with covering, it is stacked on the Semiconductor substrate 200 in regular turn.Then by a photoetching and etch step (all demonstration), in pad oxide skin(coating) 204 and pad nitride layer 206, to form several openings, partly to expose the Semiconductor substrate 200 of its below respectively.At this, opening is to illustrate to be the opening OP1 that is positioned at both sides and opening OP2 placed in the middle, and the size of its split shed OP2 is slightly larger than the size of opening OP1, but not as limit, and the size of opening OP2 also can be equal to or less than the size of opening OP1.Opening OP1 exposes the Semiconductor substrate 200 of its below and the part of trap 202 respectively, and opening OP2 then only exposes the part of trap 202.The material of above-mentioned pad oxide skin(coating) 204 for example is a silicon dioxide, and the material of pad nitride layer 206 for example is a silicon nitride.
Please refer to Fig. 3, then in opening OP1 and opening OP2, form isolation structure 208a and 208b respectively.And after forming isolation structure 208a and 208b, form the mask layer 210 of patterning and expose isolation structure 208b and contiguous pad nitride layer 206.Then carry out an ion implantation step 212, to form a matrix (body) district 214 in the trap 202 of isolation structure 208b below, matrix area 214 has the conductivity that is same as substrate 200, and its doping content is for example between 10
12～10
14Atom/every square centimeter.As shown in Figure 3, isolation structure 208a and 208b illustrate to be field oxide (field oxide, FOX), it is formed by thermal oxidation method, but isolation structure 208a and 208b are not limited with field oxide, it also can adopt as separator with shallow grooves (shallow trench isolation, other isolation structures STI).Matrix area 214 also can be early than form before isolation structure 208a and the 208b in advance, and it can form by the use of the suitable shade of collocation and N type or P type ion.The material of above-mentioned mask layer 210 for example is a photo anti-corrosion agent material.
Please refer to Fig. 4, follow by an etching step (not shown) with after removing isolation structure 208b, then etching is removed retes such as shade 210, pad nitride layer 206 and pad oxide skin(coating) 204, and then the surface 250 of having exposed isolation structure 208a and matrix area 214.At this, the surface of matrix area 214 is a concave surface 250 that is lower than Semiconductor substrate 200 surfaces, and this concave surface 250 is the surface of slynessization, thereby makes matrix area 214 have a section situation of U type substantially.Then then on Semiconductor substrate 200, form a gate dielectric layer 216 and a conductive layer 218 in regular turn, use the surface that conformably covers Semiconductor substrate 200, concave surface 250 and isolation structure 208a.As shown in Figure 4, the generation type of gate dielectric layer 216 for example is a thermal oxidation method, therefore its material can be the silica material, and before be formed at matrix areas 214 in first trap 202 when gate dielectric layer 216 forms, will further spread and formed matrix area 214 once diffusion ', gate dielectric layer 216 then conformably is formed in regular turn with conductive layer 218 has part depression and part raised surface on the Semiconductor substrate 200.The material of conductive layer 218 then can be through the polysilicon of doping or the metal material of tungsten silicide.
Please refer to Fig. 5, then, the mask layer (not shown) that forms a patterning is on conductive layer 218, and exposed portions serve conductive layer 218.Then carry out an etching step (not shown) to remove the conductive layer that mask layer was exposed 218 and gate dielectric layer 216 parts of patterning for this reason, and then respectively at forming biseptate grid stacking material G1 and G2 on the part of Semiconductor substrate 200, its partly cover respectively matrix area 214 ' a part and expose matrix area 214 ' part between grid stacking material G1 and G2.Then form the mask layer 220 of a patterning, with part expose grid stacking material G1 and G2 reach therebetween matrix area 214 '.Then carry out an ion implantation step 222, have the admixture that is same as trap 202 conductivity with doping, with in matrix area 214 ' a part in form shallow doped region 224.The doping content that ion implantation step 222 is adopted is for example between 10
12～10
13Atom/every square centimeter.
Please refer to Fig. 6, behind the mask layer 220 of removing patterning, then on the corresponding sidewall of grid stacking material G1 and G2, form a sept 226 respectively.Then plant the application of shade (not shown) by suitable cloth, have with doping the admixture that is same as trap 202 conductivity in matrix area 214 ' with trap 202 in, to form an one source pole district 228s and a drain region 228d respectively, the doping content that is adopted is for example between 10
14～10
15Atom/every square centimeter.Then plant the application of shade (not shown) by another suitable cloth, have with doping the admixture that is different from trap 202 conductivity in matrix area 214 ' in, to form a matrix contact zone 230, the doping content that it adopted is for example between 10
14～10
15Atom/every square centimeter, and this matrix contact zone 230 is positioned in the middle of two source area 228s substantially, and source area 228s is respectively adjacent to shallow doped region 224 and contacts it.
As shown in Figure 6, be to illustrate to having the two corresponding LDMOS devices that are provided with at this LDMOS device, it is a relative matrix contactant 230 and mirror image is arranged on the Semiconductor substrate 200 symmetrically.At this, in LDMOS device shown in Figure 6, label L ' has shown the passage length (channel length) of each LDMOS device, be defined as shallow doped region 224 to the P mold base district 214 that is positioned at grid stacking material G1 and G2 below ' the distance of a side.Label P ' has then shown the device pitch (pitch) of each LDMOS device in addition, is to be defined as the intersection of matrix contact zone 230 and each source area 228s to the distance between the mid point of drain region 228d.Therefore, with reference to result shown in Figure 6, because matrix area 214 ' have a concave surface that is lower than contiguous semiconductor substrate 200 surfaces, thereby make the grid stacking material G1 of follow-up formation and G2 can partly be arranged on the above-mentioned concave surface but not integral level be located on the Semiconductor substrate 200, and then reduced the grid stacking material G1 that is positioned on the semiconductor substrate 200 and the horizontal length of G2.Therefore, compared to LDMOS device shown in Figure 1, the device pitch P in the LDMOS device as shown in Figure 6 can further obtain reduction, so can reduce its conducting resistance (Rds_on).
Moreover, since matrix area 214 ' be to form before formation in advance in grid stacking material G1 and G2, therefore can be for the passage length L ' of the LDMOS device in the LDMOS device shown in Figure 6 by controlling in the etch step that defines grid stacking material G1 and G2, therefore its passage length L ' can be controlled more accurately, and the device of different passage lengths can be formed by the adjustment of matrix area 214 ' interior different field oxide width.
Please continue with reference to Fig. 7, then can be smooth form between one deck dielectric layer 230 with covering on structure shown in Figure 6.Then within interlayer dielectric layer 230, form several and electrically independently conduct electricity contactant 232d and 232s, with contact respectively respectively drain 228d, matrix contact zone 230 and each source area 228s.Then form several electrically leads 234 independently on interlayer dielectric layer 230, these leads 234 have covered conduction contactant 232d and 232s respectively, and then form the electrical ties relation with the part of the LDMOS device of its below.Above-mentioned conduction contactant 232d and 232s and lead 234 can form by the technology of known contactant and lead, and its material can be as the electric conducting materials such as polysilicon, tungsten or aluminium through mixing.At this, conduction contactant 232s has then contacted matrix contact zone 230 and adjacent source electrode 228s simultaneously.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly be familiar with this area related personnel; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when the scope that look accompanying Claim.
Claims (16)
1, a kind of semiconductor device is applicable to high voltage operation, it is characterized in that, described device comprises:
One substrate has one first conductivity;
A plurality of isolation structures are arranged at the surface of described substrate;
One trap is arranged in the described substrate between described isolation structure, has one second conductivity and an exposing surface in contrast to described first conductivity;
One matrix area is arranged in the part of described trap, has described first conductivity and the recessed surface that are same as described substrate;
One grid stacking material is arranged on the part of described substrate, and part covers the described recessed surface of the described exposing surface and the described matrix area of described trap;
One drain region is arranged in another part of described trap and is not covered by described grid stacking material, has described second conductivity;
The one source pole district is arranged in the part of described matrix area, has described second conductivity; And
One matrix contact zone is arranged in another part of described matrix area, has described first conductivity and contiguous described source area.
2, device according to claim 1 is characterized in that described first conductivity is P-type conduction and described second conductivity is N type conductivity.
3, install according to claim 1, it is characterized in that described matrix area does not contact described isolation structure.
4, install according to claim 1, it is characterized in that, the dopant concentration in described source area and the described drain region is higher than the dopant concentration in the described trap, and the dopant concentration of described matrix contact zone is higher than the dopant concentration in the described matrix area.
5, install according to claim 1, it is characterized in that described grid stacking material has a non-smooth surface.
6, install according to claim 1, it is characterized in that the described recessed surface of described matrix area is a smoothing surface that is lower than the described exposing surface of described substrate.
7, install according to claim 1, it is characterized in that, matrix area has a section of U type substantially.
8, device according to claim 1 is characterized in that described device more comprises a shallow doped region, is arranged in the described matrix area and adjacent to described source area but non-conterminous in described matrix contact zone.
9, a kind of manufacture method of semiconductor device, described semiconductor device is applicable to high voltage operation, described method comprises:
Semi-conductive substrate is provided, is provided with a trap in it, wherein said Semiconductor substrate has one first conductivity, and described trap has one second conductivity and an exposing surface in contrast to described first conductivity;
Form a plurality of isolation structures on the surface of described Semiconductor substrate, one of wherein said isolation structure is on the described Semiconductor substrate that is formed in the described trap;
A screen that forms patterning is on described Semiconductor substrate, to expose the described isolation structure that is positioned at described trap;
Carry out an ion implantation step, as etch mask, form a matrix area with the below of the described isolation structure in described trap with described screen, described matrix area has one first conductivity;
Carry out an etching step, as etch mask, etching is removed the described isolation structure in the described trap with described screen, and to expose described matrix area, wherein said matrix area has a recessed surface that is lower than contiguous described Semiconductor substrate;
Remove described screen;
Form a grid stacking material of patterning, part covers the described recessed surface of described matrix area and the surface that is close to the described trap of described matrix area;
Form an one source pole district and a drain region in the part of described matrix area and in the part of described trap respectively, wherein said source area and described drain region are not covered by described grid stacking material and are had described second conductivity; And
Form a matrix contact zone in another part of described matrix area, described matrix contact zone is adjacent to described source area and do not covered by described grid stacking material and have described first conductivity.
As method as described in the claim 9, it is characterized in that 10, described first conductivity is P-type conduction and described second conductivity is N type conductivity.
11, as method as described in the claim 9, it is characterized in that described matrix area does not contact described isolation structure.
As method as described in the claim 9, it is characterized in that 12, the dopant concentration in described source area and the described drain region is higher than the dopant concentration in the described trap, and the dopant concentration of described matrix contact zone is higher than the dopant concentration in the described matrix area.
13, as method as described in the claim 9, it is characterized in that described grid stacking material has a non-smooth surface.
14, as method as described in the claim 9, it is characterized in that the described recessed surface of described matrix area is a smoothing surface.
As method as described in the claim 9, it is characterized in that 15, matrix area has a section of U type substantially.
16, as method as described in the claim 9, it is characterized in that, form respectively in the part of described matrix area and in the part of described trap before described source area and the described drain region, more be included in the step that forms a shallow doped region in the described matrix area, described shallow doped region has described second conductivity and is not covered by described grid stacking material.
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| CN200810127254A CN101621072A (en) | 2008-06-30 | 2008-06-30 | Semiconductor device and manufacture method thereof |
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| CN200810127254A CN101621072A (en) | 2008-06-30 | 2008-06-30 | Semiconductor device and manufacture method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN109545853A (en) * | 2017-09-21 | 2019-03-29 | 新唐科技股份有限公司 | semiconductor substrate structure and semiconductor device |
| CN109599439A (en) * | 2017-12-28 | 2019-04-09 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor field effect transistor |
-
2008
- 2008-06-30 CN CN200810127254A patent/CN101621072A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN102738215B (en) * | 2011-08-18 | 2015-07-29 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN109545853A (en) * | 2017-09-21 | 2019-03-29 | 新唐科技股份有限公司 | semiconductor substrate structure and semiconductor device |
| CN109599439A (en) * | 2017-12-28 | 2019-04-09 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor field effect transistor |
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